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[23.128.96.31]) by mx.google.com with ESMTPS id j13-20020a170902da8d00b001b9d5f07068si6866220plx.585.2023.09.20.11.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 11:06:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Drsvbd7B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 7E3FC82F9150; Wed, 20 Sep 2023 08:46:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236806AbjITPqh (ORCPT + 27 others); Wed, 20 Sep 2023 11:46:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236768AbjITPqf (ORCPT ); Wed, 20 Sep 2023 11:46:35 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FE00C9 for ; Wed, 20 Sep 2023 08:46:28 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-69101022969so28202b3a.3 for ; Wed, 20 Sep 2023 08:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695224788; x=1695829588; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sAr/f3EP2NDO5TcbIFTZtzzZHLVf3n++r+Cj6Pd3+Fs=; b=Drsvbd7BiH5l19WrmmwzoEKJC8NtpPdS0J9DbFak31f859CyaM6sOmnUBMDp/IfL1F LkJ5jteocsE2/eQBBmGI9+fDXDxTR7EbIwNIr1Bzsb+oidwi2oqYqFwN1ki2jk1CNGgz gPXgEMAJ2R35uCLOUn6qRKZU6vrWFLf7kyincqCPQ6NgH8cpf7BNzIwpaZv+8bgVvKqq UXF9DYK/3uZvaKEe3AF0xPCHYdr8qkVSUo1nLUe+bdQMTfiNPXLMoqr6MeuNXvYu+pva YJ1Ky/7r9zVEZVb4PEgymE0HF8ibqr4rV9kS9nmDK7xgrkIwJXjPB2GQXdkUGmtnTtoD JPRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695224788; x=1695829588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sAr/f3EP2NDO5TcbIFTZtzzZHLVf3n++r+Cj6Pd3+Fs=; b=ftJAecQvvhOTPiY3CSvlva9oQ63TcbhaIMJoMn35PXaPLvWgUVNgksOR7y6/Bce10Y XhHr6+P5l8YNmIwJ8QpkUFEfBU4AvNFxXEkTXy4W0kAExYSBBkSJcFcr1/fClga/gD7A leH9YrcopcrkxPOsP6VJKjimeZU2/C8NABtvqGQJ+3EIuJm2MzGMKsda1JCIt2s8Oc9t kQklb4vRauymqEZH54ljD6yLuxvyr8op4zkVEzw0XmOChbgA47M9r/+xTZh1Px5yISRW CaIZQ75y4l3lUOx5TdjGbp+yK5zWOfsfZSLw+GmLrNKN7ABPYD7XJA6VlHbc7gqn/uKn YL4g== X-Gm-Message-State: AOJu0YxJU0evIO7sS/wyqqFmaIQeB52fkgaIT3MFIXtY3L63eEeMf++R 343WoLoawY7lNKy5rAS+sUqXEQ== X-Received: by 2002:a05:6a20:8410:b0:12e:5f07:7ede with SMTP id c16-20020a056a20841000b0012e5f077edemr3874367pzd.41.1695224787947; Wed, 20 Sep 2023 08:46:27 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.85.109]) by smtp.gmail.com with ESMTPSA id m7-20020a170902db0700b001c0de73564dsm11995153plx.205.2023.09.20.08.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 08:46:27 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v2 1/4] RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers Date: Wed, 20 Sep 2023 21:16:05 +0530 Message-Id: <20230920154608.1447057-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920154608.1447057-1-apatel@ventanamicro.com> References: <20230920154608.1447057-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 20 Sep 2023 08:46:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777580821600743502 X-GMAIL-MSGID: 1777580821600743502 The ISA_EXT registers to enabled/disable ISA extensions for VCPU are always available when underlying host has the corresponding ISA extension. The copy_isa_ext_reg_indices() called by the KVM_GET_REG_LIST API does not align with this expectation so let's fix it. Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support") Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_onereg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 1b7e9fa265cb..e7e833ced91b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -842,7 +842,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu, u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; isa_ext = kvm_isa_ext_arr[i]; - if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext)) + if (!__riscv_isa_extension_available(NULL, isa_ext)) continue; if (uindices) { From patchwork Wed Sep 20 15:46:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 142780 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4711642vqi; Thu, 21 Sep 2023 02:16:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHwjt/zRSFzCsUb5fQt1tcHoqXnVht9ktK1iD/oG65l/6FlPEKfnqsWewsjL9v6eCTv1QSf X-Received: by 2002:a17:90a:b118:b0:275:4103:6adc with SMTP id z24-20020a17090ab11800b0027541036adcmr5029233pjq.43.1695287766459; Thu, 21 Sep 2023 02:16:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695287766; cv=none; d=google.com; s=arc-20160816; b=bOnGDQVgxee4fqSpY97YdEBu81fkQ6m0JlfQOKrPgpwmgOsxgdTGN+yGLQH5sY1rd+ +c1MbAa9Qlv4sHK7FLts1Wh0oJzA4Oan4G8W0Cpd3VFPNZA7qy8OWzNVqzQDdGeuQDRZ piMH2dKQmLtgJ5oOuWiCsLE5o8I++XJWYc2K1uzFRxYccslCazasA4p+q8g9jwuyicjB AtBMgBB/wcBt4IpjH4S51D0LegLvRvb6x3gM072hZjxB9KhqH0o0QIqNcs08QKTK7mt/ K4EA8dYCKH2rm2L/Z8WiKNrYb+2MRLaTaY2M9Y1NtWBfsE7Yqov8QjlTjFn4cqJB8hLL IdUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0WW4VSH0fAhQvFEKg4libvP4KxfqhgcxX9zTpJuWWZQ=; fh=665Qm2DFjeImEVP2NCXef/1YQ8IF0QpHIEyBqpmie5I=; b=N7iHsTQgXJEXY60USlBZGg2Bg/zvOaAa6K7EH9I7BNvNrdK0mKpI+JnuE4dbUocvGU WrlAxyrnDhHqZHyIdR17fSS6iT2YDtFjg/mx3qyYLQKz311F1E76//ajX3t0IbNDqbD3 5xfS7Va3x2m/Bpdbnwmf9NRLRQjxupaAw73+kB5F8VNrW3+G/SuSJ0rqoYc7gE+6VinP nxYgWAGFt1IlLeTLw/ST8uU4jOH42+byhDzY0YiPxAhVfSslcTNXbnTNy5dmvH5D8BRs XjpgJOS7P5JOTmj3s5q+spYxgZUzhyFgDDbAZmHQgCiliwM1Yx6OkEELYBV/aTU/ey/i owwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JTE3Q4KZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Fixes: e98b1085be79 ("RISC-V: KVM: Factor-out ONE_REG related code to its own source file") Signed-off-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_onereg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index e7e833ced91b..b7e0e03c69b1 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -460,8 +460,11 @@ static int riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) return -ENOENT; - *reg_val = 0; host_isa_ext = kvm_isa_ext_arr[reg_num]; + if (!__riscv_isa_extension_available(NULL, host_isa_ext)) + return -ENOENT; + + *reg_val = 0; if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) *reg_val = 1; /* Mark the given extension as available */ From patchwork Wed Sep 20 15:46:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 142603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4424103vqi; Wed, 20 Sep 2023 14:04:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGDu0KEYj0S31D2u/6As2gN6smR4f5vhZhi0DvA0OeugVOR+RGkPC6NkUVW9Y6+6M+OZLiP X-Received: by 2002:a17:90a:d252:b0:26d:1f3d:6e85 with SMTP id o18-20020a17090ad25200b0026d1f3d6e85mr3618381pjw.37.1695243841951; Wed, 20 Sep 2023 14:04:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695243841; cv=none; d=google.com; s=arc-20160816; b=ewX8Xfsk97sZgQzNoVVNp2OvOQ3gFDba3iHrOKkfYaKqEeP2avBOjY3wxu8s+clJyI PQpmqinkCHRooC9JTzacCLUW9Ffh9g2+LzgjL+bUhEMLiYDTPinJ/DxtdpKR/NxA0bkf 5a2ndXZ8OKEKN0HCXokySeQdfepH376OEdUUTEbqdhU3K4MKMCuqw3Gf+j2IPX9Mjc2A tiz6SJKy3EZom/8QeUWetX+Gqx58JanCFLVcBVZKbf+qe/m3MSoV/Mb7YwXcfwZvdmVY hdPpdjvewBT/rr29sJ9llwskmvYIMaEQFuts9/1XTeMQxTHUFaIpuPY6oeH+xk7wfKwq eeQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/2F/KgrFF+qMw0t/vo/nHoae6ojEjBo+38MWpMzETGM=; fh=2S+54NKBCousR9yNCeiEbYlRCvnfU9LmKXxbaD6jKe8=; b=hczp6a9VgON1I6RMvbDkTpXkFXRZNnVOo5NgTPO8ekOo2IdkbRNPUstJlVC1St01FY 6NWa5No6O2ceKkz6Zlvf2Rvqh+YWoOnUqTzRyXP9iSMsK0SopGenZ2Bm9v8WuVnu5YHm JpNyfLyIFzv832Sv7VAAU+tQtkhexjwSxMi2j/NVK5bpcXTmmcVh0uYUQvH+oPrG/z0F TUNGUNDG2Bh1CyrjFz8aCqM1PBDHtMprHN32VaxjgwtFkCY6dth8M+heK7OXnkkw2bM9 JehmpAVnIT3SwgOMyVeorB9jD0xN+2cAZkCrStnhatlpjbsm7+tXSchOGFVag5vDCRTT 1XEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aphcHNEY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Also, disabling an ISA extension using corresponding ISA_EXT register does not affect the visibility of the ISA_EXT register itself. Based on the above, we should filter-out all ISA_EXT registers. Fixes: 477069398ed6 ("KVM: riscv: selftests: Add get-reg-list test") Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- .../selftests/kvm/riscv/get-reg-list.c | 35 +++++++++++-------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index d8ecacd03ecf..76c0ad11e423 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -14,17 +14,33 @@ bool filter_reg(__u64 reg) { + switch (reg & ~REG_MASK) { /* - * Some ISA extensions are optional and not present on all host, - * but they can't be disabled through ISA_EXT registers when present. - * So, to make life easy, just filtering out these kind of registers. + * Same set of ISA_EXT registers are not present on all host because + * ISA_EXT registers are visible to the KVM user space based on the + * ISA extensions available on the host. Also, disabling an ISA + * extension using corresponding ISA_EXT register does not affect + * the visibility of the ISA_EXT register itself. + * + * Based on above, we should filter-out all ISA_EXT registers. */ - switch (reg & ~REG_MASK) { + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_F: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: @@ -50,12 +66,7 @@ static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) unsigned long value; ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value); - if (ret) { - printf("Failed to get ext %d", ext); - return false; - } - - return !!value; + return (ret) ? false : !!value; } void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) @@ -506,10 +517,6 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI, From patchwork Wed Sep 20 15:46:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 142685 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4546278vqi; Wed, 20 Sep 2023 18:38:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGCun/NMAx3JRH2gZz14y642T3ePTibySDc5atgFDVs7x9srTcEtXBWndcQ+YZD3ECTZO/v X-Received: by 2002:a05:6a00:1a87:b0:690:454a:dc7b with SMTP id e7-20020a056a001a8700b00690454adc7bmr4678601pfv.28.1695260313446; Wed, 20 Sep 2023 18:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695260313; cv=none; d=google.com; s=arc-20160816; b=xNFcDkyYqjM6pbkJM2cXGSEmVGznkAa6kzsRLGm7umcVr+X4mzzrldbaQJkJWfFYGh kCkKVHBCPfdWDWbsYM8pcCZw3MUGnILfioMsLbgOBXVSN1SFCj2hD5lMa6myk6LIJnwI /myeudpi3Z7hQjKJAWT5mlzPFswEO67jtS/Ys3jXaC90oQExFCAMpt7hxCJ+g649IrN1 AdNi0ZUHCae8MoxSV1a0KwSkD4BEzVHzjCaCsaY6o3UqbMBHXlCb08qR1umy1Nc81EVb 6XV61yRSRTx3m+YERnx8BOoIM/4UGZ5FgL6wKso28PKghWmdysXkHoxp7SLcu2Xy63xl Kjzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JEpzhn0/r3h7zE+n/9TA9uRn8epPj0d0ldcwcNh6iPI=; fh=665Qm2DFjeImEVP2NCXef/1YQ8IF0QpHIEyBqpmie5I=; b=nuINCn1Zgxiw/VmisQza3mAw7cKEEHXYfXN/3NITR58cj6IEMwlZXcnMH1gNpTy1fu /+d1VagjAeiWuSm8kUBCXV/fYhMhS0blJjerH7/Gi84e/ozePamw2/lL5BdCilL9Bn4B QfT8xIM3z2utzUqRFOEzlul9R9jCRkJt7bcj+Fx+8naGntDbv49KPRDyuXQ5ty9Nhdus aRCQH9Fv9xpeUTFjPc9o76CLERermbDkA7CQ/aLRbb8IwLAk7Q2kbsEQDEtgTgliHDI3 ShnY12sHYxqxCkqhQFMgVKW8w6opthfwHYOE3/HoLnrgp/1EM2K0mnc8SOS3bUfGx9NX PatA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=pnsIS2+M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id ca17-20020a056a00419100b0068fca4405aasi356180pfb.338.2023.09.20.18.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 18:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=pnsIS2+M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 3336B81BAF0F; Wed, 20 Sep 2023 08:47:03 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236845AbjITPqu (ORCPT + 27 others); Wed, 20 Sep 2023 11:46:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236814AbjITPqr (ORCPT ); Wed, 20 Sep 2023 11:46:47 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B934CF2 for ; Wed, 20 Sep 2023 08:46:40 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1c5cd27b1acso972005ad.2 for ; Wed, 20 Sep 2023 08:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695224800; x=1695829600; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JEpzhn0/r3h7zE+n/9TA9uRn8epPj0d0ldcwcNh6iPI=; b=pnsIS2+MTr2syyrsxFZt/NPneM/jbrZM+vk1hWMRdcktLCahZ5qNh6DdmvHWfLanSC dMQoxCi0zx9jP7VvVr56THiz0lVK53+LZwo918oBaWIKxGP2IhN0ZqEEvboE/P39Ae+p xjvUwmA3QiXbuJ1Ao389VLBWeiLw8qa7eWlfXdYadW/5ftumg9+MEE0IkVlazRqrhqPK +Vt6+ZUldom8MdnnhmP7fWC6M62qLLlUgYToMcobwhptAeFgTP//T5KHqO/QJdrWufg4 3Uz5LPOmZBwhemVi5dy9akfH6dEJxTvghjgY8ClQcigL77zLBFivRv6Vqfjw3iyOWtG0 bs5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695224800; x=1695829600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JEpzhn0/r3h7zE+n/9TA9uRn8epPj0d0ldcwcNh6iPI=; b=JMFSkflSeLL2E+ev1E35QwbRzURfZADeMzQpv93ExGf7hNHxp1mYfqOfGJmt03SdLY z7MEUEo4hPA9MzhdzerneR2S2sR4GYralyVsUz+bvT1TH+CNa9IjSmAWU99J+OsdKGsD ae/FzESP8eEmVy2WIZjLa02zcYAg8Sy1Melpd/al6eXTIG/dLL19ODT0+86MaIvVMMF1 X4tbp3ZO/rAD7MZZX/+y+adtJnUx6Px543409ooaznCN4xjNXIJRN0bdgcMtpCpZeZ3z Xh5/GnGywg6c4WtDx+B2VDJuCd+WhfD+TB557sUi/JI5mbjBYY5A6MVGelMiftHIhP7+ +mAA== X-Gm-Message-State: AOJu0YyEJtjYGqGIey3x9nGWOP8Lv+QWwr0FP8IvXnC4Vto7hVYV4phV JagBNLDmNUe02Eel5Yt3l5nsow== X-Received: by 2002:a17:902:c142:b0:1c4:bc8:4b64 with SMTP id 2-20020a170902c14200b001c40bc84b64mr2711290plj.5.1695224799935; Wed, 20 Sep 2023 08:46:39 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.85.109]) by smtp.gmail.com with ESMTPSA id m7-20020a170902db0700b001c0de73564dsm11995153plx.205.2023.09.20.08.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 08:46:39 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v2 4/4] KVM: riscv: selftests: Selectively filter-out AIA registers Date: Wed, 20 Sep 2023 21:16:08 +0530 Message-Id: <20230920154608.1447057-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920154608.1447057-1-apatel@ventanamicro.com> References: <20230920154608.1447057-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 20 Sep 2023 08:47:03 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777589871805674959 X-GMAIL-MSGID: 1777609278508986862 Currently the AIA ONE_REG registers are reported by get-reg-list as new registers for various vcpu_reg_list configs whenever Ssaia is available on the host because Ssaia extension can only be disabled by Smstateen extension which is not always available. To tackle this, we should filter-out AIA ONE_REG registers only when Ssaia can't be disabled for a VCPU. Fixes: 477069398ed6 ("KVM: riscv: selftests: Add get-reg-list test") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- .../selftests/kvm/riscv/get-reg-list.c | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 76c0ad11e423..9f99ea42f45f 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -12,6 +12,8 @@ #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK) +static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; + bool filter_reg(__u64 reg) { switch (reg & ~REG_MASK) { @@ -48,6 +50,15 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: return true; + /* AIA registers are always available when Ssaia can't be disabled */ + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): + return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; default: break; } @@ -71,14 +82,22 @@ static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { + unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; struct vcpu_reg_sublist *s; + int rc; + + for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) + __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); /* * Disable all extensions which were enabled by default * if they were available in the risc-v host. */ - for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) - __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); + for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { + rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); + if (rc && isa_ext_state[i]) + isa_ext_cant_disable[i] = true; + } for_each_sublist(c, s) { if (!s->feature)