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Wed, 20 Sep 2023 07:04:16 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_=A0ipraga__=3Calsi=40bang-oluf?= =?unknown-8bit?q?sen=2Edk=3E?= Cc: Sebastian Hesselbarth , Rabeeh Khoury , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: clock: si5351: convert to yaml Date: Wed, 20 Sep 2023 15:09:53 +0200 Message-ID: <20230920140343.2329225-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920140343.2329225-1-alvin@pqrs.dk> References: <20230920140343.2329225-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 20 Sep 2023 07:05:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777568898727855060 X-GMAIL-MSGID: 1777568898727855060 From: Alvin Šipraga The following additional properties are described: - clock-names - clock-frequency of the clkout child nodes In order to suppress warnings from the DT schema validator, the clkout child nodes are prescribed names clkout@[0-7] rather than clkout[0-7]. The latter form is still admissible but the example has been changed to use the former. The example is refined as follows: - correct the usage of property pll-master -> silabs,pll-master - give an example of how the silabs,pll-reset property can be used I made myself maintainer of the file as I cannot presume that anybody else wants the responsibility. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.txt | 126 --------- .../bindings/clock/silabs,si5351.yaml | 251 ++++++++++++++++++ 2 files changed, 251 insertions(+), 126 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index bfda6af76bee..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml new file mode 100644 index 000000000000..3ca8d998c48c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5351A/B/C programmable I2C clock generators + +description: | + The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to + 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 + output clocks are accessible. The internal structure of the clock generators + can be found in [1]. + + [1] Si5351A/B/C Data Sheet + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf + +maintainers: + - Alvin Šipraga + +properties: + compatible: + enum: + - silabs,si5351a # Si5351A, 20-QFN package + - silabs,si5351a-msop # Si5351A, 10-MSOP package + - silabs,si5351b # Si5351B, 20-QFN package + - silabs,si5351c # Si5351C, 20-QFN package + + reg: + enum: + - 0x60 + - 0x61 + description: | + I2C address of the clock generator + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + + silabs,pll-source: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + description: | + Pair of for each PLL. Allows to overwrite clock source of + PLL A (number=0) or PLL B (number=1). + +patternProperties: + "^clkout@?[0-8]$": + type: object + + properties: + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Clock output number. + + clock-frequency: + $ref: /schemas/clock/clock.yaml#/properties/clock-frequency + + silabs,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Source clock of the this output's divider stage. + + 0 - use multisynth N for this output, where N is the output number + 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4 + (otherwise) for this output + 2 - use XTAL for this output + 3 - use CLKIN for this output (Si5351C only) + + silabs,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 6, 8] + description: Output drive strength in mA. + + silabs,multisynth-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Source PLL A (0) or B (1) for the corresponding multisynth divider. + + silabs,pll-master: + type: boolean + description: | + The frequency of the source PLL is allowed to be changed by the + multisynth when setting the rate of this clock output. + + silabs,pll-reset: + type: boolean + description: Reset the source PLL when enabling this clock output. + + silabs,disable-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Clock output disable state. The state can be one of: + + 0 - clock output is driven LOW when disabled + 1 - clock output is driven HIGH when disabled + 2 - clock output is FLOATING (HIGH-Z) when disabled + 3 - clock output is never disabled + + allOf: + - if: + properties: + compatible: + contains: + const: silabs,si5351a-msop + then: + properties: + reg: + minimum: 0 + maximum: 2 + else: + properties: + reg: + minimum: 0 + maximum: 7 + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + silabs,clock-source: + enum: [0, 1, 2, 3] + else: + properties: + silabs,clock-source: + enum: [0, 1, 2] + required: + - reg + + additionalProperties: false + +allOf: + - $ref: /schemas/clock/clock.yaml + - if: + properties: + compatible: + contains: + enum: + - silabs,si5351a + - silabs,si5351a-msop + - silabs,si5351b + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: xtal + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: xtal + - const: clkin + +required: + - reg + - "#address-cells" + - "#size-cells" + - "#clock-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + si5351a: clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* Connect XTAL input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* Use XTAL input as source of PLL0 and PLL1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* + * Overwrite CLK0 configuration with: + * - 8 mA output drive strength + * - PLL0 as clock source of multisynth 0 + * - Multisynth 0 as clock source of output divider + * - Multisynth 0 can change PLL0 + * - Set initial clock frequency of 74.25MHz + */ + clkout@0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * Overwrite CLK1 configuration with: + * - 4 mA output drive strength + * - PLL1 as clock source of multisynth 1 + * - Multisynth 1 as clock source of output divider + * - Multisynth 1 can change PLL1 + * - Reset PLL1 when enabling this clock output + */ + clkout@1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + silabs,pll-reset; + }; + + /* + * Overwrite CLK2 configuration with: + * - XTAL as clock source of output divider + */ + clkout@2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; + }; From patchwork Wed Sep 20 13:09:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 142489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4219704vqi; Wed, 20 Sep 2023 08:22:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEXJfWwGzOyPXVsSBOKbZxKZgkvGfMLinKIGv6t7KFxwoMFza3hT46rbOexnn1KRNVe73eO X-Received: by 2002:a17:90a:be11:b0:273:ed61:a682 with SMTP id a17-20020a17090abe1100b00273ed61a682mr2919196pjs.1.1695223377317; Wed, 20 Sep 2023 08:22:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695223377; cv=none; d=google.com; s=arc-20160816; b=c/SwJzph7hsZessUHT5uPjWPUqYEQ2dEe4nhKBo2mXe+9zdBxug4YzrF81KZ9Zghjq jRq1OSgvywtX/wB9mlrBfPh0VZkw9vVgp4GQ2Msxdr8BEoIb0qhtylxNUBD8X8sJjq/g AcuUJxVrI184topcvZJHp99WCOL+yypQfFSrWC8nwPp3IAtqxsQD0+8m+OGtko0ky3PJ Aq1HttV0L1FxmQu2HbYpkgAAhKVIumr7p4tfZ0W5ZE6KrfxnwX0yDzRizuBgN/DDm+DM AUVZBCIkAHNZRgjiWfqz7+VKp378/o6TdvWPrtKV76sPswMZG+AuMday3heTAqs35CLO F3Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=b+1FYQtXao8Yw3xmiSSXbsCd2slRgXlF0cJKkQ9uwuw=; fh=KyFBUXcuM6fUgur5yAGjxy8UwwGrnAi0qyRlE0N5PJo=; b=Rn1RMFxpDcrjKBzMdO9qiPES/gt1CV9TrQAw5zLDjEaW9GpErZqQ8vpSkSPokDUxh+ fRTIwPxVDbwi0GALtRHlIn8q3kS+9U7PDouuCcc3yvhF6LormZhSX4iLJmsfZ+DgGyQY 10ho82XV84K34dXqcIcdZrzu/yUXzLmNI44ldzM700y+6dJGBL2dHN3LhipeY0liA5Tc a4DXmp8hK8DbjaKKpV7lHCfWH6JSZV2O9px5rqLaOMz4EJtvr/rxodRecpwD+hPMPeeZ xaMeEOnd2wMqGwGzM1eEq7SdJflo6583piQD86Xeafb+N1MPZOreddZ6iXFjO72FI6Cz g/CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=fvWGL1FD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. 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Wed, 20 Sep 2023 07:04:18 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_=A0ipraga__=3Calsi=40bang-oluf?= =?unknown-8bit?q?sen=2Edk=3E?= Cc: Sebastian Hesselbarth , Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: clock: si5351: add PLL reset mode property Date: Wed, 20 Sep 2023 15:09:54 +0200 Message-ID: <20230920140343.2329225-3-alvin@pqrs.dk> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920140343.2329225-1-alvin@pqrs.dk> References: <20230920140343.2329225-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 20 Sep 2023 07:05:13 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777570547839489460 X-GMAIL-MSGID: 1777570547839489460 From: Alvin Šipraga For applications where the PLL must be adjusted without glitches in the clock output(s), a new silabs,pll-reset-mode property is added. It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml index 3ca8d998c48c..b6692b323a66 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -50,6 +50,22 @@ properties: Pair of for each PLL. Allows to overwrite clock source of PLL A (number=0) or PLL B (number=1). + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + description: | + Pair of for each PLL. Configures the reset mode for PLL A + (number=0) and/or PLL B (number=1). Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is specified in + one of the clock output child nodes that also sources the PLL. This mode + may be preferable if output clocks are expected to be adjusted without + glitches. + patternProperties: "^clkout@?[0-8]$": type: object @@ -205,6 +221,9 @@ examples: /* Use XTAL input as source of PLL0 and PLL1 */ silabs,pll-source = <0 0>, <1 0>; + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode = <1 1>; + /* * Overwrite CLK0 configuration with: * - 8 mA output drive strength From patchwork Wed Sep 20 13:09:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 142574 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4391530vqi; Wed, 20 Sep 2023 13:01:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHWt94mDvHVv30+lopamjL4BuuWW/p50C9iVApTLHDhkLWVMcDyVxHTrNi26zi5lGbRB4ze X-Received: by 2002:a17:903:24c:b0:1bb:b86e:8d60 with SMTP id j12-20020a170903024c00b001bbb86e8d60mr4174910plh.46.1695240109522; Wed, 20 Sep 2023 13:01:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695240109; cv=none; d=google.com; s=arc-20160816; b=l2O868dhtgDvMYXv5bIue780sobLe0PppwBQHd2p43dRo4sYmMtyZeW8QFW5BKbW8K Vx8sLXEwlknHXLUCGeIbl8R38D2E2osiOPZqGo1/iPFeNjr4lS254tVpdsGsO9kRZsiw BKDYuab5U9PlkfVptwhmESAQ4F50Zl7CZSkPHlKZbR1+J7VncT2JnSHT27p1FWitqJ7N QAZjPz2AxRhLD6rwrip09Sp9u48Ra9aRvLmf8OZaaClV+zM+t6QcJhBuy/xvk/Va+I0j 9dg6NgEMAyH2zqiqQ0zcDsmV9x7gRd1P7rYdGba46W7mm7BBz/jKystjcMJzDTQyntRi 9NlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DWkKzE4Z8RDrXV6wrMgsXOyr17/u+hWk6l6i8+o41y0=; fh=KyFBUXcuM6fUgur5yAGjxy8UwwGrnAi0qyRlE0N5PJo=; b=my7u27ybhq/b90lol0ScCa3Qoap/QPejXhs0eQz7LVH4GWVLgqcoQXqvvpdavbKsn9 zvQR+ib6FR4nhdqdy63/Wd4OKRP0Lx8mc5zXMgvMCFCYo58b0+2+xtAQy+oOB/m8lQdy bXpQLcD8wmLZPi4ggx/561yFRBBIdAfVjQzI2NDGZdTNryac9v6i9pJwX8vByak918s9 vc1v2xAJi0FDg43Uu3AisYkA/8wKc6Nh6mCu4M9DZnlmS8BuhjfChinHYB0VaWAbI843 agdOMU54+6HeVN/N6j7YTwotV5oWfWAcHwYkw3p0uHEemnOQii4CRJYQf4g+cED6YZmb irOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=em1W+8KZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. 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Wed, 20 Sep 2023 07:04:21 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_=A0ipraga__=3Calsi=40bang-oluf?= =?unknown-8bit?q?sen=2Edk=3E?= Cc: Sebastian Hesselbarth , Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] clk: si5351: allow PLLs to be adjusted without reset Date: Wed, 20 Sep 2023 15:09:55 +0200 Message-ID: <20230920140343.2329225-4-alvin@pqrs.dk> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920140343.2329225-1-alvin@pqrs.dk> References: <20230920140343.2329225-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 20 Sep 2023 07:05:27 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777588093100889102 X-GMAIL-MSGID: 1777588093100889102 From: Alvin Šipraga Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga --- drivers/clk/clk-si5351.c | 47 ++++++++++++++++++++++++++-- include/linux/platform_data/si5351.h | 2 ++ 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 00fb9b09e030..95d7afb8cfc6 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index c71a2dd66143..5f412a615532 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -105,10 +105,12 @@ struct si5351_clkout_config { * @clk_xtal: xtal input clock * @clk_clkin: clkin input clock * @pll_src: array of pll source clock setting + * @pll_reset: array indicating if plls should be reset after setting the rate * @clkout: array of clkout configuration */ struct si5351_platform_data { enum si5351_pll_src pll_src[2]; + bool pll_reset[2]; struct si5351_clkout_config clkout[8]; };