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Wed, 20 Sep 2023 02:46:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777558262297823315 X-GMAIL-MSGID: 1777558262297823315 From: Vitaly Lubart Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 39d7b0740bf0..4cbc3062cb9a 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) From patchwork Wed Sep 20 09:41:49 2023 Content-Type: text/plain; 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Add has_heci_gscfi indication to xe_device and xe_pci structures. Mark DG1 and DG2 devices as supported. Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/xe_device_types.h | 3 +++ drivers/gpu/drm/xe/xe_pci.c | 9 +++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index a82f28c6a3a0..696416afa7d1 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -33,6 +33,7 @@ struct xe_ggtt; #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) #define IS_DGFX(xe) ((xe)->info.is_dgfx) +#define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) #define XE_VRAM_FLAGS_NEED64K BIT(0) @@ -238,6 +239,8 @@ struct xe_device { u8 has_link_copy_engine:1; /** @enable_display: display enabled */ u8 enable_display:1; + /** @has_heci_gscfi: device has heci gscfi */ + u8 has_heci_gscfi:1; #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) const struct intel_display_device_info *display; diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index dc233a1226bd..145eaa430d74 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -57,6 +57,7 @@ struct xe_device_desc { u8 require_force_probe:1; u8 is_dgfx:1; u8 has_display:1; + u8 has_heci_gscfi:1; u8 has_llc:1; }; @@ -265,6 +266,7 @@ static const struct xe_device_desc dg1_desc = { PLATFORM(XE_DG1), .has_display = true, .require_force_probe = true, + .has_heci_gscfi = 1, }; static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 }; @@ -274,6 +276,7 @@ static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 }; #define DG2_FEATURES \ DGFX_FEATURES, \ PLATFORM(XE_DG2), \ + .has_heci_gscfi = 1, \ .subplatforms = (const struct xe_subplatform_desc[]) { \ { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ @@ -562,6 +565,7 @@ static int xe_info_init(struct xe_device *xe, return -ENODEV; xe->info.is_dgfx = desc->is_dgfx; + xe->info.has_heci_gscfi = desc->has_heci_gscfi; xe->info.graphics_name = graphics_desc->name; xe->info.media_name = media_desc ? media_desc->name : "none"; xe->info.has_llc = desc->has_llc; @@ -703,7 +707,7 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) xe_display_info_init(xe); - drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d", + drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d", desc->platform_name, subplatform_desc ? subplatform_desc->name : "", xe->info.devid, xe->info.revid, @@ -715,7 +719,8 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) xe->info.media_verx100 / 100, xe->info.media_verx100 % 100, str_yes_no(xe->info.enable_display), - xe->info.dma_mask_size, xe->info.tile_count); + xe->info.dma_mask_size, xe->info.tile_count, + xe->info.has_heci_gscfi); drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n", xe_step_name(xe->info.step.graphics), From patchwork Wed Sep 20 09:41:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Usyskin, Alexander" X-Patchwork-Id: 142399 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4123963vqi; Wed, 20 Sep 2023 06:05:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG4m9tQxrZ/QRqXVJkeicoU5azaAc1WeaO8wEbvhwRRaOe1yRzMDV6dwEzvb9JUyVvoBQJJ X-Received: by 2002:a17:902:d702:b0:1c0:774d:9342 with SMTP id w2-20020a170902d70200b001c0774d9342mr2033719ply.25.1695215128642; Wed, 20 Sep 2023 06:05:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695215128; cv=none; d=google.com; s=arc-20160816; b=SkNV1yeJjBp7iAdkAj6tZ3FX1jbOPw/zskGyRjX9iJdbdezl/Fex/RKwgnKY4FrneF nVu/n1FzNorrHAYkifFAZDoZRpaUEeLvq1TVIB5v0OaamRpd+REj0jnUSPRtNcz/13UL 5BikYWR9wQI8WwlwHqSdbNzuWz6AyQROIv+nSCrdAQoexqS6MH5ZOBQfqR9nedeky1Kn mpKIes6dk5txYFbNRGJvMasOiepqQOCTy54cNWsDZjEFXtmWMJPcvi3NUSlm2fOgUd13 vLy2UjCVvbWOJvZEdYbN92SHMNVeI2ewpNJstW46wSjcPR02JiuC1Qu6SXgk5nUESec4 f8AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0TR/UqmhhvY2AYBF/BtEdyIakTdX03Sez52OrgM13A4=; fh=7xjKU1xkhmTazBlAQtMk+Chl7JSt/CUyagAgyiLWmTI=; b=bNfAoFFMUIAysT+JwF/3cY7n8zPaWnv9qWsQ1qeOUA+Lx1mg3/hjK4hxI5Np9SfUMv Exku/k4u+Sj0ChwROdmybDgZyDnIC85dZ0v9ZvNQwk8EHAbnNoRkJ8VEkOO/KmfT7ehn l9R+wQfxpQr8S6bb7rp5mDyHkNLIWtf53jQZCmVvHdHDNxqh6U9srnPRMMK/tqR/u4ZH Vy7u//jn6M6zeaKZmH3ZRJ7tLNn6SJ4GeAU2n7IqPwOnwbegxbxSTbe+ASEBEDN/MQS8 cSDHac95SBucndanuq1ZZplQm4G815k8wYeI7fZeWbkRW9YsnRHThifmQFfGRewe6ZuK FwDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oAeluAgr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id z9-20020a170903018900b001c5841b16c8si4508192plg.145.2023.09.20.06.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 06:05:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oAeluAgr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 938C081129AB; Wed, 20 Sep 2023 02:46:42 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234235AbjITJqf (ORCPT + 26 others); Wed, 20 Sep 2023 05:46:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234221AbjITJq1 (ORCPT ); Wed, 20 Sep 2023 05:46:27 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 023F3AB for ; Wed, 20 Sep 2023 02:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695203180; x=1726739180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kb/MqG+8hGs7sJxn6q18Pz8fc9ZzXNKF2rq4JnktHB4=; b=oAeluAgryQIi/gTPCBKlPGKwQiSVw7cJqIPTTzIc4SJ+fhSITeUuiVGc zu0V0HORfnSTr8C3tvq+2ghFUrhuEm9J5+Ntv93wgHo6lqbMsZBhQ9MlK BiTyLtoAvns8r2IowSBL6WQNQBeJyO09UWkuELQj1UE6QTOWRhurNfmu9 AdleJEPh+Y5ZKuoCy0U90Fp/fIi+/3RP6luzzz8vCgEl5GxGbj6MnvadU +DpO03wh5Gj4reFk6r+GX4jJxHyTIXHHkXVm8tFPvjHqm5WiD9v/CFdgs gJy4tFyZlpZe1FeocjYsukUByJhU+zwcUY6tEtTBQpZYJBJ/B7vAnbO16 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370491742" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="370491742" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="861911793" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="861911793" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:16 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] drm/xe/gsc: add gsc device support Date: Wed, 20 Sep 2023 12:41:50 +0300 Message-Id: <20230920094151.1593505-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920094151.1593505-1-alexander.usyskin@intel.com> References: <20230920094151.1593505-1-alexander.usyskin@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:46:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777561898918929471 X-GMAIL-MSGID: 1777561898918929471 From: Vitaly Lubart Create mei-gscfi auxiliary device and configure interrupts to be consumed by mei-gsc device driver. Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/xe/Kconfig | 1 + drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 4 + drivers/gpu/drm/xe/xe_device_types.h | 4 + drivers/gpu/drm/xe/xe_heci_gsc.c | 222 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_heci_gsc.h | 35 +++++ drivers/gpu/drm/xe/xe_irq.c | 21 ++- 7 files changed, 283 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/xe/xe_heci_gsc.c create mode 100644 drivers/gpu/drm/xe/xe_heci_gsc.h diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index d57181ff47e6..7df49b12a724 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -37,6 +37,7 @@ config DRM_XE select DRM_SCHED select MMU_NOTIFIER select WANT_DEV_COREDUMP + select AUXILIARY_BUS help Experimental driver for Intel Xe series GPUs diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index cc95a46b5e4d..379bd977a0a6 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -73,6 +73,7 @@ xe-y += xe_bb.o \ xe_guc_log.o \ xe_guc_pc.o \ xe_guc_submit.o \ + xe_heci_gsc.o \ xe_hw_engine.o \ xe_hw_engine_class_sysfs.o \ xe_hw_fence.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index b6bcb6c3482e..5c32da629baf 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -292,6 +292,8 @@ int xe_device_probe(struct xe_device *xe) goto err_irq_shutdown; } + xe_heci_gsc_init(xe); + err = xe_mmio_probe_vram(xe); if (err) goto err_irq_shutdown; @@ -367,6 +369,8 @@ void xe_device_remove(struct xe_device *xe) xe_display_fini(xe); + xe_heci_gsc_fini(xe); + xe_irq_shutdown(xe); } diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 696416afa7d1..3c2315c80ac2 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -13,6 +13,7 @@ #include #include "xe_devcoredump_types.h" +#include "xe_heci_gsc.h" #include "xe_gt_types.h" #include "xe_platform_types.h" #include "xe_pmu.h" @@ -368,6 +369,9 @@ struct xe_device { /** @pmu: performance monitoring unit */ struct xe_pmu pmu; + /** @heci_gsc: graphics security controller */ + struct xe_heci_gsc heci_gsc; + /* private: */ #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c new file mode 100644 index 000000000000..3328ddca42d0 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2023, Intel Corporation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "regs/xe_regs.h" +#include "xe_device_types.h" +#include "xe_drv.h" +#include "xe_heci_gsc.h" +#include "xe_platform_types.h" + +#define GSC_BAR_LENGTH 0x00000FFC + +static void heci_gsc_irq_mask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static void heci_gsc_irq_unmask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static struct irq_chip heci_gsc_irq_chip = { + .name = "gsc_irq_chip", + .irq_mask = heci_gsc_irq_mask, + .irq_unmask = heci_gsc_irq_unmask, +}; + +static int heci_gsc_irq_init(int irq) +{ + irq_set_chip_and_handler_name(irq, &heci_gsc_irq_chip, + handle_simple_irq, "heci_gsc_irq_handler"); + + return irq_set_chip_data(irq, NULL); +} + +/** + * struct heci_gsc_def - graphics security controller heci interface definitions + * + * @name: name of the heci device + * @bar: address of the mmio bar + * @bar_size: size of the mmio bar + * @use_polling: indication of using polling mode for the device + * @slow_firmware: indication of whether the device is slow (needs longer timeouts) + */ +struct heci_gsc_def { + const char *name; + unsigned long bar; + size_t bar_size; + bool use_polling; + bool slow_firmware; +}; + +/* gsc resources and definitions */ +static const struct heci_gsc_def heci_gsc_def_dg1 = { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, +}; + +static const struct heci_gsc_def heci_gsc_def_dg2 = { + .name = "mei-gscfi", + .bar = DG2_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, +}; + +static void heci_gsc_release_dev(struct device *dev) +{ + struct auxiliary_device *aux_dev = to_auxiliary_dev(dev); + struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev); + + kfree(adev); +} + +void xe_heci_gsc_fini(struct xe_device *xe) +{ + struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; + + if (!HAS_HECI_GSCFI(xe)) + return; + + if (heci_gsc->adev) { + struct auxiliary_device *aux_dev = &heci_gsc->adev->aux_dev; + + auxiliary_device_delete(aux_dev); + auxiliary_device_uninit(aux_dev); + heci_gsc->adev = NULL; + } + + if (heci_gsc->irq >= 0) + irq_free_desc(heci_gsc->irq); + heci_gsc->irq = -1; +} + +static int heci_gsc_irq_setup(struct xe_device *xe) +{ + struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; + int ret; + + heci_gsc->irq = irq_alloc_desc(0); + if (heci_gsc->irq < 0) { + drm_err(&xe->drm, "gsc irq error %d\n", heci_gsc->irq); + return heci_gsc->irq; + } + + ret = heci_gsc_irq_init(heci_gsc->irq); + if (ret < 0) + drm_err(&xe->drm, "gsc irq init failed %d\n", ret); + + return ret; +} + +static int heci_gsc_add_device(struct xe_device *xe, const struct heci_gsc_def *def) +{ + struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + struct auxiliary_device *aux_dev; + struct mei_aux_device *adev; + int ret; + + adev = kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + adev->irq = heci_gsc->irq; + adev->bar.parent = &pdev->resource[0]; + adev->bar.start = def->bar + pdev->resource[0].start; + adev->bar.end = adev->bar.start + def->bar_size - 1; + adev->bar.flags = IORESOURCE_MEM; + adev->bar.desc = IORES_DESC_NONE; + adev->slow_firmware = def->slow_firmware; + + aux_dev = &adev->aux_dev; + aux_dev->name = def->name; + aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent = &pdev->dev; + aux_dev->dev.release = heci_gsc_release_dev; + + ret = auxiliary_device_init(aux_dev); + if (ret < 0) { + drm_err(&xe->drm, "gsc aux init failed %d\n", ret); + kfree(adev); + return ret; + } + + heci_gsc->adev = adev; /* needed by the notifier */ + ret = auxiliary_device_add(aux_dev); + if (ret < 0) { + drm_err(&xe->drm, "gsc aux add failed %d\n", ret); + heci_gsc->adev = NULL; + + /* adev will be freed with the put_device() and .release sequence */ + auxiliary_device_uninit(aux_dev); + } + return ret; +} + +void xe_heci_gsc_init(struct xe_device *xe) +{ + struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; + const struct heci_gsc_def *def; + int ret; + + if (!HAS_HECI_GSCFI(xe)) + return; + + heci_gsc->irq = -1; + + if (xe->info.platform == XE_DG2) { + def = &heci_gsc_def_dg2; + } else if (xe->info.platform == XE_DG1) { + def = &heci_gsc_def_dg1; + } else { + drm_warn_once(&xe->drm, "Unknown platform\n"); + return; + } + + if (!def->name) { + drm_warn_once(&xe->drm, "HECI is not implemented!\n"); + return; + } + + if (!def->use_polling) { + ret = heci_gsc_irq_setup(xe); + if (ret) + goto fail; + } + + ret = heci_gsc_add_device(xe, def); + if (ret) + goto fail; + + return; +fail: + xe_heci_gsc_fini(xe); +} + +void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir) +{ + int ret; + + if ((iir & GSC_IRQ_INTF(1)) == 0) + return; + + if (!HAS_HECI_GSCFI(xe)) { + drm_warn_once(&xe->drm, "GSC irq: not supported"); + return; + } + + if (xe->heci_gsc.irq < 0) + return; + + ret = generic_handle_irq(xe->heci_gsc.irq); + if (ret) + drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret); +} diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.h b/drivers/gpu/drm/xe/xe_heci_gsc.h new file mode 100644 index 000000000000..9db454478fae --- /dev/null +++ b/drivers/gpu/drm/xe/xe_heci_gsc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2023, Intel Corporation. All rights reserved. + */ +#ifndef __XE_HECI_GSC_DEV_H__ +#define __XE_HECI_GSC_DEV_H__ + +#include + +struct xe_device; +struct mei_aux_device; + +/* + * The HECI1 bit corresponds to bit15 and HECI2 to bit14. + * The reason for this is to allow growth for more interfaces in the future. + */ +#define GSC_IRQ_INTF(_x) BIT(15 - (_x)) + +/** + * struct xe_heci_gsc - graphics security controller for xe, HECI interface + * + * @adev : pointer to mei auxiliary device structure + * @irq : irq number + * + */ +struct xe_heci_gsc { + struct mei_aux_device *adev; + int irq; +}; + +void xe_heci_gsc_init(struct xe_device *xe); +void xe_heci_gsc_fini(struct xe_device *xe); +void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir); + +#endif /* __XE_HECI_GSC_DEV_H__ */ diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c index ccb934f8fa34..ea53d34fd745 100644 --- a/drivers/gpu/drm/xe/xe_irq.c +++ b/drivers/gpu/drm/xe/xe_irq.c @@ -142,6 +142,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); u32 ccs_mask, bcs_mask; u32 irqs, dmask, smask; + u32 gsc_mask; if (xe_device_uc_enabled(xe)) { irqs = GT_RENDER_USER_INTERRUPT | @@ -191,9 +192,13 @@ void xe_irq_enable_hwe(struct xe_gt *gt) xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask); xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask); - if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) { - xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, irqs); - xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~irqs); + if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) + gsc_mask = irqs; + else if (HAS_HECI_GSCFI(xe)) + gsc_mask = GSC_IRQ_INTF(1); + if (gsc_mask) { + xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask); + xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask); } } } @@ -298,6 +303,11 @@ static void gt_irq_handler(struct xe_tile *tile, instance = INTR_ENGINE_INSTANCE(identity[bit]); intr_vec = INTR_ENGINE_INTR(identity[bit]); + if (class == XE_ENGINE_CLASS_OTHER && instance == OTHER_GSC_INSTANCE) { + xe_heci_gsc_irq_handler(xe, intr_vec); + continue; + } + engine_gt = pick_engine_gt(tile, class, instance); hwe = xe_gt_hw_engine(engine_gt, class, instance, false); @@ -488,8 +498,9 @@ static void gt_irq_reset(struct xe_tile *tile) if (ccs_mask & (BIT(2)|BIT(3))) xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0); - if (tile->media_gt && - xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) { + if ((tile->media_gt && + xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) || + HAS_HECI_GSCFI(tile_to_xe(tile))) { xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0); xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0); } From patchwork Wed Sep 20 09:41:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Usyskin, Alexander" X-Patchwork-Id: 142364 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4059847vqi; Wed, 20 Sep 2023 04:26:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMHKH59HB7n62Hu7+kIiX30xDR/28N6Be/aVoRx+pTcsuQl/ey79QHMeAB5MetmCvfsZSL X-Received: by 2002:a05:6a00:2d08:b0:690:ce36:8b00 with SMTP id fa8-20020a056a002d0800b00690ce368b00mr2661940pfb.2.1695209183310; Wed, 20 Sep 2023 04:26:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695209183; cv=none; d=google.com; s=arc-20160816; b=ni71GUIu5HUKfbdmFo4zx7kdKuDm5cPgDbtxv0ouR8rE22IrygPdDFhc2eeos4OkI6 vDxXk4GJO435HoCy1eDvNC+hxxlvVYCiXQLrOIEENCLu76IkXSYFeXmNn/a9cP+UdIoE qnec96VB1Tu2S+AVVIKecH5wg7vU+QJa2yQPA+5qT/vL4wvwOmRR1mKyEhcxR+9ags05 iHiyHSfbjcA2BC5sTu3qufh3c3/u0euVSXVPFz06WR6dCjASdcxGIZaj9ZsIcTcjRWp5 5xI8zQDpvV67HnTmUJAmnbFUECT6Jtg2WfAv1ThhudKZaNc11YxZwrAvc3ZU84L9GdIq IwXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Kgcnhws0Eozw1ag59pmpVZhKfUiJWmJ5MY/y7+v0isU=; fh=7xjKU1xkhmTazBlAQtMk+Chl7JSt/CUyagAgyiLWmTI=; b=esxVWTU3GqCniIStlz72UBD/A+TtybKbfDNUC5xpYuUibQFEHSYVmT68/wX2OKCMh3 YpE91MptE+cuKXcG4G1IwbYw6Km6LMClp/waFhu4Pj6cobLcHYk1HmG2ztVlxb06nSWh 3CXGwhU8h0mN7jNHSHpfkb/VHjMEWGuFXzFU5VJaZ5OggIifP6PTPv5cy2Vruvr31cSE JCQFZ3udDnYV25ysukfPH+9+U4iZ2Ot6SK46wtWWHglrbam2UMUUnS49EHNQK1SLMAvK sFOsouk4zcLvunweJS1HhZI/KR/iG3KSijw3Vqf8huFuIXPtgp42+AmPDvp2K5QbeBBB TX9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=E+0Ijbti; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id g16-20020a633750000000b00565e756639asi11500098pgn.389.2023.09.20.04.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:26:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=E+0Ijbti; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id CE63F80D8FDF; Wed, 20 Sep 2023 02:46:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234238AbjITJqi (ORCPT + 26 others); Wed, 20 Sep 2023 05:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234223AbjITJq2 (ORCPT ); Wed, 20 Sep 2023 05:46:28 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DA34DE for ; Wed, 20 Sep 2023 02:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695203182; x=1726739182; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dZu45T376T/X7r3FJumZkOqnP5mgPwgQVYAJTdBtTgs=; b=E+0Ijbti425s0S6MrGPEW/ZqwlGGPXr814VwjJIXOLAeEDcv+rKa/978 aghneUvmSEGEHWHSxNWBipUhiHqVbEsIGUHvIn52fmOSLz6Eio+VLGUIB vpUOXRYR/RAoeWtSNJM83cSiOSA80McbQSAI5vVqm6DjzlT0v/Mk8V2vX mlX/2KfK6N4Uh+pepXtqB5xrcBWZ1AjX3QU00uoI2Y86SDNrLTqESVsXK vBBAjEoXb6VHF5MRx93JWd2rKWBICd+jsU5SW7SSx7CdD4mhQ6l4ruZcL h37W75pL3L8eWG0hP1kdKzF2N6azj56J58zoPiXUAYgpFyIQLFv0jmqps A==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370491748" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="370491748" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="861911799" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="861911799" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:19 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/4] mei: gsc: add support for auxiliary device created by Xe driver Date: Wed, 20 Sep 2023 12:41:51 +0300 Message-Id: <20230920094151.1593505-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920094151.1593505-1-alexander.usyskin@intel.com> References: <20230920094151.1593505-1-alexander.usyskin@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:46:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777555664629307348 X-GMAIL-MSGID: 1777555664629307348 From: Vitaly Lubart Add support for gsc mei auxiliary device created by Xe driver Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/misc/mei/gsc-me.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index e63cabd0818d..63525778a4e0 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -292,6 +292,10 @@ static const struct auxiliary_device_id mei_gsc_id_table[] = { .name = "i915.mei-gscfi", .driver_data = MEI_ME_GSCFI_CFG, }, + { + .name = "xe.mei-gscfi", + .driver_data = MEI_ME_GSCFI_CFG, + }, { /* sentinel */ } @@ -312,4 +316,5 @@ module_auxiliary_driver(mei_gsc_driver); MODULE_AUTHOR("Intel Corporation"); MODULE_ALIAS("auxiliary:i915.mei-gsc"); MODULE_ALIAS("auxiliary:i915.mei-gscfi"); +MODULE_ALIAS("auxiliary:xe.mei-gscfi"); MODULE_LICENSE("GPL");