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Peter Anvin" Subject: [PATCH v2 1/5] x86: add X86_FEATURE_XENPV to disabled-features.h Date: Fri, 4 Nov 2022 08:26:57 +0100 Message-Id: <20221104072701.20283-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221104072701.20283-1-jgross@suse.com> References: <20221104072701.20283-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748549823525116114?= X-GMAIL-MSGID: =?utf-8?q?1748549823525116114?= Add X86_FEATURE_XENPV to the features handled specially in disabled-features.h. Signed-off-by: Juergen Gross Acked-by: Dave Hansen --- arch/x86/include/asm/disabled-features.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 33d2cd04d254..c862552d7d6d 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -81,6 +81,12 @@ # define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) #endif +#ifdef CONFIG_XEN_PV +# define DISABLE_XENPV 0 +#else +# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31)) +#endif + #ifdef CONFIG_INTEL_TDX_GUEST # define DISABLE_TDX_GUEST 0 #else @@ -98,7 +104,7 @@ #define DISABLED_MASK5 0 #define DISABLED_MASK6 0 #define DISABLED_MASK7 (DISABLE_PTI) -#define DISABLED_MASK8 (DISABLE_TDX_GUEST) +#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST) #define DISABLED_MASK9 (DISABLE_SGX) #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET) From patchwork Fri Nov 4 07:26:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 15406 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp228421wru; Fri, 4 Nov 2022 00:31:11 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7LV5tyOfsVg9xwrfqcEDjD8L3CdkdhF+nztYJD0YH37jreKfyfEQbcVvblax0zsxGfKDFL X-Received: by 2002:a17:902:7b8f:b0:186:a1c4:e648 with SMTP id w15-20020a1709027b8f00b00186a1c4e648mr33315959pll.37.1667547070799; Fri, 04 Nov 2022 00:31:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667547070; cv=none; d=google.com; s=arc-20160816; b=V65Tows/g4oc1d7Btr4PS6MqPcsN0hkRBVk/n7pCMdHVxrxzaRIafNwF1lECKmwR17 +JfWbRn3z5r1Qo9FssJ4Jp1IAjaGvl76KJdX3R2nb85cAWQUFS9PDkVUIiEXsDnOEcbS U+XGNohmwiPNQ5RsCb8CV6vVf1vwmYzkAAy091mqm4/SfBqM1TT12qbsMZ9XmncjEbjO vshhmweYAovPxKlEGxrj7+FGSCKBQYFiVEDwv8ZTyi37xF67mQ0rzqAp8o++WW25DD7o xsq0bdnrG7+u4NJwBTKKHVf8jaM41g4zADRKCKgep6gocwZhfxQTgqb66yYls4rfDvha TZag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mK6Yb+HDZYey+MdThM5vOztF2LsAJko2NCXxRRCzJLc=; b=OJ/ddRFhSRxAlel/MqGGIxZeo2UTvLnc8V2z0Z4LYh/j9xv/YxZrZS6nR1SQ4KkYtg 72OCQJLsv9WnFONu2A9qxypnP2S71qzynM32Q+0Cj/iQk+tABygSiChIxdIJ7on9VLzx BGFdUFM4t7mVYQy0mo9EI+awbRvNar9cYWpqrLpJN88mqX6W4bUBk1nQ8+3ItcKeBu/e 6hnHXJLXY3V9+OKkApe+aNATo0KT25eIZJcY7kVFttEYMXis0UmPoM3TmUGOZ8vfrtFE au99BlUtz7TyTPYw1kIm52mG7+6HLDiT7NlvrtkqBUDqixuxG4OOOP0pd4l94Vv09KxM ImuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=t3mgxfqu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v2 2/5] x86: remove unneeded 64-bit dependency in arch_enter_from_user_mode() Date: Fri, 4 Nov 2022 08:26:58 +0100 Message-Id: <20221104072701.20283-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221104072701.20283-1-jgross@suse.com> References: <20221104072701.20283-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748549837048549631?= X-GMAIL-MSGID: =?utf-8?q?1748549837048549631?= The check for 64-bit mode when testing X86_FEATURE_XENPV isn't needed, as Xen PV guests are no longer supported in 32-bit mode. While at it switch from boot_cpu_has() to cpu_feature_enabled(). Signed-off-by: Juergen Gross Acked-by: Dave Hansen --- arch/x86/include/asm/entry-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry-common.h index 674ed46d3ced..117903881fe4 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -24,8 +24,8 @@ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) /* * For !SMAP hardware we patch out CLAC on entry. */ - if (boot_cpu_has(X86_FEATURE_SMAP) || - (IS_ENABLED(CONFIG_64BIT) && boot_cpu_has(X86_FEATURE_XENPV))) + if (cpu_feature_enabled(X86_FEATURE_SMAP) || + cpu_feature_enabled(X86_FEATURE_XENPV)) mask |= X86_EFLAGS_AC; WARN_ON_ONCE(flags & mask); From patchwork Fri Nov 4 07:26:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 15407 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp228425wru; Fri, 4 Nov 2022 00:31:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7R4okipE8kzE2T9FSbHt+7yLkiIgoU92iI/I/r1h5LopIJoUXVg/akEkwmQGvxbx+l+PqV X-Received: by 2002:a65:5a8b:0:b0:470:2ecd:ea02 with SMTP id c11-20020a655a8b000000b004702ecdea02mr4156772pgt.83.1667547071943; Fri, 04 Nov 2022 00:31:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667547071; cv=none; d=google.com; s=arc-20160816; b=JgVsEjeKavHwylRMUEGOyRQ+6VMPmk1FYNIuO3/JnZF3ya4/W8CJTRJ5AvpzMIat9/ ctW69RoWvr5l86omDHMTdJGjtvKAAqGGVM1y+z1x6izQ94Tg/DR3DE689q11TBEXPi9p dhsq/UfsZwAZkg4ThFLrN9wc69Dgyy8H+b0Xi3XE84odAdIKw/RblhjyPghrXpM0ZgNr 7Sw6Z4OIQcutszVlIbfPgexP/oH6E0pHj+qlEJtC26aQGsmxez+MDskPZlBjRMfBz+9d TZ+hlfYdbiGgw0DaiC77/4CZF2i+KSw+AyT1PJn4wvvYNe3tz32O/eCc/GHtb/2pAkoF MsGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZIOvMf0VCiOOdx+pSynOR3iuEcnpBNHWVTTFgfhwJA0=; b=LXYLF0KI5xogdLB/vTT7Fmhw1FucsT4IhQOW6kbO7evW7p8WUb8BoF9e8jTaQQh0cg 4WuMyFUyAXdrf7CT/neEukHxcfkb7L5cp7EGTbSSO057M2RkiwVe2Nb9eLWEsLWsOM3E zsc0Wi29oykagYFAMIoMAUSsbCY6kCHrr6Y4CoJpL7N/XAFLFzw1Yzi8F9WpLBlYuIZV 5arM3oTHI8adKBqdiqAhOhA8GoGQlkUBhIaGp1oLi98IPQZeFns7uCH5cqtExdACw1YE XnWbv0aSnbH96ULDhiZod1V6ulD+i6mEETmbOjA0qohs9k4+khpsRsPRqtK/yVA3LSaQ 7t6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=EnjxfVY1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v2 3/5] x86: drop 32-bit Xen PV guest code in update_task_stack() Date: Fri, 4 Nov 2022 08:26:59 +0100 Message-Id: <20221104072701.20283-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221104072701.20283-1-jgross@suse.com> References: <20221104072701.20283-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748549838460978743?= X-GMAIL-MSGID: =?utf-8?q?1748549838460978743?= Testing for Xen PV guest mode in a 32-bit only code section can be dropped, as Xen PV guests are supported in 64-bit mode only. While at it switch from boot_cpu_has() to cpu_feature_enabled() in the 64-bit part of the code. Signed-off-by: Juergen Gross Acked-by: Dave Hansen --- arch/x86/include/asm/switch_to.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index c08eb0fdd11f..5c91305d09d2 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -66,13 +66,10 @@ static inline void update_task_stack(struct task_struct *task) { /* sp0 always points to the entry trampoline stack, which is constant: */ #ifdef CONFIG_X86_32 - if (static_cpu_has(X86_FEATURE_XENPV)) - load_sp0(task->thread.sp0); - else - this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); + this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); #else /* Xen PV enters the kernel on the thread stack. */ - if (static_cpu_has(X86_FEATURE_XENPV)) + if (cpu_feature_enabled(X86_FEATURE_XENPV)) load_sp0(task_top_of_stack(task)); #endif } From patchwork Fri Nov 4 07:27:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 15408 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp228611wru; Fri, 4 Nov 2022 00:31:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6rbXdPvKq7qw7lAbDvGBXEMzDMjlJN6kehy9rQnEDo6X2I66kyckSXDxBzdDKJUEn1V5pT X-Received: by 2002:a17:903:2442:b0:186:ef89:7b41 with SMTP id l2-20020a170903244200b00186ef897b41mr33572955pls.164.1667547093508; Fri, 04 Nov 2022 00:31:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667547093; cv=none; d=google.com; s=arc-20160816; b=vXuMcOFDclamtxDpqwJkAfiGwz32BCZ/Vebyjeg3i5wB+wFsyASJRUAhHolM+rKjwW jqE8d6tFN4of9m5LHnR7lBNAN1NhdgJLFFlJ8ZoHj1gPikfXiqiIFg68yA3bLs1lb4hw goFcr0qXjjEEaKs42n+WNT+5CD/DCylFpitQL4yxG7Eex+qTAvqpWp4RK98tP0dUcDqj p8V3rb3xWztOW/49PmkXS/9s4cujqqyjbEBqaAJt3f4au/lpEWOq6hwVucH3JDscBarv Nv9/F2NqnwGvlzk5IbnonPBTugOYDd95BPZkM4jCsZR4LgO6W2k6uHMBRgJPdyLMwLxm inbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ly27pQKB8zJ1EGsnrKjc1hdO+HpUmQnfYr1acXfsIKI=; b=eJCi0O9kEF7G1h3XcaCvZPsbl79C7DiS7mpsrwhS5JjwnhbBzQlVne2bHnn4ul79As pIeBzPOxHxgaf8jWiHJOz1uQ/IQ0ThOo2ckTD7VhyZr8VqbZMlkOhwxm4i/0yw2ydmxE mgw/Koze8jSbXkYmiN9FuKXXFfR4DlcY6JfJt9ez5yxWGzUITzen8AR4CPwxkwsUCizn GpPeK69G26dXHppI5Eo26llNrqmk4wSdzWoZfIBV/CD78bU28HN/z3PcyjOlfihDxKN+ X0MkDAtbn2SZMp1LWSALoLUENkGwNoRfk5uIUbvNVPg2tlhdNmUbyioS0hGShX0+iHTC wxeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=pWWGyaE1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v2 4/5] x86: remove X86_FEATURE_XENPV usage in setup_cpu_entry_area() Date: Fri, 4 Nov 2022 08:27:00 +0100 Message-Id: <20221104072701.20283-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221104072701.20283-1-jgross@suse.com> References: <20221104072701.20283-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748549860761319493?= X-GMAIL-MSGID: =?utf-8?q?1748549860761319493?= Testing of X86_FEATURE_XENPV in setup_cpu_entry_area() can be removed, as this code path is 32-bit only, and Xen PV guests are not supporting 32-bit mode. Signed-off-by: Juergen Gross Acked-by: Dave Hansen --- V2: - new patch --- arch/x86/mm/cpu_entry_area.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index 6c2f1b76a0b6..42cd96e7d733 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -138,17 +138,13 @@ static void __init setup_cpu_entry_area(unsigned int cpu) pgprot_t tss_prot = PAGE_KERNEL_RO; #else /* - * On native 32-bit systems, the GDT cannot be read-only because + * On 32-bit systems, the GDT cannot be read-only because * our double fault handler uses a task gate, and entering through * a task gate needs to change an available TSS to busy. If the * GDT is read-only, that will triple fault. The TSS cannot be * read-only because the CPU writes to it on task switches. - * - * On Xen PV, the GDT must be read-only because the hypervisor - * requires it. */ - pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? - PAGE_KERNEL_RO : PAGE_KERNEL; + pgprot_t gdt_prot = PAGE_KERNEL; pgprot_t tss_prot = PAGE_KERNEL; #endif From patchwork Fri Nov 4 07:27:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 15410 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp228906wru; Fri, 4 Nov 2022 00:32:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4mGRS9nQdvwJlayaZTXHtfp/F+bWJHuRQEqa74tAvnXUhIbR+hNu9tznUS478XLjPfVZ6g X-Received: by 2002:a63:f84c:0:b0:470:f04:5c81 with SMTP id v12-20020a63f84c000000b004700f045c81mr9440140pgj.143.1667547142365; Fri, 04 Nov 2022 00:32:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667547142; cv=none; d=google.com; s=arc-20160816; b=ui9/5wG+cHBCu+Z/gNGSrv8TQ1LRBocLfLuG/oEKD6WETE4Y25rG/wdZEQpxWemvhN qnBDZZ883lM3h8oj7bKQUtIUHPVlsKaPf9Wp89o/S/3IPSRg0fNhddBWSKEXXppnBGbE XcHg3ciFhtgZK8/bH1ZyHqDISz80f53iUsHiDYMusPm9MrZy9WprE6awwMkjqPLmJYMb HKCsoJeROMH7krimI0GIkk/lonl7XRXEuap4xEzKdtGGMbuIYgzrREFlHrjZSxVq6uea 1FGWGQONzd/E2nHC8xPkdnMGIFeI5Fejeu/2alv5JkC+Ovcu9Y3a4SvRkvZvvM4eIxAz ax+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ETDMSDRjzWVlC2eQNNmpxl8Qm+9vtlmDFMYqkaHH46A=; b=Jw1f+DAnIcOmR9eidv8e70ubfW47DNigBY1TxGQbLmEuvlm+G2M4pUYCjYEvHKatPX y52nw+RJRVJNiwYiJ1IlXJ3yoUxEauDkLh8/Q05sOsRqUfW+kcQIF73sKe0Ndlt9L7HF DnIlre0u1q45hU5KMqKV5M9SIu8jrFh80yr6mPNKZvverI/5tqV55MLcnfdSIrWRUnUZ ZV3oHv39FsJV6qkIZKGTsu4D2LJSsUUihI92mGqhtxB5/9H4ntmlmJVWWPgESLQyxMo0 Gzy3DM7U8d6sREbOtcFeNgrVnLqpYc3nIwjdIw1E0kqRkfdsYtd/mTyhQUib5GOlpQas 904w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=eJn1trHV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Pu Wen Subject: [PATCH v2 5/5] x86: switch to cpu_feature_enabled() for X86_FEATURE_XENPV Date: Fri, 4 Nov 2022 08:27:01 +0100 Message-Id: <20221104072701.20283-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221104072701.20283-1-jgross@suse.com> References: <20221104072701.20283-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748549912137901244?= X-GMAIL-MSGID: =?utf-8?q?1748549912137901244?= Convert the remaining cases of static_cpu_has(X86_FEATURE_XENPV) and boot_cpu_has(X86_FEATURE_XENPV) to use cpu_feature_enabled(), allowing more efficient code in case the kernel is configured without CONFIG_XEN_PV. Signed-off-by: Juergen Gross Acked-by: Dave Hansen --- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/bugs.c | 2 +- arch/x86/kernel/cpu/hygon.c | 2 +- arch/x86/kernel/process_64.c | 4 ++-- arch/x86/kernel/topology.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 860b60273df3..697fe881e967 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -985,7 +985,7 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ - if (!cpu_has(c, X86_FEATURE_XENPV)) + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); /* diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index da7c361f47e0..7f78e1527c5e 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1302,7 +1302,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return SPECTRE_V2_CMD_AUTO; } - if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) { + if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) { pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", mitigation_options[i].option); return SPECTRE_V2_CMD_AUTO; diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 21fd425088fe..1c27645fd429 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -339,7 +339,7 @@ static void init_hygon(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_ARAT); /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ - if (!cpu_has(c, X86_FEATURE_XENPV)) + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); check_null_seg_clears_base(c); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 6b3418bff326..e2f469175be8 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,7 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +190,7 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs(); diff --git a/arch/x86/kernel/topology.c b/arch/x86/kernel/topology.c index 8617d1ed9d31..1b83377274b8 100644 --- a/arch/x86/kernel/topology.c +++ b/arch/x86/kernel/topology.c @@ -106,7 +106,7 @@ int arch_register_cpu(int num) * Xen PV guests don't support CPU0 hotplug at all. */ if (c->x86_vendor != X86_VENDOR_INTEL || - boot_cpu_has(X86_FEATURE_XENPV)) + cpu_feature_enabled(X86_FEATURE_XENPV)) cpu0_hotpluggable = 0; /*