From patchwork Wed Sep 20 09:54:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4014373vqi; Wed, 20 Sep 2023 03:03:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGcQigd0nbSJR14gZQbGY+3fYWgzjW/BlsLwf9x7SEdcNQNGnytKGnrcofQ/uYdqmyLhRUf X-Received: by 2002:a05:6a00:812:b0:68e:4303:edb8 with SMTP id m18-20020a056a00081200b0068e4303edb8mr2299973pfk.30.1695204230321; Wed, 20 Sep 2023 03:03:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695204230; cv=none; d=google.com; s=arc-20160816; b=DtqNzppHfbdJKWbxJISfRJcB254rh4P0eMx7Ey1yLZM4iovQEOrl0qIvm5htn5BrNF 8qyFPIlajbf8eq+hZJRV/Hi9byxvnE5UK++E84Ps08z3omXemIKvGZmk63mv55GDkNiW mdaSTfD4AgqYxCocCKNamMcsORncVkngQLittIYI4xh/+EvzVAXb++KY0lLKbjheaukF 2fFtpl5Ad16kPDQsR3pxLiWWtpiVe+F+ltLr2glv/lpKk+b8ylcJCLTWJB9PKMuBkwyT tZzLBi40WoVn+VqjbIHt8T1O3UFZii8E2t9dwm84II04HwwdNqoDJWhGoP9wZYt9/aJ9 a6RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lIKSc1L8JNYSxtTlGTrxKJ5F2yZL3v9XfGB/qKz4mmM=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=EXII+LcmZIhy0aCwhD9lMQuaW7DInq21WryKvzW2Ktc/iQlmqUJJSy1BMnZHs+WAf5 jMwlHy+6+J48TDm6sZQ0nlrymGL5pk08GsNzbKQF/O6el8Dt8ArMsmKrBJOwYBfrArPk NFWla4WuAmr/rdh/FrNlTAoq0asw2BKZfhv0JPS49EY9OvkBnoEnHrdp6bmNz2lsvB6f /qINgVoAuroaNyH87siK6tGjjDKMrNVzrsd9gGdxwQPQYrltiDm2lFztDSgza2RTnJdt 28dK/pjgBJLSf8spug4U6DGciUB1TvlEohmm8Q54JzRuc+T1RYUngMdozMCac3m5LJZ9 XoCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id i62-20020a638741000000b00578b79c785bsi2820869pge.217.2023.09.20.03.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 03:03:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 4740D8022AA3; Wed, 20 Sep 2023 02:55:20 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234233AbjITJzP (ORCPT + 26 others); Wed, 20 Sep 2023 05:55:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234227AbjITJzH (ORCPT ); Wed, 20 Sep 2023 05:55:07 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C78B6AC; Wed, 20 Sep 2023 02:54:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B23AB1FB; Wed, 20 Sep 2023 02:55:36 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.59.204]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5FD8C3F5A1; Wed, 20 Sep 2023 02:54:55 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V6 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus Date: Wed, 20 Sep 2023 15:24:41 +0530 Message-Id: <20230920095443.1126617-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920095443.1126617-1-anshuman.khandual@arm.com> References: <20230920095443.1126617-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:55:20 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777550471238191963 X-GMAIL-MSGID: 1777550471238191963 This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN field in ETM gets an wrong value. If software uses the value returned by the TRCIDR3.CCITMIN register field, then it will limit the range which could be used for programming the ETM. In reality, the ETM could be programmed with a much smaller value than what is indicated by the TRCIDR3.CCITMIN field and still function correctly. If software reads the TRCIDR3.CCITMIN register field, corresponding to the instruction trace counting minimum threshold, observe the value 0x100 or a minimum cycle count threshold of 256. The correct value should be 0x4 or a minimum cycle count threshold of 4. This work arounds the problem via storing 4 in drvdata->ccitmin on affected systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count threshold granularity. These errata information has been updated in arch/arm64/silicon-errata.rst, but without their corresponding configs because these have been implemented directly in the driver. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/silicon-errata.rst | 10 +++++ .../coresight/coresight-etm4x-core.c | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index e96f057ea2a0..8f1be5da68b7 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -115,6 +115,10 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A76 | #1490853 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A77 | #1491015 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | @@ -125,6 +129,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1 | #1502854 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | @@ -133,6 +139,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N1 | #1490853 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | @@ -141,6 +149,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V1 | #1619801 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-600 | #1076982,1209401| N/A | diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 77b0271ce6eb..9619d9d0bbb1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1150,6 +1150,41 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) drvdata->trfcr = trfcr; } +/* + * The following errata on applicable cpu ranges, affect the CCITMIN filed + * in TCRIDR3 register. Software read for the field returns 0x100 limiting + * the cycle threshold granularity, whereas the right value should have + * been 0x4, which is well supported in the hardware. + */ +static struct midr_range etm_wrong_ccitmin_cpus[] = { + /* Erratum #1490853 - Cortex-A76 */ + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), + /* Erratum #1490853 - Neoverse-N1 */ + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), + /* Erratum #1491015 - Cortex-A77 */ + MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), + /* Erratum #1502854 - Cortex-X1 */ + MIDR_REV(MIDR_CORTEX_X1, 0, 0), + /* Erratum #1619801 - Neoverse-V1 */ + MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), + {}, +}; + +static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) +{ + /* + * Erratum affected cpus will read 256 as the minimum + * instruction trace cycle counting threshold whereas + * the correct value should be 4 instead. Override the + * recorded value for 'drvdata->ccitmin' to workaround + * this problem. + */ + if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) { + if (drvdata->ccitmin == 256) + drvdata->ccitmin = 4; + } +} + static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -1214,6 +1249,8 @@ static void etm4_init_arch_data(void *info) etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); + etm4_fixup_wrong_ccitmin(drvdata); + /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); drvdata->config.s_ex_level = drvdata->s_ex_level; From patchwork Wed Sep 20 09:54:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4014676vqi; Wed, 20 Sep 2023 03:04:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGEUZisvm37KwccZCwV9Z1XYNRDQHji3Wf/PDAW00Hwd+/IlXiEHKmcRWcwF+moX1jtFyGR X-Received: by 2002:a05:6a00:c91:b0:68c:3f2:6007 with SMTP id a17-20020a056a000c9100b0068c03f26007mr2352116pfv.8.1695204258064; Wed, 20 Sep 2023 03:04:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695204258; cv=none; d=google.com; s=arc-20160816; b=pni20XbMRwG81lEh1xjbgDaxsu1bkAnPLoKl14c7TMPNSO4tdMYD0G/gnbMHeTxzVY uSXfpuFmyXsuuXyAJFwmKc4I4UPayMU5iUANAjahilYrO04iCkvSM+kCSn2ya3sdq+Gj r7hONff8ca0xQ/1oIkOu6tZBzzBPm6o9di7TiA+2Sr5cuEs7Kpu/7tRJIYW1g2TlDxDL +v+OEKmrVtULfLpbrSi26KI1TTcXoDiVFarjLmC06VzzST3SKkucTvw+K12Ca78fp3X9 GG9JadYKtEhfz+Cj36e9UrkEf9SmBcbOO2b5oCkIkrFAYH1InXX8/uS1HcLUxyfqenuL X5fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lVoGUkRpzQk76GjV7S75PqLo3Vd5zIqA1gX1OPeuHik=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=U/3MXG3MRT7Kl5l9y60kmGqQS8IEbyLqD9b1UCbgdaE23I9Qo7bcScd27Zb0TmNN0f 56dGN0G6YFdkuaAPqG/xfs2c1g3ugwes8vrxwvrLvJR0ImKy1WPLgrbfLgtN6/6zIQzv 78L1ukciuedY1o9gCWScFalBlpZd9vM07zZFFl9QIXv5j/81tIP6ybzx+CWtl5TttOzQ m5cGTwLJSQEMMTXU+4nY25oSmHWJTM3TzU7lb4KxpCG+NqCI5HMA3G92ZX3rbnG9lkuO W6cHUAn+fa59SrzwXHXKPxjQwHBmIWiOuAbgnmIxE2W4aGnkAWQWJ1ca1jrx1RH72R11 //Dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id x24-20020a056a000bd800b00690fbe083f8si149676pfu.334.2023.09.20.03.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 03:04:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 5B553802139C; Wed, 20 Sep 2023 02:55:30 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234291AbjITJzX (ORCPT + 26 others); Wed, 20 Sep 2023 05:55:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234246AbjITJzK (ORCPT ); Wed, 20 Sep 2023 05:55:10 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5DB79A3; Wed, 20 Sep 2023 02:55:04 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39E03C15; Wed, 20 Sep 2023 02:55:41 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.59.204]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 29C603F5A1; Wed, 20 Sep 2023 02:54:59 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V6 2/3] coresight: etm: Make cycle count threshold user configurable Date: Wed, 20 Sep 2023 15:24:42 +0530 Message-Id: <20230920095443.1126617-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920095443.1126617-1-anshuman.khandual@arm.com> References: <20230920095443.1126617-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:55:30 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777550500177200661 X-GMAIL-MSGID: 1777550500177200661 Cycle counting is enabled, when requested and supported but with a default threshold value ETM_CYC_THRESHOLD_DEFAULT i.e 0x100 getting into TRCCCCTLR, representing the minimum interval between cycle count trace packets. This makes cycle threshold user configurable, from the user space via perf event attributes. Although it falls back using ETM_CYC_THRESHOLD_DEFAULT, in case no explicit request. As expected it creates a sysfs file as well. /sys/bus/event_source/devices/cs_etm/format/cc_threshold New 'cc_threshold' uses 'event->attr.config3' as no more space is available in 'event->attr.config1' or 'event->attr.config2'. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5ca6278baff4..09f75dffae60 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); +PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); /* @@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, + &format_attr_cc_threshold.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9619d9d0bbb1..5b6a878a2ac5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -644,7 +644,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct etmv4_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; - int preset; + int preset, cc_threshold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -667,7 +667,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; + if (!cc_threshold) + cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; + if (cc_threshold < drvdata->ccitmin) + cc_threshold = drvdata->ccitmin; + config->ccctlr = cc_threshold; } if (attr->config & BIT(ETM_OPT_TS)) { /* From patchwork Wed Sep 20 09:54:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142318 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4015027vqi; Wed, 20 Sep 2023 03:04:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENFEh4GzdF3riOodBx9irdkBY17ciRhCXFcdpkegwQRfNPGMURuYrY8EKzRTO5izSUiOtg X-Received: by 2002:a17:902:ef87:b0:1bf:1:a4a8 with SMTP id iz7-20020a170902ef8700b001bf0001a4a8mr1605755plb.25.1695204291449; Wed, 20 Sep 2023 03:04:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695204291; cv=none; d=google.com; s=arc-20160816; b=ddIehcXbPpU8XsHsVkmjIQZv80IaV08WiJx90WslXpEK/gMDThIfG/IB2/W8XrfzxW JCQHfYRcyKXI6n6ymKtjc2x7mRYPwA5KAE783n+J1D8mOrkh4MAGDRSuiH6Hv0diplYh GQ6D06KAhgtjD+BLFYkpjUIznPKfpOLsjwl2VVKA3t/Lt1U4bO7jrMevaN2E3l94mU4/ 7hxIuIJfaTHEx49IR53CpSX5fIaD13gZnqfxQGUOQyvoV88DIdQ/0eqdSYPzyLXPvS7T ySe3PIvuYvuZFrUxFWAv+zmCiePcGB1kYoZ9LIjOuCNr5xI5PRtlEcNiEK4HC5nGCc/Q 0gaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/ABFvXitoUhGgvKWgVLSjE34Xutdrpxjmzw+8l/wgFw=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=cLCcZU7+55VVgG77UPP4qseATgmK9qMT+pN1VijRmTfrs9ZsisbKoLoK9r/ZSeZxS9 tTxzFOyLABQSKHEeZTSvE8z2dgnrT828DPtbPuGlebyGCxcnFE0DYSPCceptiHHYw0bF q8d3VesdJBEXA+ArnVrFOs0ERRow+5HdThm/gD6jmSFSL66vLI1JOLDfop9Aevp7H/Bz wQlx0g+BXkhbCFqw5DG/ZEckwtT7zZ9OJ7xtqlMRcd8UYgTufv5t20NyCzMecqxI2U65 Txkduxr+3ervC8BxuG7cM17u+1LWt0cPOAKlx+D2ONQKeUx/uEzCFRhKhj64NF5/H/qx OYaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id x2-20020a170902a38200b001bbc80a2a3asi2185308pla.299.2023.09.20.03.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 03:04:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id D652A809565A; Wed, 20 Sep 2023 02:56:19 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234317AbjITJz3 (ORCPT + 26 others); Wed, 20 Sep 2023 05:55:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234248AbjITJzP (ORCPT ); Wed, 20 Sep 2023 05:55:15 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CDA25AB; Wed, 20 Sep 2023 02:55:08 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4DFA1FB; Wed, 20 Sep 2023 02:55:45 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.59.204]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AD71E3F5A1; Wed, 20 Sep 2023 02:55:04 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V6 3/3] Documentation: coresight: Add cc_threshold tunable Date: Wed, 20 Sep 2023 15:24:43 +0530 Message-Id: <20230920095443.1126617-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230920095443.1126617-1-anshuman.khandual@arm.com> References: <20230920095443.1126617-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:56:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777550535143756534 X-GMAIL-MSGID: 1777550535143756534 This updates config option to include 'cc_threshold' tunable value. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed by: Mike Leach Signed-off-by: Anshuman Khandual --- Documentation/trace/coresight/coresight.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 4a71ea6cb390..ce55adb80b82 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ * - timestamp - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP ` + * - cc_threshold + - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the + default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold + value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead. How to use the STM module -------------------------