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[8.43.85.97]) by mx.google.com with ESMTPS id k23-20020a05640212d700b00532dfd1e74dsi1351613edx.691.2023.09.19.20.38.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 20:38:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CnMGhuje; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB72E385C301 for ; Wed, 20 Sep 2023 03:38:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 7077E385783F for ; Wed, 20 Sep 2023 03:37:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7077E385783F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695181076; x=1726717076; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=xYjVASNlr309T7XZCtXUnX/6GKg932nA6FofjLC/HDI=; b=CnMGhujeMAU77CsY7ehebG96i2zUdfjB//aOgjNZK0Z41F78nZSsX80E PAlyTWd3hZyBvAaiVRt1bs65y+tSR3+NlPgBI4EH8GNGf9z2/iLM4KvkJ c0pyl7b8elgJn81UFPfq3/zL9GS2Z1KuihhZNGqPrH4OLjgQQaKPvbYuh BxpCnHXTviVE4GXGfTiK6VO3xLG+maRvxkxAWLrjmhSp+C3p9TzvbYp5Y 8r01D3tUJvwGza0x0owrlmDPu4ks7BF88azyTdOTZDlAqq/QBsC3lL6L5 VuuiiFP5vZVBout7TOkcVRSwnv3FitEPzvRt8+i2lEKOWxt5+6QPAq+iT Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="360369612" X-IronPort-AV: E=Sophos;i="6.02,160,1688454000"; d="scan'208";a="360369612" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 20:37:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="775814373" X-IronPort-AV: E=Sophos;i="6.02,160,1688454000"; d="scan'208";a="775814373" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga008.jf.intel.com with ESMTP; 19 Sep 2023 20:37:52 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.159.141]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 490DA1005667; Wed, 20 Sep 2023 11:37:51 +0800 (CST) From: yanzhang.wang@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, jeffreyalaw@gmail.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Support simplifying x/(-1) to neg for vector. Date: Wed, 20 Sep 2023 11:36:20 +0800 Message-ID: <20230920033736.365110-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777526236223934181 X-GMAIL-MSGID: 1777526236223934181 From: Yanzhang Wang gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): support simplifying vector int not only scalar int. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/simplify-vdiv.c: New test. Signed-off-by: Yanzhang Wang --- Currently, the simplify works only for scalar int. I think it should also work for vector int. So push this patch. Have tested with aarch64 and x86, there's no regression introduced. gcc/simplify-rtx.cc | 4 ++-- .../gcc.target/riscv/rvv/base/simplify-vdiv.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index eb1ac120832..170406aa28b 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -4093,7 +4093,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, } } } - else if (SCALAR_INT_MODE_P (mode)) + else if (SCALAR_INT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_VECTOR_INT) { /* 0/x is 0 (or x&0 if x has side-effects). */ if (trueop0 == CONST0_RTX (mode) @@ -4111,7 +4111,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, return tem; } /* x/-1 is -x. */ - if (trueop1 == constm1_rtx) + if (trueop1 == CONSTM1_RTX (mode)) { rtx x = rtl_hooks.gen_lowpart_no_emit (mode, op0); if (x) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c new file mode 100644 index 00000000000..08300061832 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +#define VDIV_WITH_LMUL(LMUL, DTYPE) \ + vint##DTYPE##m##LMUL##_t \ + shortcut_for_riscv_vdiv_case_##LMUL##_##DTYPE \ + (vint##DTYPE##m##LMUL##_t v1, \ + size_t vl) \ + { \ + return __riscv_vdiv_vx_i##DTYPE##m##LMUL (v1, -1, vl); \ + } + +VDIV_WITH_LMUL (1, 16) +VDIV_WITH_LMUL (1, 32) + +/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */