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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w23-20020aa7cb57000000b00532c7f80069si640156edt.6.2023.09.19.04.27.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 04:27:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 33D42385C423 for ; Tue, 19 Sep 2023 11:27:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 19EAB3858D39 for ; Tue, 19 Sep 2023 11:27:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 19EAB3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp63t1695122815timf7hso Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 19 Sep 2023 19:26:54 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: vrqOr+ppv0vQLveuTz9QGvxPz4r4UNRa6zSF0TPkteiMK+Hfw8ADC26WzDugi Am1K3oTc4zbIfM6YGVRR40URBXUJVpW4PJ+neZHh4j85XCy7CBT3fD7Hmsl3Pmlyq3YtlR2 OibyEh5n3rIB2rLLdYcKem2bfjRm/AeASR7GH+vc5Y8fHpOGPMP8OUd918QKOHBuD1hQ35a afrs16S2dIA9dyT8mhE0lBk2bVr0SIueneW9Go8j3rxwzwUn9saev2fAQFEIpRKC8xLk4v5 iYqfm5B1QxM0hI4A4PmvXVSpQG5a5VWQuyjFEZU/aSGrOVGUNNk7B46N+cNYJKr+8/CDFbp LZqVLYLoC1UYTg6AxayR4Ht30eM0YxHOdHghLXYTxIjqmdpUyc2MnHFnKiGBdqfROZhzLOo Oe6EjPh7/328jmXpglZtTb5SrLtIRx4L X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3169073006552906553 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [Committed] RISC-V: Support VLS unary floating-point patterns Date: Tue, 19 Sep 2023 19:26:53 +0800 Message-Id: <20230919112653.539780-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777465152582531335 X-GMAIL-MSGID: 1777465152582531335 Extend current VLA patterns with VLS modes. Regression all passed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test. --- gcc/config/riscv/autovec.md | 12 ++--- gcc/config/riscv/vector.md | 20 +++---- .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +- .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++ 4 files changed, 70 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 769ef6daa36..75ed7ae4f2e 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1031,9 +1031,9 @@ ;; - vfneg.v/vfabs.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop_nofrm:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1052,9 +1052,9 @@ ;; - vfsqrt.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f7f37da692a..f66ffebba24 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6756,8 +6756,8 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") @@ -6768,9 +6768,9 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (any_float_unop:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_unop:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") @@ -6783,8 +6783,8 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") @@ -6793,9 +6793,9 @@ (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_float_unop_nofrm:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.v\t%0,%3%p1" [(set_attr "type" "") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 5df90704885..d7b721b4e3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -1,4 +1,5 @@ #include +#include typedef int8_t v1qi __attribute__ ((vector_size (1))); typedef int8_t v2qi __attribute__ ((vector_size (2))); @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096))); PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \ { \ for (int i = 0; i < NUM; ++i) \ - a[i] = OP b[i]; \ + a[i] = OP (b[i]); \ } #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c new file mode 100644 index 00000000000..c2ab0098afa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (neg, 2, _Float16, -) +DEF_OP_V (neg, 4, _Float16, -) +DEF_OP_V (neg, 8, _Float16, -) +DEF_OP_V (neg, 16, _Float16, -) +DEF_OP_V (neg, 32, _Float16, -) +DEF_OP_V (neg, 64, _Float16, -) +DEF_OP_V (neg, 128, _Float16, -) +DEF_OP_V (neg, 256, _Float16, -) +DEF_OP_V (neg, 512, _Float16, -) +DEF_OP_V (neg, 1024, _Float16, -) +DEF_OP_V (neg, 2048, _Float16, -) + +DEF_OP_V (neg, 2, float, -) +DEF_OP_V (neg, 4, float, -) +DEF_OP_V (neg, 8, float, -) +DEF_OP_V (neg, 16, float, -) +DEF_OP_V (neg, 32, float, -) +DEF_OP_V (neg, 64, float, -) +DEF_OP_V (neg, 128, float, -) +DEF_OP_V (neg, 256, float, -) +DEF_OP_V (neg, 512, float, -) +DEF_OP_V (neg, 1024, float, -) + +DEF_OP_V (neg, 2, double, -) +DEF_OP_V (neg, 4, double, -) +DEF_OP_V (neg, 8, double, -) +DEF_OP_V (neg, 16, double, -) +DEF_OP_V (neg, 32, double, -) +DEF_OP_V (neg, 64, double, -) +DEF_OP_V (neg, 128, double, -) +DEF_OP_V (neg, 256, double, -) +DEF_OP_V (neg, 512, double, -) + +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */