From patchwork Tue Sep 19 10:39:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 141815 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp3287049vqi; Tue, 19 Sep 2023 03:49:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF3uR3j6L1xOz4dtqI3sVZ5PhrHsCZQUKxQLsW661sNXxYCyIGVdDm5U5Ul6IoXAJrdJHM0 X-Received: by 2002:a05:6a20:96d7:b0:152:3e16:3f0b with SMTP id hq23-20020a056a2096d700b001523e163f0bmr8622433pzc.46.1695120567212; Tue, 19 Sep 2023 03:49:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695120567; cv=none; d=google.com; s=arc-20160816; b=FSlLvS7UoUori4iI9yAxQvwtrr9aYW9nsO0DxY0LaFddrNi/hL5SxKq86LHRU87BUe A8NKFr39nq+yfYRTfnFegQZFrV6Ws+n5MAQAx8Ug2tCmbRtjxWxmCB69EfJ8M5Wm281S Zb6qj8Au/kvwsN+RcLQ87uEKHJa8nRjLX/VvS/2i/WVPeG0Pz7gSFcnBA0T9hTft9jOL qmzWK5JFsO1S9tGK6UUjasPiva2HldMmL78Bg1oiq32wMEAh62Gt2yYXtFhSIsE462Lk lW6pJejftK4VFYff92MvchZlAMgpO8S8VhkquOlreS+2TWOqDfNV6eXs8SowQ/hstpgR XY+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=s9BWuPFbmQNk9l4hxbmCGEzrUx7aAGGjTfc1yCObXGo=; fh=6Pv8GJxBPgLEOb7aBKvQ0v66ty4eQcOaKyfCFyguvUU=; b=0wsRZSDuPh71eKK2qKr8x1WITR/68595+w0DPxZ+LdA8e5NAMjtKJndUJWIK6y83RC aHF6h21k+8XtDIzVkycPzIIGCKxXP+8WW3K1LN/DtOe2hTZ0FKd+/1UDXbkOW3X9p5LM 8GcFRCP1P9hOYkAlSXBKeABpMZy1hIN49RiTiTH+w9JYs/2QEEn8/RR/RsSh6yE4GU3U fS3hiBdldrrYBmTAJjmnLDiI2ne4Urou8TLkkhoPoYRpGG5h3BhiiNXOc/HbwG5HrF0n NLXIocFx9X0vo5erFZO742CLpcO+3m4HxpUamig1dEBR1A9B4lcVwo0TB2EuPkgoI6Kn OfyA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id ef6-20020a056a002c8600b0069029c49b66si9489201pfb.60.2023.09.19.03.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 03:49:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 43F2B802B046; Tue, 19 Sep 2023 03:39:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbjISKjq (ORCPT + 26 others); Tue, 19 Sep 2023 06:39:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231580AbjISKjb (ORCPT ); Tue, 19 Sep 2023 06:39:31 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D2112F0; Tue, 19 Sep 2023 03:39:22 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3E6FC15; Tue, 19 Sep 2023 03:39:59 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.101.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 86DA23F67D; Tue, 19 Sep 2023 03:39:20 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Icenowy Zheng , Mark Brown , Jernej Skrabec , Samuel Holland , Shengyu Qu , Martin Botka , Matthew Croughan , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: mfd: x-powers,axp152: make interrupt optional for more chips Date: Tue, 19 Sep 2023 11:39:12 +0100 Message-Id: <20230919103913.463156-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919103913.463156-1-andre.przywara@arm.com> References: <20230919103913.463156-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 19 Sep 2023 03:39:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777462743490136991 X-GMAIL-MSGID: 1777462743490136991 All X-Powers PMICs described by this binding have an IRQ pin, and so far (almost) all boards connected this to some NMI pin or GPIO on the SoC they are connected to. However we start to see boards that omit this connection, and technically the IRQ pin is not essential to the basic PMIC operation. The existing Linux driver allows skipping the IRQ pin setup for two chips already, so update the binding to also make the DT property optional for the missing chip. And while we are at it, add the AXP313a to that list, as they are actually boards out there not connecting the IRQ pin. This allows to have DTs correctly describing those boards not wiring up the interrupt. Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml index 9ad55746133b5..06f1779835a1e 100644 --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml @@ -67,7 +67,10 @@ allOf: properties: compatible: contains: - const: x-powers,axp305 + enum: + - x-powers,axp15060 + - x-powers,axp305 + - x-powers,axp313a then: required: From patchwork Tue Sep 19 10:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 141814 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp3283957vqi; Tue, 19 Sep 2023 03:45:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBkBnGwPKsd8+k52y4hlri/TxwVEgiQJ3UlWyoTbKIU5uFUAdPZDf49zcZiIigsi9T/Wry X-Received: by 2002:a17:90b:350e:b0:268:5620:cfc7 with SMTP id ls14-20020a17090b350e00b002685620cfc7mr10382315pjb.30.1695120330782; Tue, 19 Sep 2023 03:45:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695120330; cv=none; d=google.com; s=arc-20160816; b=XQ0TLmNVpUSYM8T+U1pgZCMPJ9Rbqayju4wu2rWzQe8s4vYafX0Xl14RF6RnLyzOAI zlcdjhGx4zg0aw7fJ2ofYf0o/AcssJaF8SI11jNOhRY/s3/IdRujnNIa7FwZHD4rSdTU IV/48Sr9cBVt0FLnKq0quc0o4FBn5aW317CmxFN4kZHp+4DdUZHGd+ZzdZVx0Z3OKwUf KPwsYdMZDPhrMhuU/gPbeDUyiOhpL+KIEJgVBpn01lVyJWmgn0L57Ag31dkYjhsZr36G prWJLs4jXfee691UgXgBj0J3w9i9h5FCncvELdQKZuzNpWQE+3YEPPmZilVyKQr3Jxiw DqUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=wwVRyhwEe6p9KI4f4EwKflg90SeJf00atJulMXpOEow=; fh=6Pv8GJxBPgLEOb7aBKvQ0v66ty4eQcOaKyfCFyguvUU=; b=AE0CVZIaBgwxc6JPAug9D5ptkekuv7h+w7N0Mm0DmQqrFsCM+cXzgvg7GAGhU8WXj4 zlyjz5bqiuUok4yHy8YO8hKbRmKP+Hmfhnp5tgReVVlEK3ayKRz8AZjXlaXH+JEn7KEK vKStAeGGKXPwj60LF4PeyQuxwFrslf2UcxzfaNkEchWYdy2PKCa47hATB7m2cBZefG2m PhpUXcxyE7nRsStbId54MFXYqtz9tKZFhjhgf5CGhwLxoOhQN1sE01DTeK+fCTbPNhqE ByQF9MbTkXBemcThCXDK7a03bre32KjXVcfSrOf3hIVJoHnrjWmj0QVqpRwnFYywNo99 yoXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id l5-20020a17090a850500b00274cd892b39si5153537pjn.132.2023.09.19.03.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 03:45:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 53FD9826EDA4; Tue, 19 Sep 2023 03:40:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231821AbjISKjv (ORCPT + 26 others); Tue, 19 Sep 2023 06:39:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbjISKjc (ORCPT ); Tue, 19 Sep 2023 06:39:32 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0BC1FEA; Tue, 19 Sep 2023 03:39:25 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1353AFEC; Tue, 19 Sep 2023 03:40:02 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.101.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B9EF23F67D; Tue, 19 Sep 2023 03:39:22 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Icenowy Zheng , Mark Brown , Jernej Skrabec , Samuel Holland , Shengyu Qu , Martin Botka , Matthew Croughan , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] mfd: axp20x: Generalise handling without interrupt Date: Tue, 19 Sep 2023 11:39:13 +0100 Message-Id: <20230919103913.463156-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919103913.463156-1-andre.przywara@arm.com> References: <20230919103913.463156-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 19 Sep 2023 03:40:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777462496148445941 X-GMAIL-MSGID: 1777462496148445941 At the moment we allow the AXP15060 and the AXP806 PMICs to omit the interrupt line to the SoC, and we skip registering the PEK (power key) driver in this case, since that crashes when no IRQ is described in the DT node. The IRQ pin potentially not being connected to anything does affect more PMICs, though, and the PEK driver is not the only one requiring an interrupt: at least the AC power supply driver crashes in a similar fashion. Generalise the handling of AXP MFD devices when the platform tables describe no interrupt, by allowing each device to specify an alternative MFD list for this case. If no specific alternative is specified, we go with the safe default of "just the regulators", which matches the current situation. This enables new devices using the AXP313a PMIC, but not connecting the IRQ pin. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/mfd/axp20x.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 87603eeaa2770..d93189b0230de 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -1133,6 +1133,8 @@ int axp20x_match_device(struct axp20x_dev *axp20x) struct device *dev = axp20x->dev; const struct acpi_device_id *acpi_id; const struct of_device_id *of_id; + const struct mfd_cell *cells_no_irq = NULL; + int nr_cells_no_irq = 0; if (dev->of_node) { of_id = of_match_device(dev->driver->of_match_table, dev); @@ -1207,14 +1209,15 @@ int axp20x_match_device(struct axp20x_dev *axp20x) * if there is no interrupt line. */ if (of_property_read_bool(axp20x->dev->of_node, - "x-powers,self-working-mode") && - axp20x->irq > 0) { + "x-powers,self-working-mode")) { axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells); axp20x->cells = axp806_self_working_cells; } else { axp20x->nr_cells = ARRAY_SIZE(axp806_cells); axp20x->cells = axp806_cells; } + nr_cells_no_irq = ARRAY_SIZE(axp806_cells); + cells_no_irq = axp806_cells; axp20x->regmap_cfg = &axp806_regmap_config; axp20x->regmap_irq_chip = &axp806_regmap_irq_chip; break; @@ -1238,24 +1241,8 @@ int axp20x_match_device(struct axp20x_dev *axp20x) axp20x->regmap_irq_chip = &axp803_regmap_irq_chip; break; case AXP15060_ID: - /* - * Don't register the power key part if there is no interrupt - * line. - * - * Since most use cases of AXP PMICs are Allwinner SOCs, board - * designers follow Allwinner's reference design and connects - * IRQ line to SOC, there's no need for those variants to deal - * with cases that IRQ isn't connected. However, AXP15660 is - * used by some other vendors' SOCs that didn't connect IRQ - * line, we need to deal with this case. - */ - if (axp20x->irq > 0) { - axp20x->nr_cells = ARRAY_SIZE(axp15060_cells); - axp20x->cells = axp15060_cells; - } else { - axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells); - axp20x->cells = axp_regulator_only_cells; - } + axp20x->nr_cells = ARRAY_SIZE(axp15060_cells); + axp20x->cells = axp15060_cells; axp20x->regmap_cfg = &axp15060_regmap_config; axp20x->regmap_irq_chip = &axp15060_regmap_irq_chip; break; @@ -1263,6 +1250,23 @@ int axp20x_match_device(struct axp20x_dev *axp20x) dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant); return -EINVAL; } + + /* + * Use an alternative cell array when no interrupt line is connected, + * since IRQs are required by some drivers. + * The default is the safe "regulator-only", as this works fine without + * an interrupt specified. + */ + if (axp20x->irq <= 0) { + if (cells_no_irq) { + axp20x->nr_cells = nr_cells_no_irq; + axp20x->cells = cells_no_irq; + } else { + axp20x->nr_cells = ARRAY_SIZE(axp_regulator_only_cells); + axp20x->cells = axp_regulator_only_cells; + } + } + dev_info(dev, "AXP20x variant %s found\n", axp20x_model_names[axp20x->variant]);