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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ox29-20020a170907101d00b0099bcadfde72si8321287ejb.364.2023.09.17.19.55.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Sep 2023 19:55:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D5C31385772D for ; Mon, 18 Sep 2023 02:54:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id C68673858D32 for ; Mon, 18 Sep 2023 02:54:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C68673858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1695005662tjh9uzia Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 18 Sep 2023 10:54:21 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 3M0okmaRx3i6VuFE1BDExbDFnIdGXQJ2xBiydwEyviyUFZEteSCx80sdZ7ML6 K8CPtT4LPQVEe0UJfo1mUpHkAZt1RlQB/WLbs6Oh7Zb2jCZL+zCbMHgPaQeQeT1Iu7RLBSf s8JGyj5rUh7kPmBWZIGJkDbaPy/Kz86mLOuVEQGCA82ROhPsEnZgwFSVMcnDsi8+MJOh3N/ BAv9GLT3uNxWfq3Gf2QL4vbwHw3ex+bOvoGq1O1E9TuJQea88+y3btprVVZqguaKBV8lHET uMHzf1sWMRTwrdalYkRXX70ZsRTm7vY60FzohVRFrNdIMuM9iGxzVA1w6HaX7rC/zV6ti2i 5tfGERL1WyZVzyus+2tbyOjs/YVyWgEgAjskd/HldVxT/hNo01vKTx2eUnv98LUcx2NdccI fRz6fcmrXyo= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3666536329870032074 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] Date: Mon, 18 Sep 2023 10:54:08 +0800 Message-Id: <20230918025408.2591026-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777342300675964223 X-GMAIL-MSGID: 1777342300675964223 Consider those VLS patterns are the same VLA patterns. Now extend VI -> V_VLSI and VF -> V_VLSF. Then remove the redundant codes of VLS patterns. gcc/ChangeLog: * config/riscv/autovec-vls.md (3): Deleted. (copysign3): Ditto. (xorsign3): Ditto. (2): Ditto. * config/riscv/autovec.md: Extend VLS modes. --- gcc/config/riscv/autovec-vls.md | 138 -------------------------------- gcc/config/riscv/autovec.md | 44 +++++----- 2 files changed, 22 insertions(+), 160 deletions(-) diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index d4ed2081537..3488f452e5d 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -194,141 +194,3 @@ } [(set_attr "type" "vector")] ) - -;; ------------------------------------------------------------------------- -;; ---- [INT] Binary operations -;; ------------------------------------------------------------------------- -;; Includes: -;; - vadd.vv/vsub.vv/... -;; - vadd.vi/vsub.vi/... -;; ------------------------------------------------------------------------- - -(define_insn_and_split "3" - [(set (match_operand:VLSI 0 "register_operand") - (any_int_binop_no_shift:VLSI - (match_operand:VLSI 1 "") - (match_operand:VLSI 2 "")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - riscv_vector::emit_vlmax_insn (code_for_pred (, mode), - riscv_vector::BINARY_OP, operands); - DONE; -} -[(set_attr "type" "vector")] -) - -;; ------------------------------------------------------------------------- -;; ---- [FP] Binary operations -;; ------------------------------------------------------------------------- -;; Includes: -;; - vfadd.vv/vfsub.vv/vfmul.vv/vfdiv.vv -;; - vfadd.vf/vfsub.vf/vfmul.vf/vfdiv.vf -;; ------------------------------------------------------------------------- -(define_insn_and_split "3" - [(set (match_operand:VLSF 0 "register_operand") - (any_float_binop:VLSF - (match_operand:VLSF 1 "") - (match_operand:VLSF 2 "")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - riscv_vector::emit_vlmax_insn (code_for_pred (, mode), - riscv_vector::BINARY_OP_FRM_DYN, operands); - DONE; -} -[(set_attr "type" "vector")] -) - -;; ------------------------------------------------------------------------- -;; Includes: -;; - vfmin.vv/vfmax.vv -;; - vfmin.vf/vfmax.vf -;; - fmax/fmaxf in math.h -;; ------------------------------------------------------------------------- -(define_insn_and_split "3" - [(set (match_operand:VLSF 0 "register_operand") - (any_float_binop_nofrm:VLSF - (match_operand:VLSF 1 "") - (match_operand:VLSF 2 "")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - riscv_vector::emit_vlmax_insn (code_for_pred (, mode), - riscv_vector::BINARY_OP, operands); - DONE; -} -[(set_attr "type" "vector")] -) - -;; ------------------------------------------------------------------------- -;; Includes: -;; - vfsgnj.vv -;; - vfsgnj.vf -;; ------------------------------------------------------------------------- -(define_insn_and_split "copysign3" - [(set (match_operand:VLSF 0 "register_operand") - (unspec:VLSF - [(match_operand:VLSF 1 "register_operand") - (match_operand:VLSF 2 "register_operand")] UNSPEC_VCOPYSIGN))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, mode), - riscv_vector::BINARY_OP, operands); - DONE; - } - [(set_attr "type" "vector")] -) - -;; ------------------------------------------------------------------------- -;; Includes: -;; - vfsgnjx.vv -;; - vfsgnjx.vf -;; ------------------------------------------------------------------------- -(define_insn_and_split "xorsign3" - [(set (match_operand:VLSF 0 "register_operand") - (unspec:VLSF - [(match_operand:VLSF 1 "register_operand") - (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, mode), - riscv_vector::BINARY_OP, operands); - DONE; - } -) - -;; ------------------------------------------------------------------------------- -;; ---- [INT] Unary operations -;; ------------------------------------------------------------------------------- -;; Includes: -;; - vneg.v/vnot.v -;; ------------------------------------------------------------------------------- - -(define_insn_and_split "2" - [(set (match_operand:VLSI 0 "register_operand") - (any_int_unop:VLSI - (match_operand:VLSI 1 "register_operand")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - insn_code icode = code_for_pred (, mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); - DONE; -} -[(set_attr "type" "vector")] -) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 8d3ad9f3add..72a8d5307a4 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -420,10 +420,10 @@ ;; ------------------------------------------------------------------------- (define_insn_and_split "3" - [(set (match_operand:VI 0 "register_operand") - (any_int_binop_no_shift:VI - (match_operand:VI 1 "") - (match_operand:VI 2 "")))] + [(set (match_operand:V_VLSI 0 "register_operand") + (any_int_binop_no_shift:V_VLSI + (match_operand:V_VLSI 1 "") + (match_operand:V_VLSI 2 "")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -985,9 +985,9 @@ ;; - vneg.v/vnot.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "2" - [(set (match_operand:VI 0 "register_operand") - (any_int_unop:VI - (match_operand:VI 1 "register_operand")))] + [(set (match_operand:V_VLSI 0 "register_operand") + (any_int_unop:V_VLSI + (match_operand:V_VLSI 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1516,10 +1516,10 @@ ;; - vfadd.vf/vfsub.vf/... ;; ------------------------------------------------------------------------- (define_insn_and_split "3" - [(set (match_operand:VF 0 "register_operand") - (any_float_binop:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_binop:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1537,10 +1537,10 @@ ;; - vfmin.vf/vfmax.vf ;; ------------------------------------------------------------------------- (define_insn_and_split "3" - [(set (match_operand:VF 0 "register_operand") - (any_float_binop_nofrm:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_binop_nofrm:V_VLSF + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1563,10 +1563,10 @@ ;; Leave the pattern like this as to still allow combine to match ;; a negated copysign (see vector.md) before adding the UNSPEC_VPREDICATE later. (define_insn_and_split "copysign3" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (unspec:VF - [(match_operand:VF 1 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))] + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (unspec:V_VLSF + [(match_operand:V_VLSF 1 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1585,9 +1585,9 @@ ;; - vfsgnjx.vf ;; ------------------------------------------------------------------------------- (define_expand "xorsign3" - [(match_operand:VF 0 "register_operand") - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand")] + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand")] "TARGET_VECTOR" { riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, mode),