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Fri, 15 Sep 2023 11:49:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777167584846261237 X-GMAIL-MSGID: 1777167584846261237 Difference layerscape chip have not difference exit_from_l2() method. Using function pointer for ls1028. It prepare for other layerscape suspend/resume support. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-layerscape.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index b931d597656f6..20c48c06e2248 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -39,6 +39,8 @@ struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; + void (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; }; @@ -180,6 +182,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .exit_from_l2 = ls_pcie_exit_from_l2, }; static const struct of_device_id ls_pcie_of_match[] = { @@ -213,7 +216,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->pp.ops = &ls_pcie_host_ops; + pci->pp.ops = pcie->drvdata->ops ? pcie->drvdata->ops : &ls_pcie_host_ops; pcie->pci = pci; @@ -251,7 +254,7 @@ static int ls_pcie_resume_noirq(struct device *dev) if (!pcie->drvdata->pm_support) return 0; - ls_pcie_exit_from_l2(&pcie->pci->pp); + pcie->drvdata->exit_from_l2(&pcie->pci->pp); return dw_pcie_resume_noirq(pcie->pci); } From patchwork Fri Sep 15 18:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 140646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1280322vqi; Fri, 15 Sep 2023 12:44:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFCWLsGQ6gMtNdHpsd7qiSzhGc8RVjcfy7G4mfme/l4kwNm9G9uJ5n/epSo6rdLwipy+14t X-Received: by 2002:a17:903:245:b0:1c3:fa9a:1e41 with SMTP id j5-20020a170903024500b001c3fa9a1e41mr2877705plh.45.1694807070665; Fri, 15 Sep 2023 12:44:30 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1694807070; cv=pass; d=google.com; s=arc-20160816; b=d+FaCCCoASWQpOqHi1jb9/MT0yLoz06MiDa98FKiO1ei/dZP6C1schgako0CFE4Ikv 6u5vtauTo++MnG+/0JpUEXiVPRXaUlkIeyCEJCrX/jvx3tcHe2TlI/uofb6AelJmol9e H6i9S8G95dKdxjCKAOLL4K7CAicN12LGoORevEajiN27/KvHVsxXJFrrI5XShvQQJ/7q e6MG8E35mRJGyryW1dfQ6E7TpA9i9EJUMVXwKZu39q7PI7XECGABzAt6HbrYAvdNwTs9 QL8eMY0dOLiL3zfEzTQC0C17QUWHFH+wVTazdOHWFZS367deIn7rThWif4OQxkKcNDXc Msqw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QumOeoWtlkpcZNKxeTPO0UIw55ZdtSB9pWNTJIivito=; fh=oooHTiAXK44aMf+XQcyrMApjhhRxQuk8M9D/ohRv+pM=; b=SNK8dXJIhUiz9s3XHa9O+mBEwxo6879vKF6gPVW7UetQnaryCzWZPu3B0TJTvQF3Uv 5vV/F8YaR1YQShGOuj49hOIVRbssyIZNqDbevdOJKPE/dpnQlIueAwyiixb6zNvAzcyz s3NtBSDa/VBDFyQVfMo9dGfX+0p85NgQeRA1yO+pIbGkptXhZEoyrpn2YpnN+wv9ChPh uKzWCH/kTO4nOzFAfbKGvfgYecroZmPWUQCFDi66EG7nVcUz7L63K+Mzp+MoBN4aLssy xqa1qZnMOoBvav9cix3BlXav0IA5+CYM3IfRB3LBpWJqBR7+1XaRPMwfEe4hd4dZ/rY0 JdCQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=ALrIEt9K; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from morse.vger.email (morse.vger.email. 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Fri, 15 Sep 2023 11:48:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777134018558748423 X-GMAIL-MSGID: 1777134018558748423 ls1021a add suspend/resume support. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-layerscape.c | 88 ++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 20c48c06e2248..bc5a8ff1a26ce 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,6 +35,12 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { @@ -48,6 +54,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -170,13 +178,91 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val |= PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); + + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val &= ~PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); +} + +static void ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val |= PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val &= ~PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); +} + +static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + struct device *dev = pcie->pci->dev; + u32 index[2]; + int ret; + + ret = ls_pcie_host_init(pp); + if (ret) + return ret; + + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + ret = PTR_ERR(pcie->scfg); + dev_err(dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return ret; + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) { + pcie->scfg = NULL; + return ret; + } + + pcie->index = index[1]; + + return ret; +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls1021a_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { From patchwork Fri Sep 15 18:43:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 140727 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1350315vqi; Fri, 15 Sep 2023 15:15:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHn32mDGt6UpxmEkwEkxXl7Smh8fTMCKwi4QP1E9hfu3E6pD5lADthOw41BDkV/yDVc7QKk X-Received: by 2002:a17:903:32c5:b0:1c3:3461:75b5 with SMTP id i5-20020a17090332c500b001c3346175b5mr3668348plr.0.1694816148087; Fri, 15 Sep 2023 15:15:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1694816148; cv=pass; d=google.com; s=arc-20160816; b=s1a0JAam6Y1Fll0WNJxfpRndN7VmPTbo9wWIg/srkRv38R7YSyl02HnUbDGGEYjziz qUcs+zeIK6DXWWQB/DpdZLVvVd+BIL2D6jrr7brLi/3qp1ZXHrgMDX9OOgg63IzVKsxg AK9hhION8YFTuofbVNUFnF8VZELNB3aeI1URjq4ee43I8UP3AxAGJ4x2Mm88kJEAZh1z tEUAfWBGr0nH8j3Mv5e5n2IWaN3SwMrHxCysbGvfT84u55DJNJ6U8U5ERK0MrYwt8OBq 28eMQNNqgjMkZVqt9ehCiqH88d7HxP5WwDX79/J1Dxq80ET17X37ocFzwvvx7kl5+TTx UxrA== ARC-Message-Signature: i=2; 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Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-layerscape.c | 91 ++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index bc5a8ff1a26ce..debabb9bb41f4 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -41,10 +41,20 @@ #define SCFG_PEXSFTRSTCR 0x190 #define PEXSR(idx) BIT(idx) +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const u32 lut_off; const struct dw_pcie_host_ops *ops; void (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; @@ -54,6 +64,7 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + void __iomem *lut_base; struct regmap *scfg; int index; bool big_endian; @@ -116,6 +127,23 @@ static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) iowrite32(val, pcie->pf_base + off); } +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->lut_base + off); + + return ioread32(pcie->lut_base + off); +} + +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + iowrite32be(val, pcie->lut_base + off); + else + iowrite32(val, pcie->lut_base + off); +} + + static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -249,6 +277,54 @@ static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) return ret; } +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val |= PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); + + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val &= ~PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); +} + +static void ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, @@ -265,6 +341,18 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { + .host_init = ls1021a_pcie_host_init, /* the same as ls1021 */ + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .lut_off = 0x10000, + .pm_support = true, + .ops = &ls1043a_pcie_host_ops, + .exit_from_l2 = ls1043a_pcie_exit_from_l2, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, @@ -275,7 +363,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, @@ -314,6 +402,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; if (!ls_pcie_is_bridge(pcie)) return -ENODEV;