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Signed-off-by: xiaoguang.xing Signed-off-by: Wang Chen --- arch/riscv/Kconfig.socs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6833d01e2e70..fc7b5e6c7def 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -110,4 +110,14 @@ config SOC_CANAAN_K210_DTB_SOURCE endif # ARCH_CANAAN +config ARCH_SOPHGO + bool "Sophgo SoCs" + select SIFIVE_PLIC + help + This enables support for Sophgo SoC platform hardware. + SOPHGO is committed to become a provider of universal + computing power, focusing on the development and + promotion of computing power products such as AI and + RISC-V CPU. + endmenu # "SoC selection" From patchwork Fri Sep 15 07:14:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1022401vqi; Fri, 15 Sep 2023 05:58:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzVWiyciYLkcUrDxgqw0iBt7h0k0gtpCnRAFOUnEdmOkzBe0LlWQD7iafdHZ67nxUSDQS1 X-Received: by 2002:a05:6a00:24d5:b0:68e:2fcd:f4de with SMTP id d21-20020a056a0024d500b0068e2fcdf4demr2167182pfv.20.1694782737081; Fri, 15 Sep 2023 05:58:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694782737; cv=none; d=google.com; s=arc-20160816; b=zsbAkRxd9cyV96xx4oMdFtk6mmmApmnkJbgZg7Mb08WWHKsS/Sy7acP4/qvtmHvkgV Lq3Q9GnqFAiNXbZjARnqzt9GYm7QYezvWMmcD8srDRP+9KFpCk2NYdouYlP8kPc0U6vj FfSD3QUdrP3SMj6qpK6TVIZoKjhFNpzhVN6IYjiSxhyUtBfJYUYS652nxUnoTLAzfYgF KTIxGBJWOq0z0lSYJc0l4DcC3GAw1ctxLZsGT8eF9wmKMRtYwJL3UVBXK7KAeEYjNtHk 9xlj3HdAvJqkekExZUgA+xlKLAhFQJPyl/0XgNW4GiVFBUR2nmDS0KBf0KHpUSOV17Y8 OIhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=xPt+lflGxmD7kew86V+AaK7Q6nPGEAHxfdx7vSqNo0w=; fh=uX8GTfQZ4oxMzeIzkttJn/ljCrddTXNVgdIuxqRbyug=; b=rg9yOLUQZuRBM7zROUhI9rSRB8vqYWdWDP26YV7ov65cAulcyMl7O7xOIGniuNJRu3 X3ryr6jIE4dt7yGgsgOIVXdBN1wdmGUdDIHwywN2t8vrZ143aAJEe4ItZOkrajiKb21a 8H0PLDYLzNagD5gdjDh994gg8oohWM5OX63ZRxGWDmbyhfB1r3GUG2/DI9MMuRjBOQm9 SQVgB2SiowJhf3o4hT2dEgGKB5FEJizduBlxzDjm4xAg4tNqohUB6Mhb/4SRxH79QlMO MQuygFmy8zcr67ElA2UVUEEsRExOyEl5y7bGNRw37VPtWth+ny3pY1HmLz5lUFGfTmVF KTdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=ANaTPxcQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from pete.vger.email (pete.vger.email. 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Signed-off-by: Wang Chen Signed-off-by: Xiaoguang Xing --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 573578db9509..fcca9e070a9a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -863,6 +863,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milkv,.*": + description: MilkV Technology Co., Ltd "^miniand,.*": description: Miniand Tech "^minix,.*": @@ -1273,6 +1275,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sophgo,.*": + description: Sophgo Technology Inc. "^sourceparts,.*": description: Source Parts Inc. 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[1]: https://en.sophgo.com/product/introduce/sg2042.html [2]: https://milkv.io/pioneer Signed-off-by: Wang Chen Signed-off-by: Xiaoguang Xing Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++ MAINTAINERS | 6 ++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml new file mode 100644 index 000000000000..82468ae915db --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SoC-based boards + +maintainers: + - Chao Wei + - Xiaoguang Xing + +description: + Sophgo SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milkv,pioneer + - const: sophgo,sg2042 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..0e0d477dab38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20063,6 +20063,12 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c F: include/linux/sony-laptop.h +SOPHGO DEVICETREES +M: Xiaoguang Xing +M: Chao Wei +S: Maintained +F: Documentation/devicetree/bindings/riscv/sophgo.yaml + SOUND M: Jaroslav Kysela M: Takashi Iwai From patchwork Fri Sep 15 07:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1221360vqi; Fri, 15 Sep 2023 10:51:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH2lSogmew7+eIjmT1OgCb9APXdE+uoAFU8ebFc8+ESi2Q+GejwNuq4zsWvDVHvOOEULqb8 X-Received: by 2002:a05:6a21:7782:b0:141:d640:794a with SMTP id bd2-20020a056a21778200b00141d640794amr2434243pzc.39.1694800309805; Fri, 15 Sep 2023 10:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694800309; cv=none; d=google.com; s=arc-20160816; b=ovBjocbDxtnOxe7CsOw2etTJuofU1+SblN/vqhUkn+kHElLKMCcZke0v8RZrvrbWOC N30I4IrM6sZWqN7e/y07kHpMPI9i1+CekOGNbqV8S0iQ5zYuofaprTCDYD5+zdDQ6myt O9zZlXitBiGkH6NJaow15m3Zjq4kawN0/hrQD5YS5ZIIURvASUioCv65yRRYOl9IkDgu jMHhSAgcrMyx/f0UJkiiTe9C0gFmqC4HIGgMxrnIpDgC/afYKuqGqKc7JPZE+yteBH+f t/bJD4mF7g40j9iUyKfblbk7NxBNivNrf0/iepExs7x03CAUHTVBuvTsJDX9FDYQv5PY 6vmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=i5DdN2I9qJnXX8fUomCodux5qyyadXgZyIqOEcUZz9g=; fh=uX8GTfQZ4oxMzeIzkttJn/ljCrddTXNVgdIuxqRbyug=; b=p32rlv+pHSaPteQhO1PHofLHz0Q+kosiAHYgokF5iJVzRY8qP0+pgrNeO6WzkF0hrh o7wQ+xq8KQOSgoL4qlJvryNHJ0Nw1h+fKl0A5WsRRP+YfVSWOO3mgBEmpG1FeTpdjyPX unM9Jq9OEsS/5LMSMXF9UhShPhCTaRK29k4jrRGljlqWK+WjyMyNMp9EK5Af5z7Tz/y2 NpFCYByyrHY7brqL6TQDSvLGHc3yaJ82OTHcCr9B6Lo7r9DFosv5hVUbI2wuPcusiSjb 8WjF99wDPIjOJd9dZZUFjCF9dFQQKBqlFj9DKf81tiLTQHpHchWhP+YV/VF7zuRa5j2h LPXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=AnGHV8XH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from lipwig.vger.email (lipwig.vger.email. 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Notably, the C920 core is used in the SOPHGO SG2042 SoC. Signed-off-by: Wang Chen Signed-off-by: Xiaoguang Xing --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 38c0b5213736..185a0191bad6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74-mc - thead,c906 - thead,c910 + - thead,c920 - const: riscv - items: - enum: From patchwork Fri Sep 15 07:23:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp878074vqi; Fri, 15 Sep 2023 01:00:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQia/T5F7VkAgJ/dNo1fpVzElsCoq50Mqw5Ic0vTyzTzn7lJwrzv6w1xnyp+YjF8G/xUsn X-Received: by 2002:a17:902:ec83:b0:1c3:4361:ca18 with SMTP id x3-20020a170902ec8300b001c34361ca18mr1007449plg.5.1694764826251; Fri, 15 Sep 2023 01:00:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694764826; cv=none; d=google.com; s=arc-20160816; b=KPRCVQLi6M3qsLdiDFTv2zrL8a3iaTIUk/2RJaDEwYlCTf5PFa4EVVtaVrkJsMxri9 mKM/TBl+WH/HAXH+TcYlJWpy21z8N09aZtMNCJuyVebMAUYkB12U5/jnaEus+t1RHyyD EaDxC+ju6cVq2D+JymQm0B0MMiOoPbKPXBUWyYjNqX4anH5jysBe1HhoZUC8S2UJOIOk ygKyJdmR1tTDX8A7adq5DHQl3KH3KDlgy+ENN7ALV2cKM4tvldg084K9gq3HZCDq6+oM J9xbhQLly86cKTWiw6mAqAWpaKOda94oQz+KJ5k4r7gWKHk4kK7IVojtd/jc/UbdPSZg wjIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=QaNp6vd76nBX4EIgc/17q2XiC73X4sxuT4uDWwfKOL4=; fh=uX8GTfQZ4oxMzeIzkttJn/ljCrddTXNVgdIuxqRbyug=; b=qMntmq1U+zOUzjJ6IAQ0WwUDwA/CUvNiKqA/oNyxJGucsqoWdpAf6aXUi79YwPEG19 mbUwzXXVy6vFW1H+TwaaubB7FjPW/L20afH5XVlVBWbzoCHRSpKej6BtPDBiPPWzValg Xtd7tVwXBsmIXBua4UQQ001QNKszu/HTK1JziHEhM7rAdMMz/Yun0Y5LN4mbQHMvSkVL 0tL2DeukNbAmiC9x2Sc9L7bN+IO70dmUOWAkYBBw5nTPX9TPFqeSXH1MJsLEOLjtZE0Z E8KDYSbUuROFFT7pFnhQxPdrINfrYrypicJUK1NqhddsWlCwE4ujmUuxNE2V7KtIxV9l 3p9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=HWq8sVN8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from lipwig.vger.email (lipwig.vger.email. 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Signed-off-by: Wang Chen Signed-off-by: Xiaoguang Xing --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index dc1f28e55266..3abb1f68ea62 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,6 +66,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - thead,th1520-plic + - sophgo,sg2042-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 From patchwork Fri Sep 15 07:24:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp897621vqi; Fri, 15 Sep 2023 01:47:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHNjsg7dHcRfgXSY9ofgb/o1vpq90I4fZilnWU1mPaazEXNbnb0P1f8f+saZ8pXU3OottnE X-Received: by 2002:a05:6358:290b:b0:139:9dda:8344 with SMTP id y11-20020a056358290b00b001399dda8344mr1599207rwb.19.1694767627900; Fri, 15 Sep 2023 01:47:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694767627; cv=none; d=google.com; s=arc-20160816; b=TroRH1r4LRh19WBHujwB/VxC6xM6MLs/LWuiOGEO0DJM4xHRh5TiZgPcphlpDNQfGq q1H+aoS6tBZl/wqlQTI7tLECRunAR/cdK4TfFQBh8u9KLA7yWWKpLuR0NFjWTIjd3MjY vXHFQNSIwpIMo18oKVG5XgvLByAobKChmxm71p03ND9vsDJxtSEPaMbSJgTrsC6pDW+S h2sDeKDjxT+PeMfyqQTZ1Mgeh2KFlL4q6SEmMlHufLt+g4FvzlWnzVuxfTnYJPveQgCo h68ezZVtmJ4bJfl1QzWYshRUuUnjn81PMiWw3IoDKTCDWrGky/QVYq4j4+YpCpWh18Uo Q72g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=FJzMSRsFGWXl1x3CI8KZnuJ0K/8zXSh3L5yWA+KvyC4=; fh=SoHMjjwKbOCJHkpPAb6ApbQYGCkORo5QgFo6HIEqHyk=; b=eSwVlH2dKBnbt2LyGEAIAiaItRpc2QUfpz93zGxYsCAviudzCYigqxYc17gI3TtN+8 o8BjES/Q/sFq3EVOpjoBxnykz3Pgsqegjqib51h2POkoGhwJqLZ4OlxPWyQFEolJdcbd w6Spms1mCwi8jJMrnQcak8MfjxuKbDNhff6O6ezQeWRUJfXtY9CFuEIlyvO17IrJN+1b s81qhX9x/WLfbgHn8jg4vhfBDGCic/SYOd7bQ3Z7/lwGGBQjuNVqwo9qyYxPYp/UFKny bJ9vPK2NwVYCSeIJKTMSFC7zpY3OXdr0CdS6SN+flkc43JRvc52+N1npU5XWvIG2CBez dEyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=H36TSCYr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from agentk.vger.email (agentk.vger.email. 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With the same compatible string, this will cause a mismatch when is processed by SBI. Add two new compatible string formatted like `C9xx-clint-xxx` to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict. Signed-off-by: Inochi Amaoto --- .../bindings/timer/sifive,clint.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a0185e15a42f..2a86b80c3f1e 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -39,6 +39,14 @@ properties: - allwinner,sun20i-d1-clint - thead,th1520-clint - const: thead,c900-clint + - items: + - enum: + - sophgo,sg2042-clint-mtimer + - const: thead,c900-clint-mtimer + - items: + - enum: + - sophgo,sg2042-clint-mswi + - const: thead,c900-clint-mswi - items: - const: sifive,clint0 - const: riscv,clint0 @@ -74,4 +82,22 @@ examples: <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; + - | + clint-mtimer@ac010000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac010000 0x00007ff8>; + }; + - | + clint-mswi@94000000 { + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x94000000 0x00004000>; + }; ... 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SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores which implements IMAFDC - 4 cores per cluster, 16 clusters on chip - ...... More info is available at [1]. [1]: https://en.sophgo.com/product/introduce/sg2042.html Currently only support booting into console with only uart enabled, other features will be added soon later. Signed-off-by: Xiaoguang Xing Signed-off-by: Inochi Amaoto Signed-off-by: Wang Chen --- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1794 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 513 ++++++ 3 files changed, 2308 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 0e0d477dab38..b74d505003e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20068,6 +20068,7 @@ M: Xiaoguang Xing M: Chao Wei S: Maintained F: Documentation/devicetree/bindings/riscv/sophgo.yaml +F: arch/riscv/boot/dts/sophgo/ SOUND M: Jaroslav Kysela diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi new file mode 100644 index 000000000000..0b6cd3559693 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -0,0 +1,1794 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu-map { + socket0 { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu16>; + }; + core1 { + cpu = <&cpu17>; + }; + core2 { + cpu = <&cpu18>; + }; + core3 { + cpu = <&cpu19>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu20>; + }; + core1 { + cpu = <&cpu21>; + }; + core2 { + cpu = <&cpu22>; + }; + core3 { + cpu = <&cpu23>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + + cluster6 { + core0 { + cpu = <&cpu24>; + }; + core1 { + cpu = <&cpu25>; + }; + core2 { + cpu = <&cpu26>; + }; + core3 { + cpu = <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu = <&cpu28>; + }; + core1 { + cpu = <&cpu29>; + }; + core2 { + cpu = <&cpu30>; + }; + core3 { + cpu = <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu = <&cpu32>; + }; + core1 { + cpu = <&cpu33>; + }; + core2 { + cpu = <&cpu34>; + }; + core3 { + cpu = <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu = <&cpu36>; + }; + core1 { + cpu = <&cpu37>; + }; + core2 { + cpu = <&cpu38>; + }; + core3 { + cpu = <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu = <&cpu48>; + }; + core1 { + cpu = <&cpu49>; + }; + core2 { + cpu = <&cpu50>; + }; + core3 { + cpu = <&cpu51>; + }; + }; + + cluster11 { + core0 { + cpu = <&cpu52>; + }; + core1 { + cpu = <&cpu53>; + }; + core2 { + cpu = <&cpu54>; + }; + core3 { + cpu = <&cpu55>; + }; + }; + + cluster12 { + core0 { + cpu = <&cpu40>; + }; + core1 { + cpu = <&cpu41>; + }; + core2 { + cpu = <&cpu42>; + }; + core3 { + cpu = <&cpu43>; + }; + }; + + cluster13 { + core0 { + cpu = <&cpu44>; + }; + core1 { + cpu = <&cpu45>; + }; + core2 { + cpu = <&cpu46>; + }; + core3 { + cpu = <&cpu47>; + }; + }; + + cluster14 { + core0 { + cpu = <&cpu56>; + }; + core1 { + cpu = <&cpu57>; + }; + core2 { + cpu = <&cpu58>; + }; + core3 { + cpu = <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu = <&cpu60>; + }; + core1 { + cpu = <&cpu61>; + }; + core2 { + cpu = <&cpu62>; + }; + core3 { + cpu = <&cpu63>; + }; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu1: cpu@1 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu2: cpu@2 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu3: cpu@3 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu4: cpu@4 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu5: cpu@5 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu6: cpu@6 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu7: cpu@7 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu8: cpu@8 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache4>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu8_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu9: cpu@9 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache4>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu9_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu10: cpu@10 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache4>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu10_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu11: cpu@11 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache4>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu11_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu12: cpu@12 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache5>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu12_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu13: cpu@13 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache5>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu13_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu14: cpu@14 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache5>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu14_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu15: cpu@15 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache5>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu15_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu16: cpu@16 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache2>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu16_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu17: cpu@17 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache2>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu17_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu18: cpu@18 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache2>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu18_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu19: cpu@19 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache2>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu19_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu20: cpu@20 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache3>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu20_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu21: cpu@21 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache3>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu21_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu22: cpu@22 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache3>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu22_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu23: cpu@23 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache3>; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + status = "okay"; + + cpu23_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu24: cpu@24 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache6>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu24_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu25: cpu@25 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache6>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu25_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu26: cpu@26 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache6>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu26_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu27: cpu@27 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache6>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu27_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu28: cpu@28 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache7>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu28_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu29: cpu@29 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache7>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu29_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu30: cpu@30 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache7>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu30_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu31: cpu@31 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache7>; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + status = "okay"; + + cpu31_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu32: cpu@32 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache8>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu32_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu33: cpu@33 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache8>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu33_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu34: cpu@34 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache8>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu34_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu35: cpu@35 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache8>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu35_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu36: cpu@36 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache9>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu36_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu37: cpu@37 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache9>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu37_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu38: cpu@38 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache9>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu38_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu39: cpu@39 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache9>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu39_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu40: cpu@40 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <40>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache12>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu40_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu41: cpu@41 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <41>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache12>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu41_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu42: cpu@42 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <42>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache12>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu42_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu43: cpu@43 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <43>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache12>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu43_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu44: cpu@44 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <44>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache13>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu44_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu45: cpu@45 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <45>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache13>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu45_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu46: cpu@46 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <46>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache13>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu46_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu47: cpu@47 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <47>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache13>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu47_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu48: cpu@48 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <48>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache10>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu48_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu49: cpu@49 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <49>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache10>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu49_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu50: cpu@50 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <50>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache10>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu50_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu51: cpu@51 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <51>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache10>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu51_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu52: cpu@52 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <52>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache11>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu52_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu53: cpu@53 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <53>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache11>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu53_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu54: cpu@54 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <54>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache11>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu54_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu55: cpu@55 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <55>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache11>; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + status = "okay"; + + cpu55_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu56: cpu@56 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <56>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache14>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu56_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu57: cpu@57 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <57>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache14>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu57_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu58: cpu@58 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <58>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache14>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu58_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu59: cpu@59 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <59>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache14>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu59_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu60: cpu@60 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <60>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache15>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu60_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu61: cpu@61 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <61>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache15>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu61_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu62: cpu@62 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <62>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache15>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu62_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + cpu63: cpu@63 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <63>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache15>; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + status = "okay"; + + cpu63_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + l2_cache0: l2-cache@0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache1: l2-cache@1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache2: l2-cache@2 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache3: l2-cache@3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache4: l2-cache@4 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache5: l2-cache@5 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache6: l2-cache@6 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache7: l2-cache@7 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache8: l2-cache@8 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache9: l2-cache@9 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache10: l2-cache@10 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache11: l2-cache@11 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache12: l2-cache@12 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache13: l2-cache@13 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache14: l2-cache@14 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + l2_cache15: l2-cache@15 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi new file mode 100644 index 000000000000..5c4b82f13207 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/dts-v1/; +#include + +#include "sg2042-cpus.dtsi" + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + compatible = "sophgo,sg2042"; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 25>, + <0 3 30>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>; + }; + + /* the mem node will be updated by ZSBL. */ + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x00000000>; + numa-node-id = <0>; + }; + memory@1 { + device_type = "memory"; + reg = <0x00000000 0x00000001 0x00000000 0x00000000>; + numa-node-id = <1>; + }; + memory@2 { + device_type = "memory"; + reg = <0x00000000 0x00000002 0x00000000 0x00000000>; + numa-node-id = <2>; + }; + memory@3 { + device_type = "memory"; + reg = <0x00000000 0x00000003 0x00000000 0x00000000>; + numa-node-id = <3>; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + linux,cma { + compatible = "shared-dma-pool"; + size = <0x00000000 0x10000000>; + alloc-ranges = <0x00000000 0xc0000000 + 0x00000000 0xd0000000>; + reusable; + linux,cma-default; + }; + }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000010>, + <0x00004 0x00000000 0x00000011>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x00008 0x00000000 0x00000027>, + <0x00009 0x00000000 0x00000028>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10008 0x00000000 0x00000001>, + <0x10009 0x00000000 0x00000002>, + <0x10010 0x00000000 0x00000010>, + <0x10011 0x00000000 0x00000011>, + <0x10012 0x00000000 0x00000012>, + <0x10013 0x00000000 0x00000013>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>, + <0x10030 0x00000000 0x0000001c>, + <0x10031 0x00000000 0x0000001b>; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0xfffffff8>, + <0x00004 0x00004 0xfffffff8>, + <0x00005 0x00005 0xfffffff8>, + <0x00006 0x00006 0xfffffff8>, + <0x00007 0x00007 0xfffffff8>, + <0x00008 0x00008 0xfffffff8>, + <0x00009 0x00009 0xfffffff8>, + <0x0000a 0x0000a 0xfffffff8>, + <0x10000 0x10000 0xfffffff8>, + <0x10001 0x10001 0xfffffff8>, + <0x10002 0x10002 0xfffffff8>, + <0x10003 0x10003 0xfffffff8>, + <0x10008 0x10008 0xfffffff8>, + <0x10009 0x10009 0xfffffff8>, + <0x10010 0x10010 0xfffffff8>, + <0x10011 0x10011 0xfffffff8>, + <0x10012 0x10012 0xfffffff8>, + <0x10013 0x10013 0xfffffff8>, + <0x10019 0x10019 0xfffffff8>, + <0x10021 0x10021 0xfffffff8>, + <0x10030 0x10030 0xfffffff8>, + <0x10031 0x10031 0xfffffff8>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint_mswi: clint-mswi@7094000000 { + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = < + &cpu0_intc 3 + &cpu1_intc 3 + &cpu2_intc 3 + &cpu3_intc 3 + &cpu4_intc 3 + &cpu5_intc 3 + &cpu6_intc 3 + &cpu7_intc 3 + &cpu8_intc 3 + &cpu9_intc 3 + &cpu10_intc 3 + &cpu11_intc 3 + &cpu12_intc 3 + &cpu13_intc 3 + &cpu14_intc 3 + &cpu15_intc 3 + &cpu16_intc 3 + &cpu17_intc 3 + &cpu18_intc 3 + &cpu19_intc 3 + &cpu20_intc 3 + &cpu21_intc 3 + &cpu22_intc 3 + &cpu23_intc 3 + &cpu24_intc 3 + &cpu25_intc 3 + &cpu26_intc 3 + &cpu27_intc 3 + &cpu28_intc 3 + &cpu29_intc 3 + &cpu30_intc 3 + &cpu31_intc 3 + &cpu32_intc 3 + &cpu33_intc 3 + &cpu34_intc 3 + &cpu35_intc 3 + &cpu36_intc 3 + &cpu37_intc 3 + &cpu38_intc 3 + &cpu39_intc 3 + &cpu40_intc 3 + &cpu41_intc 3 + &cpu42_intc 3 + &cpu43_intc 3 + &cpu44_intc 3 + &cpu45_intc 3 + &cpu46_intc 3 + &cpu47_intc 3 + &cpu48_intc 3 + &cpu49_intc 3 + &cpu50_intc 3 + &cpu51_intc 3 + &cpu52_intc 3 + &cpu53_intc 3 + &cpu54_intc 3 + &cpu55_intc 3 + &cpu56_intc 3 + &cpu57_intc 3 + &cpu58_intc 3 + &cpu59_intc 3 + &cpu60_intc 3 + &cpu61_intc 3 + &cpu62_intc 3 + &cpu63_intc 3 + >; + }; + + clint_mtimer0: clint-mtimer@70ac000000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu0_intc 7 + &cpu1_intc 7 + &cpu2_intc 7 + &cpu3_intc 7 + >; + }; + + clint_mtimer1: clint-mtimer@70ac010000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu4_intc 7 + &cpu5_intc 7 + &cpu6_intc 7 + &cpu7_intc 7 + >; + }; + + clint_mtimer2: clint-mtimer@70ac020000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu8_intc 7 + &cpu9_intc 7 + &cpu10_intc 7 + &cpu11_intc 7 + >; + }; + + clint_mtimer3: clint-mtimer@70ac030000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu12_intc 7 + &cpu13_intc 7 + &cpu14_intc 7 + &cpu15_intc 7 + >; + }; + + clint_mtimer4: clint-mtimer@70ac040000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu16_intc 7 + &cpu17_intc 7 + &cpu18_intc 7 + &cpu19_intc 7 + >; + }; + + clint_mtimer5: clint-mtimer@70ac050000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu20_intc 7 + &cpu21_intc 7 + &cpu22_intc 7 + &cpu23_intc 7 + >; + }; + + clint_mtimer6: clint-mtimer@70ac060000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu24_intc 7 + &cpu25_intc 7 + &cpu26_intc 7 + &cpu27_intc 7 + >; + }; + + clint_mtimer7: clint-mtimer@70ac070000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu28_intc 7 + &cpu29_intc 7 + &cpu30_intc 7 + &cpu31_intc 7 + >; + }; + + clint_mtimer8: clint-mtimer@70ac080000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu32_intc 7 + &cpu33_intc 7 + &cpu34_intc 7 + &cpu35_intc 7 + >; + }; + + clint_mtimer9: clint-mtimer@70ac090000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu36_intc 7 + &cpu37_intc 7 + &cpu38_intc 7 + &cpu39_intc 7 + >; + }; + + clint_mtimer10: clint-mtimer@70ac0a0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu40_intc 7 + &cpu41_intc 7 + &cpu42_intc 7 + &cpu43_intc 7 + >; + }; + + clint_mtimer11: clint-mtimer@70ac0b0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu44_intc 7 + &cpu45_intc 7 + &cpu46_intc 7 + &cpu47_intc 7 + >; + }; + + clint_mtimer12: clint-mtimer@70ac0c0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu48_intc 7 + &cpu49_intc 7 + &cpu50_intc 7 + &cpu51_intc 7 + >; + }; + + clint_mtimer13: clint-mtimer@70ac0d0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu52_intc 7 + &cpu53_intc 7 + &cpu54_intc 7 + &cpu55_intc 7 + >; + }; + + clint_mtimer14: clint-mtimer@70ac0e0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu56_intc 7 + &cpu57_intc 7 + &cpu58_intc 7 + &cpu59_intc 7 + >; + }; + + clint_mtimer15: clint-mtimer@70ac0f0000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu60_intc 7 + &cpu61_intc 7 + &cpu62_intc 7 + &cpu63_intc 7 + >; + }; + + intc: interrupt-controller@7090000000 { + compatible = "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff &cpu0_intc 9 + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9 + &cpu5_intc 0xffffffff &cpu5_intc 9 + &cpu6_intc 0xffffffff &cpu6_intc 9 + &cpu7_intc 0xffffffff &cpu7_intc 9 + &cpu8_intc 0xffffffff &cpu8_intc 9 + &cpu9_intc 0xffffffff &cpu9_intc 9 + &cpu10_intc 0xffffffff &cpu10_intc 9 + &cpu11_intc 0xffffffff &cpu11_intc 9 + &cpu12_intc 0xffffffff &cpu12_intc 9 + &cpu13_intc 0xffffffff &cpu13_intc 9 + &cpu14_intc 0xffffffff &cpu14_intc 9 + &cpu15_intc 0xffffffff &cpu15_intc 9 + &cpu16_intc 0xffffffff &cpu16_intc 9 + &cpu17_intc 0xffffffff &cpu17_intc 9 + &cpu18_intc 0xffffffff &cpu18_intc 9 + &cpu19_intc 0xffffffff &cpu19_intc 9 + &cpu20_intc 0xffffffff &cpu20_intc 9 + &cpu21_intc 0xffffffff &cpu21_intc 9 + &cpu22_intc 0xffffffff &cpu22_intc 9 + &cpu23_intc 0xffffffff &cpu23_intc 9 + &cpu24_intc 0xffffffff &cpu24_intc 9 + &cpu25_intc 0xffffffff &cpu25_intc 9 + &cpu26_intc 0xffffffff &cpu26_intc 9 + &cpu27_intc 0xffffffff &cpu27_intc 9 + &cpu28_intc 0xffffffff &cpu28_intc 9 + &cpu29_intc 0xffffffff &cpu29_intc 9 + &cpu30_intc 0xffffffff &cpu30_intc 9 + &cpu31_intc 0xffffffff &cpu31_intc 9 + &cpu32_intc 0xffffffff &cpu32_intc 9 + &cpu33_intc 0xffffffff &cpu33_intc 9 + &cpu34_intc 0xffffffff &cpu34_intc 9 + &cpu35_intc 0xffffffff &cpu35_intc 9 + &cpu36_intc 0xffffffff &cpu36_intc 9 + &cpu37_intc 0xffffffff &cpu37_intc 9 + &cpu38_intc 0xffffffff &cpu38_intc 9 + &cpu39_intc 0xffffffff &cpu39_intc 9 + &cpu40_intc 0xffffffff &cpu40_intc 9 + &cpu41_intc 0xffffffff &cpu41_intc 9 + &cpu42_intc 0xffffffff &cpu42_intc 9 + &cpu43_intc 0xffffffff &cpu43_intc 9 + &cpu44_intc 0xffffffff &cpu44_intc 9 + &cpu45_intc 0xffffffff &cpu45_intc 9 + &cpu46_intc 0xffffffff &cpu46_intc 9 + &cpu47_intc 0xffffffff &cpu47_intc 9 + &cpu48_intc 0xffffffff &cpu48_intc 9 + &cpu49_intc 0xffffffff &cpu49_intc 9 + &cpu50_intc 0xffffffff &cpu50_intc 9 + &cpu51_intc 0xffffffff &cpu51_intc 9 + &cpu52_intc 0xffffffff &cpu52_intc 9 + &cpu53_intc 0xffffffff &cpu53_intc 9 + &cpu54_intc 0xffffffff &cpu54_intc 9 + &cpu55_intc 0xffffffff &cpu55_intc 9 + &cpu56_intc 0xffffffff &cpu56_intc 9 + &cpu57_intc 0xffffffff &cpu57_intc 9 + &cpu58_intc 0xffffffff &cpu58_intc 9 + &cpu59_intc 0xffffffff &cpu59_intc 9 + &cpu60_intc 0xffffffff &cpu60_intc 9 + &cpu61_intc 0xffffffff &cpu61_intc 9 + &cpu62_intc 0xffffffff &cpu62_intc 9 + &cpu63_intc 0xffffffff &cpu63_intc 9 + >; + riscv,ndev = <224>; + }; + + uart0: serial@7040000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <500000000>; + reg-shift = <2>; + reg-io-width = <4>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + chosen: chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0"; + }; +}; From patchwork Fri Sep 15 07:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140387 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp992038vqi; Fri, 15 Sep 2023 05:06:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE8yB9umUKtQoghxJxh44jIM2xqWX+lFrm3wmW1M74Tf/izlwPwKIG8g3Ut+064Dol0JA2a X-Received: by 2002:a05:6a00:2da2:b0:68f:c9e0:1a68 with SMTP id fb34-20020a056a002da200b0068fc9e01a68mr1527343pfb.3.1694779612629; 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[23.128.96.38]) by mx.google.com with ESMTPS id l62-20020a633e41000000b0055fdd303745si3247019pga.421.2023.09.15.05.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 05:06:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=V3MY1Ywp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id B0622839233B; Fri, 15 Sep 2023 00:25:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232784AbjIOHZH (ORCPT + 33 others); Fri, 15 Sep 2023 03:25:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232782AbjIOHZG (ORCPT ); Fri, 15 Sep 2023 03:25:06 -0400 Received: from mail-oo1-xc29.google.com (mail-oo1-xc29.google.com [IPv6:2607:f8b0:4864:20::c29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AB8BA1; Fri, 15 Sep 2023 00:25:01 -0700 (PDT) Received: by mail-oo1-xc29.google.com with SMTP id 006d021491bc7-57358a689d2so1089353eaf.2; Fri, 15 Sep 2023 00:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1694762700; x=1695367500; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=iVUDT6l1ChAeIi0RC+WcBnGHyj8AAnCtHrqteS2EV7o=; b=V3MY1Ywpcabxzlg0aq6AwBESyDQjCHYHlzKYqG3IsobzCfFCGZpQtecpFH5VBo3psK ak3Fb1MVuDrnledXuFEk1oqAwKJeV4ak+o63gFpDdfanmTKOgdFLTgZF7dKMGSdWNbVe teDJHJO83/FBvTBxc8mevc+VBuRXCE2/S05k25GmTRi3VHe8PY4xrfANriLzd7vlQjqx a/kw6iZUfgf8UsvO6pnEUno+EVKPZc0G2rbDaRXHrYUN88eKA2QtoW7a/ndaUcyAPiZ3 klR6wclQLxeVtopM045djYGnfTgz+NsVVOjO+7ZHze9rG06EqpUsHSauQnVXtotxMNXF pUhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694762700; x=1695367500; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iVUDT6l1ChAeIi0RC+WcBnGHyj8AAnCtHrqteS2EV7o=; b=BJMwAUKA+bguTPWOZGLkNLJ52LlRnRPPUfX/EGbuKHvvGOLga5iwfFT9VFLTlLnSlB KLEvL22ZOuXFrx16u2dcfnE3aeNf3E0D4inLpBnFT6SNl64T13O3KwtUWBbT5jtS8KvA BeCDJBi3NOGIzLzcy/GSGPDhPX1LS6xOjwO9kB0Zs5g7Mgqvq3SPoyebe+nqdVsFG8vU nA1Md8+GXf4fr6eehBF0bbhJnAzuV3AsqMpMfqGLvtPySIz9QKhoQKACyFA+J0F7BeVb OaupfHfU5/1NCsf++1wP4sPeP+LlpDB+H0Bebu+MU1C9aVMVtNrkPmLHtmEHXceYnWCi dncw== X-Gm-Message-State: AOJu0YxMMXpxJk15E6twLTynUgsYgRdHBGCCDYzcEhLp1eJeLnPdW/mB kZ+WjCoi7Xlf61X4r0wd4nuO3pKM3NJN3A== X-Received: by 2002:a05:6870:5803:b0:1b3:8cfb:78c5 with SMTP id r3-20020a056870580300b001b38cfb78c5mr1029357oap.34.1694762700635; Fri, 15 Sep 2023 00:25:00 -0700 (PDT) Received: from localhost.localdomain ([222.95.63.58]) by smtp.gmail.com with ESMTPSA id c10-20020a63a40a000000b0056b6d1ac949sm2131946pgf.13.2023.09.15.00.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 00:25:00 -0700 (PDT) From: Wang Chen X-Google-Original-From: Wang Chen To: linux-riscv@lists.infradead.org, conor@kernel.org, aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Wang Chen , Inochi Amaoto Subject: [PATCH 08/12] riscv: dts: sophgo: add Milk-V Pioneer board device tree Date: Fri, 15 Sep 2023 15:24:51 +0800 Message-Id: <20230915072451.118209-1-wangchen20@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 15 Sep 2023 00:25:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777089146284362664 X-GMAIL-MSGID: 1777105226894667392 Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 in a standard mATX form factor. It is a good choice for RISC-V developers and hardware pioneers to experience the cutting edge technology of RISC-V. Currently only support booting into console with only uart enabled, other features will be added soon later. [1]: https://milkv.io/pioneer Signed-off-by: Xiaoguang Xing Signed-off-by: Inochi Amaoto Signed-off-by: Wang Chen --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 +++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f60a280abb15..94788486f13e 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -6,5 +6,6 @@ subdir-y += renesas subdir-y += sifive subdir-y += starfive subdir-y += thead +subdir-y += sophgo obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile new file mode 100644 index 000000000000..5a471b19df22 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb + diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts new file mode 100644 index 000000000000..4f480ff88fbd --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +/ { + model = "Milk-V Pioneer"; + compatible = "milkv,pioneer", "sophgo,sg2042"; + + info { + file-name = "sg2042-milkv-pioneer.dts"; + }; +}; + From patchwork Fri Sep 15 07:25:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140362 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp957773vqi; Fri, 15 Sep 2023 04:04:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8puyq9gLtDwO/sXSTNwUPvmgwHXCAdkPMYYX3MDEwF35P3j+NbcX1+r0Y2Q7jDu1J0M55 X-Received: by 2002:a05:6a00:170d:b0:68c:69ca:2786 with SMTP id h13-20020a056a00170d00b0068c69ca2786mr1378341pfc.34.1694775866494; Fri, 15 Sep 2023 04:04:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694775866; cv=none; d=google.com; s=arc-20160816; b=IsCcFgA+MYKKgBVDJ5PeplVjbnWNSpS8ODkJh6VK+R9I+iGcqn2dPy5CjrevbyRZVT hoSXwSVNWxjSkdhjgwqA+gEYPosvOm3Myciu/cdJTZ2/G7Y36wEGxLbv7JjDBEazJKnF amCs+OKdKs/1JUFfR4xcqME5Ig4adMLPKt83t4NCMJeb6y+fwRV7vCj4vdH7w81vlr8q BNVaBwBhARvNOwv7fWdclzfDx1/5mstNCcD0EAAEYlkXqy9MvOxLVH1o84LjdV2Hk1gx PjF0If/SncEdDhcFfttPx5hFbKZd7bUYp4HU8peqb4dSjfVvrT72KJiWN0/5So+6+ukG ufiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=vtiQk2mCxeEr3VVOeU3ze8J3wl3kSWve+xDO77CYJdQ=; fh=qcStU/cXmyi6QQmh2OH0Y187/PpiTFL4etZ28pI2hrA=; b=pajayLdxrDdXOxSsMDvUBZWnhQq4V+arLe8W3lcI//rbuCFH6/OtvaWK+jcCgYT50Z Z5RSXlErRuwZuvKIG73VX+EJDOswrBPK9n9hxBQ81bKYFTxKy5jP3X/IVVpnM3JVS39/ IhJsRm/7aiZpLzGTYrRVtq650nh81MKRA6zbYbPdlhoWuTuqlxyGPET64ZoTYijXe5Th I+jAAWq2CKKr194bzG4Ckbu1SqTWFJbIcBrzJf4HyXvKA5U4gXSGbfI9UwfxB1mseAlS JMLR5C5lGjdcGO33BAasptZF75U7GvBLEfYYQNCk27GbDKVcv8U0zaITaX5C8IYTUcLK JOYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=hbcZoBcw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from pete.vger.email (pete.vger.email. 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Signed-off-by: Emil Renner Berthing --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 17c553123f96..6c23562f1b1e 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -48,6 +48,9 @@ properties: - starfive,jh7100-hsuart - starfive,jh7100-uart - const: snps,dw-apb-uart + - items: + - const: sophgo,sg2042-uart + - const: snps,dw-apb-uart - const: snps,dw-apb-uart reg: From patchwork Fri Sep 15 07:25:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140395 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1003532vqi; Fri, 15 Sep 2023 05:24:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/pcxu1JIdipIAkCMiDUNLNzE/N6qMFbuWXYDJ2snAHosfudzEtuGa5ePrMsvodBPllXTY X-Received: by 2002:a05:6a21:7988:b0:14d:5580:8ff0 with SMTP id bh8-20020a056a21798800b0014d55808ff0mr1389278pzc.25.1694780683169; Fri, 15 Sep 2023 05:24:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694780683; cv=none; d=google.com; s=arc-20160816; b=EDuwYQblBkyswi2buvI5mYIj8+iigu2RqNk4W9Lktiuqny8DCysOnzfWIJQoASG6G5 YYiLW+3A5BgVZGh32AlZxyLs2+GCrZ7bfVuhjfMDOhtFdWwXw5CCWp504K6DlblgWwZZ TlCX+nIM83m9e0G5m+GhGt39qLJC8xhoiaDs5TcVuG8uKSjMB7A29JOjPU09PAkA+kp2 RmyQRTIxxaw7DTG/u/t/p6Gs8UGoGaZAdE3gCPJhFE3JvxKty7/VSHQJMQue4EZjFOdJ OHFjYSZ19ubq2jFDcU1TZ4h4oVey09kt+z7+7ZJU+n7zPoh9MOCyyBhzsudYkl+KQbNR uvFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=L2LlgryffFXqAnsB0AaplLotGa39fDQAXZM7QJ4rjkg=; fh=qcStU/cXmyi6QQmh2OH0Y187/PpiTFL4etZ28pI2hrA=; b=sesw9VTSDsp5j1hrhM2ZFwIh9ET4LAeLF3kwd8b2J/vF67//NxpJ+eaQzsA+MibA6K 17mCntjceHArVR+yvNIbSM3EtxMITyLmM1UVeLdKpTPl69ySuVqau88Pg1Di37s3BD85 vdsuoB6avjAmFur0dgVZm5R5nyKuRUm1DyzDGigIeZdZnAprcgwvgvc1P8fTEGVlq5kj tHJ/+FyM+NTaEihSZkZUr7r3mZRkdRshxtCPIF7mrzcQTPvBbEYLR15hwnl512fybZpm JspXMhLWKYXKf0JIvWpDtU4RK4e0GyWsPlxuDGMjWVMJ0zHIvXRCgI7lUFUH/nFcq2cR bkbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=Snl9Y5XH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from lipwig.vger.email (lipwig.vger.email. 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Signed-off-by: Emil Renner Berthing --- drivers/tty/serial/8250/8250_dw.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index f4cafca1a7da..6c344877a07f 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { .quirks = DW_UART_QUIRK_IS_DMA_FC, }; -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { +static const struct dw8250_platform_data dw8250_skip_set_rate_data = { .usr_reg = DW_UART_USR, .quirks = DW_UART_QUIRK_SKIP_SET_RATE, }; @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = { { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, - { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data }, + { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); From patchwork Fri Sep 15 07:26:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140663 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1297962vqi; Fri, 15 Sep 2023 13:19:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEa/52AsDfgBR5ds5KNJ81YprO34zSO7dGh0/+TJ89TTDiEy7QE7IFfjAQ9Ct83dqz70k0m X-Received: by 2002:a17:903:4294:b0:1c0:e6e1:4a11 with SMTP id ju20-20020a170903429400b001c0e6e14a11mr2187217plb.54.1694809184953; Fri, 15 Sep 2023 13:19:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694809184; cv=none; d=google.com; s=arc-20160816; b=qxPQkh0456NWEqtEc+VeTsopS1QpEkJjGyElyKgzkdNtjCMFLkhq5qjVtCML4xhBps Y6HonzC52DMcA/Qs402Zu0IPM6nDm1fleEoTKPMmtjusMG8PyZaKLniCPnvFL2DDinHc w6XAwlkhapjweg/ZKI6hawJV7Oc3+HiJT7G18j6aKpm7P4/JGziRREHG6uA3xKtkzRW+ PgFPNGfzBSNsiMg9Ur0n5UtM49hdv0puzhKbwSmOykO3wlpI5/oD1Z6vWfCKqGS5Ln/a ak1nFgYgt3Czfja+DZZEp54ju/aFsnpSrZkOEG/0Y/A4wy17WDudMd4omI60aUH5kmpV LK2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=lmxSozsjyQbgMnJPbBrqJiUPwUPx63V+RTOPBnTrVeI=; fh=G+Hk69Cko/wBMBNk1ZzOaKUhBGncJb8wFzIneYTxev4=; b=EkMk0OXfMK4S94WujH24EhTLT80Fpo3+tKx8O7ey56x6Tu5OOvUYeOK9lgfX/wT92L 6OLpMxQ9/9bLjHFTfZ+HuBSfYRzChx923U7VyC34Pl8dDK8/pVcipTd/3aWCTwoK9hVh Kkb86u++v0edj/jaHi3JrsQkhI2P+Gl8tyPjX0zNNEqSZ+x4tAYRIg1EppnFKiVeHcUX yKLL/2zZPh7cLz45MAf4YG3KfebCor7u9V5pIDlOcEMKKVAHXWkzTw52e+XQ0f+lcd/j TblKAMLr3trq/C1g8hF8GXzcE5h/AfC213/EaLMiOEE/iZ+oxP87AukFjiQLOCJRkrrV brFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=mPo6iw9t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. 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Signed-off-by: Emil Renner Berthing Signed-off-by: Wang Chen --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 5c4b82f13207..87f7667bbe63 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -492,7 +492,7 @@ &cpu63_intc 0xffffffff &cpu63_intc 9 }; uart0: serial@7040000000 { - compatible = "snps,dw-apb-uart"; + compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; interrupt-parent = <&intc>; interrupts = ; From patchwork Fri Sep 15 07:26:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Wang X-Patchwork-Id: 140591 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1223536vqi; Fri, 15 Sep 2023 10:56:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkPIF1XJNPrSEa6+SyoG1TjTeLZNbAL6JFSKHI32cauIYXUwnkRy8GqYvSYm++BDG2r1cs X-Received: by 2002:a17:902:d485:b0:1c3:9764:764f with SMTP id c5-20020a170902d48500b001c39764764fmr2540017plg.48.1694800582791; Fri, 15 Sep 2023 10:56:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694800582; cv=none; d=google.com; s=arc-20160816; b=QfWYs/4+xcWHdScZXQGEvTA7+J8zpSvdrFoqz8408f9nBDpIpzVEMSAqTyFVPE1EcY D3uDyfAOpeqQT3HuOB2MyavihVWsZ3UqmKkh5TKOuPZTNCUihckudE+jKeMz0IyQySye XSHEBH1TWr5Lg4w6sZyfqKDXE++ZVGMi+tTDhJdW1z9XkhgqLIgxBihkrhYEF3lNxZxn nG9DNE2IqovCJRMpVbRPk16S6V4UExqrxYd6fEq4YwN687FiIE3cGvByYJi/92ZU0Yqz DDkvk/ycYTdxSx00R5phpLSBGxJw/CMtdGEq6ig3FHAQw99vTnezfcaoq3VwUzBEJrPp MYMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=JjZ5p6sECHH5hqVMsjk72FLLIZN3XyOMXABaFLbFiJ8=; fh=uX8GTfQZ4oxMzeIzkttJn/ljCrddTXNVgdIuxqRbyug=; b=KVSkAY9xTiuIHTAWwoCNa8S6DCcoG9TeQQkVFIJR7mJyPjy/Vh86bsqzegJv3lsR26 q+boB2rhH47hKpUfKJo8Gomo/fxsoNKDkPr2pa5cJSEWj5932eberiIRPaj5q+j3FzwW olndANsG7ol7GwOUTLO0MrAPWM881+o0DyN3B+PGPRiAKnkaeuCCCua/OIpDMB/HUR0/ gPIC7t0AXs/nfX0ivLYSoRZ4IW+rVcoaw6X4VIwv73DkP7U65UFlWBi1UE+M8YnwFdn2 cTEnO2OODR8yUZQQdmSVWCB8J3KBWwaJ6C1cfkVdlYNorJI3I+tsLb2+VTTpuDTorlc5 GGUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=KlA2Wq1c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. 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Signed-off-by: Wang Chen --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..bf737cfa1d2c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_SOC_VIRT=y +CONFIG_ARCH_SOPHGO=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y