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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id d3-20020a170902f14300b001b8a6bf59cfsi2603692plb.378.2023.09.14.21.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 21:04:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=w9pW4kwX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 489B481DC7BC; Thu, 14 Sep 2023 20:49:52 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231523AbjIODtt (ORCPT + 33 others); Thu, 14 Sep 2023 23:49:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230073AbjIODtr (ORCPT ); Thu, 14 Sep 2023 23:49:47 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4304A196 for ; Thu, 14 Sep 2023 20:49:43 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-26fc9e49859so1404619a91.0 for ; Thu, 14 Sep 2023 20:49:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694749782; x=1695354582; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hYrxQXlYsxlbzxTi4wO/BXPj8sXNJd30qJO9BW1+NbI=; b=w9pW4kwXoRnN24mTCa23KvD2uArcbmnnkwJJTIat4sFVVPLEZIV/0ZERLBTnDX73TN The3+O0bJUyLDiTkDVtNBBetlV4Wq3zIytFOV2U1QceS79u1NR2GbkzfgahSlGFvjcNU 5WfcH60q8TveMDa1fJz8vVwGQqhtyasICgByFp8K/Wo7yV5uvQh3Kla36zEUdWc6+sGs CCnY3ivoFtoqmwK64GazD0rsPwgmwg3P4zrGDGl4vM8Ve5z+iCC2nXvbfHLbmoKjykX5 TaSrYUK4Aj448x36gQ4HWpqeuA6a7ELouuSyomDADJUx5H3Mbkqz/vYZ7BUxt2p4Ffgx ESbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694749782; x=1695354582; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hYrxQXlYsxlbzxTi4wO/BXPj8sXNJd30qJO9BW1+NbI=; b=lzkX0BIeiiBNmoW7kAcZmXqrcXJfVTjs+WMvbItMNgciB+mfF+A0I06U1Y6rssEDCX bB0OvnsUN5tDc4UijeGMXuCWM/mGWKBSzE8R71+TyqUk1msHNynd/WsOCwEcPkfksfFy ZlabSwCybAHiqh2D8vajPNfwH0i2DGtg9pCeMxiB2Z1qj+H3eIZQILTSF+t8KBpyGR/A N5+7CwDcejfBJzhHCTq8ha6npkoumTm45YvjSlCfDMq7+qHYWECeTh/MEAWvXltDMIuC AMTKTtIQi6wPs91xDVNMWJ8TZtMHFpczD1HCuPuhIEQdVcmVvAZPjenfYOYBxVwQEH0y No6A== X-Gm-Message-State: AOJu0YwmafJR2S+cs17t7L7gBPCixwlfLbLLbWTAtViulnnEY6Kedkd3 OAY6eJhq8scXQHLOckD70nUZpvIar8nGCjb04xg= X-Received: by 2002:a17:90a:c245:b0:268:3f6d:9751 with SMTP id d5-20020a17090ac24500b002683f6d9751mr416214pjx.23.1694749782539; Thu, 14 Sep 2023 20:49:42 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id g5-20020a17090adac500b002739282db53sm3881409pjx.32.2023.09.14.20.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 20:49:42 -0700 (PDT) From: Charlie Jenkins Date: Thu, 14 Sep 2023 20:49:37 -0700 Subject: [PATCH v5 1/4] asm-generic: Improve csum_fold MIME-Version: 1.0 Message-Id: <20230914-optimize_checksum-v5-1-c95b82a2757e@rivosinc.com> References: <20230914-optimize_checksum-v5-0-c95b82a2757e@rivosinc.com> In-Reply-To: <20230914-optimize_checksum-v5-0-c95b82a2757e@rivosinc.com> To: Charlie Jenkins , Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Albert Ou X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 14 Sep 2023 20:49:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777074853009020023 X-GMAIL-MSGID: 1777074853009020023 This csum_fold implementation introduced into arch/arc by Vineet Gupta is better than the default implementation on at least arc, x86, arm, and riscv. Using GCC trunk and compiling non-inlined version, this implementation has 41.6667%, 25%, 16.6667% fewer instructions on riscv64, x86-64, and arm64 respectively with -O3 optimization. Signed-off-by: Charlie Jenkins Reviewed-by: David Laight --- include/asm-generic/checksum.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/include/asm-generic/checksum.h b/include/asm-generic/checksum.h index 43e18db89c14..adab9ac4312c 100644 --- a/include/asm-generic/checksum.h +++ b/include/asm-generic/checksum.h @@ -30,10 +30,7 @@ extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); */ static inline __sum16 csum_fold(__wsum csum) { - u32 sum = (__force u32)csum; - sum = (sum & 0xffff) + (sum >> 16); - sum = (sum & 0xffff) + (sum >> 16); - return (__force __sum16)~sum; + return (__force __sum16)((~csum - ror32(csum, 16)) >> 16); } #endif From patchwork Fri Sep 15 03:49:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 140352 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp949721vqi; Fri, 15 Sep 2023 03:47:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHBh8hVPYz0Bs0FTgmKKUSgq47f6PT1bXfTesW+1Bl0LY9JfFEziRlpGXTRoESNP/1lSRPG X-Received: by 2002:a9d:6acd:0:b0:6b9:ba85:a5fa with SMTP id m13-20020a9d6acd000000b006b9ba85a5famr1309278otq.5.1694774854983; Fri, 15 Sep 2023 03:47:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694774854; cv=none; d=google.com; s=arc-20160816; b=EbyY43dN8L4kIwT/fRgjKmxusKHHWOUn8xF6ukXBMS1SGKdsxfxwQUQSdAzQbAoYR4 pRg+xOmbsL7QotEgVKJ9b/YOs1ajb2XoQ5S3tFd4oAHmthhuh/UKTaoJ9qojkf3y7m9d SNk3d8ELdrVEZ/Frkn9EPbPEMcmNKCxIfN47hgK7EE2lumtmT0KEco/5UEMI34LPP6l2 XTKd5rAzF4kDknfxK8qYySdBvFmdi6/YPOuc8dZPZ15U8j5DEuuRbJ5kwvoxkG6MXW33 mq1u4tIfjM217uODxtpEWyPFV44G4hkGFuSZVHOia0C9HivtSnwBaeE8QHCRBx+1LJ8U Pkzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=loF04Ge9lKLb+XrqXIoFKE9WVQmjWi5jnw1M425dhYA=; fh=gOzr2J2/AaC/1DdOEiJ/vMVIpQG7VS7WGUZu6JUmCr4=; b=Ce+ReMrMSWoRPChgi2QwONvGmA66n/8Y2F4JXHYpeO3zTF7d89eBLJn2hEdU1Qx126 FJIHI5w7BCvJMnymDCtbSsa4zdSWuNCb+NDx0cTpNlVz5AtL2q94HaT2ImirS4oUHqI9 6uoSl8Dwg5tZ1E79orH8WsicHXekar5b6Wuxl4xNrIDjdeCBmBZZt4vAbFLny8CQKrRS 6hnUz2KYGPPmXhnaSw1nJwgCxqeZvFDNNUcroMKfJs1V7XGunbaoMiGwqcQ8DzwG6mqA 2jiVTJ9YGgLkrW39ssBPgddACxGbY2k4ROAD5lgEYR2mY++Et3p8zOxa1Zc07z/KJH7S YCwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=KgYPGLwE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. 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In 64-bit, can take advantage of the larger register to avoid some overflow checking. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/checksum.h | 79 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h new file mode 100644 index 000000000000..2f0f224682bd --- /dev/null +++ b/arch/riscv/include/asm/checksum.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * IP checksum routines + * + * Copyright (C) 2023 Rivos Inc. + */ +#ifndef __ASM_RISCV_CHECKSUM_H +#define __ASM_RISCV_CHECKSUM_H + +#include +#include + +#define ip_fast_csum ip_fast_csum + +#include + +/* + * Quickly compute an IP checksum with the assumption that IPv4 headers will + * always be in multiples of 32-bits, and have an ihl of at least 5. + * @ihl is the number of 32 bit segments and must be greater than or equal to 5. + * @iph is assumed to be word aligned. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned long csum = 0; + int pos = 0; + + do { + csum += ((const unsigned int *)iph)[pos]; + if (IS_ENABLED(CONFIG_32BIT)) + csum += csum < ((const unsigned int *)iph)[pos]; + } while (++pos < ihl); + + /* + * ZBB only saves three instructions on 32-bit and five on 64-bit so not + * worth checking if supported without Alternatives. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + + if (IS_ENABLED(CONFIG_32BIT)) { + asm(".option push \n\ + .option arch,+zbb \n\ + not %[fold_temp], %[csum] \n\ + rori %[csum], %[csum], 16 \n\ + sub %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } else { + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + not %[fold_temp], %[csum] \n\ + roriw %[csum], %[csum], 16 \n\ + subw %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } + return csum >> 16; + } +no_zbb: +#ifndef CONFIG_32BIT + csum += (csum >> 32) | (csum << 32); + csum >>= 32; +#endif + return csum_fold((__force __wsum)csum); +} + +#endif // __ASM_RISCV_CHECKSUM_H From patchwork Fri Sep 15 03:49:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 140868 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp1431707vqi; Fri, 15 Sep 2023 19:02:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG6io0QdK3AjsocerYEU5DHO8upDPendE6S60cC8Amq+5chgyHq6poYTpoZOGI6+nswPUjY X-Received: by 2002:a05:6a21:191:b0:151:35ad:f331 with SMTP id le17-20020a056a21019100b0015135adf331mr4562553pzb.14.1694829732516; Fri, 15 Sep 2023 19:02:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694829732; cv=none; d=google.com; s=arc-20160816; b=xGzskTRCX4bWrIfP7LkHi+Ho+4Fo+c5YodRLkOJdVEvARyUStGDkDeM6459K+zFN1K 6sW4lsQ/UvSvXHqsUKC5p/PcwSeQagI7+HmtuxIqf+kvWPgYaXhCJU+pWHqpkHKKD0+F M7gklWeRkCnxcsPMukKO3uYDmlbCnWjpCl96XAg+D1Kd9BA+oU+xbSFwr3Jym7eg5ozz Rgrv9x9QJgJD5jfgea6xE5cI2e1S7ymQghuF2LVYhi+0GJRIB9YVEJHrgJz9jJwZcJ0z 3Q70tA/2PdO6F8chQEHNL/OstGK5mzPX3IE36Ga4zSxSWtZgUvG8neUJxPGv8PD7LWju h4tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=CyaSMvzVf/GL9jUMPj8Pe5Mgy8bVy6kL5NApChG9qVE=; fh=gOzr2J2/AaC/1DdOEiJ/vMVIpQG7VS7WGUZu6JUmCr4=; b=sCoohNXJU5AYU2oha/Aa2TThHFjiQ56/Gju/f/jOIlHN1i1j3lHz1xbAmESDyG4lgy MBIrQ0NowMRKwNeoAz5rIg3XrGonRVg0Qgl/39m1E+Lxeri3tR6UX9Ze76gZmP+dgyhH cKI7Coc3g7yBpKGIxI7VHVyft7/PbJnTpsP5SpL2QYJn5l/QSX2wpW68Er2rWmub2ltE eCtOs7K3TD7lTDLp/4DEn+9KUr0IZWbg8RFZQOXKwKBKc1wSLKyciFdhnGTfbRuMU1/7 jduwLCLoOpaUSy59vgjlIlVIDi6A3hXPR8o38r4fY+oHOeFi0/clBwzhbJSjgC9hPtDz J38w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b="1ZC0/CG4"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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When compiled for 32-bit will load from the buffer in groups of 32 bits, and when compiled for 64-bit will load in groups of 64 bits. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/checksum.h | 12 +++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/csum.c | 198 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h index 2f0f224682bd..52e7926ff3ce 100644 --- a/arch/riscv/include/asm/checksum.h +++ b/arch/riscv/include/asm/checksum.h @@ -12,6 +12,18 @@ #define ip_fast_csum ip_fast_csum +extern unsigned int do_csum(const unsigned char *buff, int len); +#define do_csum do_csum + +/* Default version is sufficient for 32 bit */ +#ifdef CONFIG_64BIT +#define _HAVE_ARCH_IPV6_CSUM +__sum16 csum_ipv6_magic(const struct in6_addr *saddr, + const struct in6_addr *daddr, + __u32 len, __u8 proto, __wsum sum); +#endif + +// Define riscv versions of functions before importing asm-generic/checksum.h #include /* diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 26cb2502ecf8..2aa1a4ad361f 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -6,6 +6,7 @@ lib-y += memmove.o lib-y += strcmp.o lib-y += strlen.o lib-y += strncmp.o +lib-y += csum.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c new file mode 100644 index 000000000000..06e1d16b29ca --- /dev/null +++ b/arch/riscv/lib/csum.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IP checksum library + * + * Influenced by arch/arm64/lib/csum.c + * Copyright (C) 2023 Rivos Inc. + */ +#include +#include +#include +#include + +#include + +/* Default version is sufficient for 32 bit */ +#ifndef CONFIG_32BIT +__sum16 csum_ipv6_magic(const struct in6_addr *saddr, + const struct in6_addr *daddr, + __u32 len, __u8 proto, __wsum csum) +{ + unsigned int ulen, uproto; + unsigned long sum = csum; + + sum += saddr->s6_addr32[0]; + sum += saddr->s6_addr32[1]; + sum += saddr->s6_addr32[2]; + sum += saddr->s6_addr32[3]; + + sum += daddr->s6_addr32[0]; + sum += daddr->s6_addr32[1]; + sum += daddr->s6_addr32[2]; + sum += daddr->s6_addr32[3]; + + ulen = htonl((unsigned int)len); + sum += ulen; + + uproto = htonl(proto); + sum += uproto; + + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + /* + * Zbb is likely available when the kernel is compiled with Zbb + * support, so nop when Zbb is available and jump when Zbb is + * not available. + */ + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[sum], 32 \n\ + add %[sum], %[fold_temp], %[sum] \n\ + srli %[sum], %[sum], 32 \n\ + not %[fold_temp], %[sum] \n\ + roriw %[sum], %[sum], 16 \n\ + subw %[sum], %[fold_temp], %[sum] \n\ + .option pop" + : [sum] "+r" (sum), [fold_temp] "=&r" (fold_temp)); + return (__force __sum16)(sum >> 16); + } +no_zbb: + sum += (sum >> 32) | (sum << 32); + sum >>= 32; + return csum_fold((__force __wsum)sum); +} +EXPORT_SYMBOL(csum_ipv6_magic); +#endif // !CONFIG_32BIT + +#ifdef CONFIG_32BIT +#define OFFSET_MASK 3 +#elif CONFIG_64BIT +#define OFFSET_MASK 7 +#endif + +/* + * Perform a checksum on an arbitrary memory address. + * Algorithm accounts for buff being misaligned. + * If buff is not aligned, will over-read bytes but not use the bytes that it + * shouldn't. The same thing will occur on the tail-end of the read. + */ +unsigned int __no_sanitize_address do_csum(const unsigned char *buff, int len) +{ + unsigned int offset, shift; + unsigned long csum = 0, data; + const unsigned long *ptr; + + if (unlikely(len <= 0)) + return 0; + /* + * To align the address, grab the whole first byte in buff. + * Since it is inside of a same byte, it will never cross pages or cache + * lines. + * Directly call KASAN with the alignment we will be using. + */ + offset = (unsigned long)buff & OFFSET_MASK; + kasan_check_read(buff, len); + ptr = (const unsigned long *)(buff - offset); + len = len + offset - sizeof(unsigned long); + + /* + * Clear the most signifant bits that were over-read if buff was not + * aligned. + */ + shift = offset * 8; + data = *ptr; + if (IS_ENABLED(__LITTLE_ENDIAN)) + data = (data >> shift) << shift; + else + data = (data << shift) >> shift; + + /* + * Do 32-bit reads on RV32 and 64-bit reads otherwise. This should be + * faster than doing 32-bit reads on architectures that support larger + * reads. + */ + while (len > 0) { + csum += data; + csum += csum < data; + len -= sizeof(unsigned long); + ptr += 1; + data = *ptr; + } + + /* + * Perform alignment (and over-read) bytes on the tail if any bytes + * leftover. + */ + shift = len * -8; + if (IS_ENABLED(__LITTLE_ENDIAN)) + data = (data << shift) >> shift; + else + data = (data >> shift) << shift; + + csum += data; + csum += csum < data; + + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + unsigned int fold_temp; + + if (IS_ENABLED(CONFIG_32BIT)) { + asm_volatile_goto(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 16 \n\ + andi %[offset], %[offset], 1 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + beq %[offset], zero, %l[end] \n\ + rev8 %[csum], %[csum] \n\ + zext.h %[csum], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), + [fold_temp] "=&r" (fold_temp) + : [offset] "r" (offset) + : + : end); + + return csum; + } else { + asm_volatile_goto(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + roriw %[fold_temp], %[csum], 16 \n\ + addw %[csum], %[fold_temp], %[csum] \n\ + andi %[offset], %[offset], 1 \n\ + beq %[offset], zero, %l[end] \n\ + rev8 %[csum], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + zext.h %[csum], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), + [fold_temp] "=&r" (fold_temp) + : [offset] "r" (offset) + : + : end); + + return csum; + } +end: + return csum >> 16; + } + +#ifndef CONFIG_32BIT + csum += (csum >> 32) | (csum << 32); + csum >>= 32; +#endif + csum = (unsigned int)csum + (((unsigned int)csum >> 16) | ((unsigned int)csum << 16)); + if (offset & 1) + return (unsigned short)swab32(csum); + return csum >> 16; +}