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Wed, 13 Sep 2023 16:50:08 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v16 1/6] dt-bindings: arm: add AMD Pensando boards Date: Wed, 13 Sep 2023 14:49:39 -0700 Message-ID: <20230913214944.59804-2-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913214944.59804-1-blarson@amd.com> References: <20230913214944.59804-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|SN7PR12MB8433:EE_ X-MS-Office365-Filtering-Correlation-Id: a6e1c103-9d99-4e4c-0599-08dbb4a3682d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EJWZ7YXOsAcebwag4dmhiaE+9NcJaYR3icI+cQ4jAmZ/no5XUSZqvZp9m8J5WliwQI3EbABPOor4JXr/rUAy61r7jWRI0W3QT3tuw0HglWCVuqSdzlrYjpnWkaR/WJH41NRZA9qxgyjxKUmr6oFULm0V7tMKacJHbiuiK2oDR7VwzFKkfWTtbvx2o2ro3a9SlszlefoAXNTvyT4a5vV9EDaoAcQtUtBJh3DBgWxsUetlxSX8x2nBSgkABa7NFWooH0hSS8Tqbz2VK8vtKZT8xTUpxLxqJ6e+tSYChMfbt8nYVhwi1x/ky/SCBP2QybOGa5uojcQkueuXGBgLTcrczzEM98rh6gx9JPxSOjJqf/UViu39nw44U2s3zposGbb3ED9dBu+B12+YifbqY1xupFj2hj8eqPCsmzn3HVR5AGfzIBe6TBk0Oqy01GaizWFd1YXQrVd9QwiTutdR2cZ9qhO19MxzVrjovRwYA3vEHQj5GmzonDrBFEN+qYEV51z87cM15QiJCNmkzmuWKXMBqZourWHd2amRIns4BCTEp5rdDoZOiH5ACQ+q2NI3Htmh1mAGO72n1yXjM7qRGDsStAj5lGdMb88c/A0QcW/8RTi/uuWWSpgur0+yEB6i6FSTh0ezSrOmiu5GvGdfK0q6P3tqP5UOv74Pxqjoni3J2BYrAOwCUseZbGaDUhTHoG/g7hK/cMrydtDl7o/2Bzhsk/nbFCki4blU6caxRzj9XMQxUWjlIMtq7RM6lE7FZ3c36Fky9/tlH7dPBp+LF3VnSH/rSwevHLMCK0EwEEosVlI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(136003)(376002)(346002)(186009)(451199024)(1800799009)(82310400011)(36840700001)(40470700004)(46966006)(40460700003)(6666004)(81166007)(82740400003)(356005)(47076005)(36860700001)(36756003)(426003)(2616005)(336012)(1076003)(40480700001)(26005)(316002)(2906002)(8676002)(7406005)(7416002)(4326008)(8936002)(70586007)(6916009)(70206006)(41300700001)(16526019)(966005)(478600001)(54906003)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 21:50:12.2725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6e1c103-9d99-4e4c-0599-08dbb4a3682d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8433 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 13 Sep 2023 14:50:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777022398894345739 X-GMAIL-MSGID: 1777022398894345739 Document the compatible for AMD Pensando Elba SoC boards. Signed-off-by: Brad Larson Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... 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Wed, 13 Sep 2023 16:50:19 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v16 2/6] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Date: Wed, 13 Sep 2023 14:49:40 -0700 Message-ID: <20230913214944.59804-3-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913214944.59804-1-blarson@amd.com> References: <20230913214944.59804-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|PH7PR12MB5997:EE_ X-MS-Office365-Filtering-Correlation-Id: 326fcdd3-d01c-459a-b190-08dbb4a36eac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QvedGxVF5eoCdkctpZQjAqnlbCEjv1wYmB8O7bVBXGuDUOiai3qGlS2QaEq+gf7tU6elf0TMeLPBpIxyoMfExZFa/KamiLsD9DfTBYPllQE5Rb0dX86wBQP2xckOnaHXPkBck5piEuB3SvDHxwBaBEtl1FpFVX+1ea16stYp5uqe9jb7LfwIlAAC0v3trK/r1GshpZGPNCTvqt0NJUEVKccchzebyTK6r/BJ1IQ5k08kHuPOzRc04MGvZ/5OXFK6i+Ep+PpQNJ7V+0yr7h2vwxf7t+ob8czVAq3ykFN/0pp4ZTVlKAFFBAjU2Hr2SAZ/oqAGGei8nFLnVuG57SgaJl8SQwAVzrMxmOh1Y3L+XqVzjthaBbeaJ3V9ZNxWyBo5UhqNA8bqhP7Nzc9p81iT5MiSUC3XMMQPnDaiBVeC85SYsxFsDsw7fO7AyRZEXE3VILxnqmOKV/1X1IAl2lEgOIpSoYdx2DSyr8+g6WeVOBvBg9mcVxG4MyHb2YKRrKTtfbrmRgya2I0yFIikDhfjQWkSo4/6hF3IgXgTIW2Qe2+YK/N0p7gYsCMLpcqD194kwkW5/bKNUtJ4QdPqSj3HP/E/LCrOtksz9faxsC4ryqQ1r4JyFJ6+MET0y7XJELeWdHUDhcOdt6E3zO/8OZRJb6vV5Vql9SEkQrYWa+4G7EGhZ6GL0mpTG6QqOft9KP1OCO0e3jMyF/Dnbw6Gw9/21W7ndGIVxjwttOlBpJJIEia6ecOa92j85gBC30pmSV8q7KIv6f//JZWhu13Q7Gg2wRTXW9rIkCGqmMRfByqE0hc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(39860400002)(376002)(346002)(1800799009)(82310400011)(451199024)(186009)(36840700001)(46966006)(40470700004)(316002)(966005)(6666004)(54906003)(426003)(26005)(83380400001)(7406005)(70206006)(6916009)(16526019)(2616005)(8936002)(4326008)(70586007)(2906002)(41300700001)(5660300002)(8676002)(1076003)(7416002)(36756003)(336012)(40460700003)(478600001)(40480700001)(36860700001)(82740400003)(47076005)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 21:50:23.1756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 326fcdd3-d01c-459a-b190-08dbb4a36eac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5997 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Sep 2023 14:50:42 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776963381273670703 X-GMAIL-MSGID: 1776963381273670703 Support the AMD Pensando Elba SoC Controller which is a SPI connected device providing a miscellaneous set of essential board control/status registers. This device is present in all Pensando SoC based designs. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v14 changes: - Change GPL-2.0-only or BSD-2-Clause to GPL-2.0-only OR BSD-2-Clause v11 changes: - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename - Reference spi-peripheral-props - Delete spi-max-frequency - Remove num-cs from example v10 changes: - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v9 changes: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml new file mode 100644 index 000000000000..e96978ad1e37 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Controller + +description: + The AMD Pensando Elba SoC Controller is a SPI connected device with essential + control/status registers accessed on chip select 0. This device is present + in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + enum: + - amd,pensando-elba-ctrl + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... 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Wed, 13 Sep 2023 16:50:52 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v16 3/6] MAINTAINERS: Add entry for AMD PENSANDO Date: Wed, 13 Sep 2023 14:49:41 -0700 Message-ID: <20230913214944.59804-4-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913214944.59804-1-blarson@amd.com> References: <20230913214944.59804-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|SN7PR12MB7979:EE_ X-MS-Office365-Filtering-Correlation-Id: c3b21010-77d8-4605-dfdf-08dbb4a38209 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jEz9NwxSyUD4x188oC26IlDhFqYzIDIL/YQm+mLMQtrFXE/AndBXDsm++7sbI2mFuexu5NEk55qZMkftJIsWUQJbMH5Q4FkXWSYvElrupqK9abUJ+JhpbobiGjqZ1VNf77gadsZfr2x1tYnulStfT4SKiUR01X/UKDH/1mGIuoRK0xUc2I3a4lHMUF8Hld2hNK4OmeyjwdImkn/4DC2hfpxr4kGdUSdYgP9tE+gsO/I2rFdWieHyLOLN7gsi3CkaQY1YyZW/yeidigMkY0EYT92+nFW4heRb0wWWtnWXSMRHoJUYsicCKsSB8cKfOoAttmCDcCBuFvHxtsxZWYYn+wgamFyy+ci25+BlKMYuD35uNWIPDSGlb4rTr5DlGpz2nkxWTYppQnZZ+EB1DWVlHsnUkHh1vqlzk/NCY05x2lcUIcp1/Mgvj6GhTLKFmVYV7/nhuGvlVpWYiBPSWK3kuM5UTCsqkmxLL7LwMaFLIs5jOBOC5bxiy/hFB9nyXWYI0OcPnhJwVbJmSBjxn9i5UgO6VEK9YSngVnIxi3k0+5KLIyRMC3qGMX0NYN0a67wtL5pMCFneaxcq9P3oerEjD4+diVb3EAO4O8keB0uRBppzNwZ4XAxXXAwKTMbcqXW3PKb4VYRRmW7oJOAsGhTxBMfFhkGSGxI0tdqNcNstjaJX6kMs8CXIuD5D5OgUMLfG23EDbL/VUX4N081fYVC3/NTtCqNI9XCHSWoIMkZfWi5BocJPCDdSAEkhpLSQiL9x1DlbtgRTj+8eXgA8O0h4Zg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(376002)(346002)(136003)(1800799009)(451199024)(186009)(82310400011)(46966006)(40470700004)(36840700001)(316002)(16526019)(83380400001)(6666004)(81166007)(36860700001)(36756003)(356005)(47076005)(40480700001)(82740400003)(4744005)(336012)(426003)(8676002)(40460700003)(1076003)(2906002)(54906003)(2616005)(26005)(478600001)(4326008)(41300700001)(8936002)(5660300002)(70586007)(7406005)(70206006)(6916009)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 21:50:55.6630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3b21010-77d8-4605-dfdf-08dbb4a38209 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7979 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Sep 2023 14:51:30 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776969899024239616 X-GMAIL-MSGID: 1776969899024239616 Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2833e2da63e0..28c1e29425a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1815,6 +1815,16 @@ N: allwinner N: sun[x456789]i N: sun[25]0i +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: Documentation/devicetree/bindings/soc/amd/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/soc/amd/ +F: include/uapi/linux/amd-pensando* + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet From patchwork Wed Sep 13 21:49:42 2023 Content-Type: text/plain; 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Signed-off-by: Brad Larson --- v16 changes: - Updated the help description to be more precise --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..24335565bad5 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -244,6 +244,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Wed Sep 13 21:49:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 139424 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp184446vqi; Thu, 14 Sep 2023 01:02:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3x2LznHMG+RUXMKOE9EC4brkww3DgDCdgjqAWMFVz0AFZaHmIP7PBOelAUq+V47T0RFku X-Received: by 2002:a05:6808:8eb:b0:3a4:8a41:c69c with SMTP id d11-20020a05680808eb00b003a48a41c69cmr5051467oic.13.1694678532723; Thu, 14 Sep 2023 01:02:12 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1694678532; cv=pass; d=google.com; s=arc-20160816; b=PF+41qjrIusqEytZ6DohxCsUgz9C2OXU3jz3UtIbYccVAHNfVEnTLBPsgs/8TOmrGN i/J5wLvL/kIC/rLq7nMLeZ3X88uZ7Z3GmFxZSxEuFm/zgu1HT/aQJtzUnZmX2EkrjMhj FRCizd4SyNkR1LXv09XpwxokgMHhBNoCO8Oo/tWmFUXslF/ZVSDgAPxF9Jc1rJuu4iUE ifQXmghkw4knZjGqhtM43cMzASQjpy3bjePaZOZhoGz9kZo42uJXiQ/Vgurb9Fx/pX+P kVREj5cgobMr8juSntcoaxkXb7SKLlJSgM9uTNJOJ0qMwGlmhbmL9wbnqV6E0EcWZNUO TCmw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=tLDk1pLssWElKuc59NCXJrJskYFxWibMqY1Y62PnTJY=; fh=7hQONAe7+8cBRT6x42L8D67oCyVCsSotAOWBsv8P9o8=; b=X9Jlmimg1v6Lg/RrhFiFZtai7VUiO54tE21njbI0qpqf09KVriXJsty52arY/svRTf QX8RmvC70nRCP5edAEx7e6wvg3H2V25oROBiGSz0Q8yKHi1iBZtRrF+NeVY9UKG1VC60 3zzCkZx/XtcxP4mnwGVR3nvp6uIqAZiAhFGPWAgx0ewFG574HFlW4NKPDyd9UgPaXw7v XddsmqOgQvbsCO4M8WQnCIudvjeECqcR9H3x49hMGAM18cM/UzyvE/jo06fz6tITmbqR WqOZcfg4ogJveQSINPUwXw2gZUwZH3cHqcsj3KmHfBu0QA950UsTBOJLypTqavFbybBw AeDg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Cugy5M+J; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from morse.vger.email (morse.vger.email. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 21:51:35.8007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f435c881-9b99-4a92-69a1-08dbb4a399f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9192 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 13 Sep 2023 14:51:53 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776999237277650219 X-GMAIL-MSGID: 1776999237277650219 Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Gardner --- v15 changes: - The first cell in the cpu reg property is always zero. Change address-cells to <1> and dropped the leading zero from all cpu* reg<> - Added read-only and spare partitions to flash0 v14 changes: - Fix dtbs_check l2-cache* property issue by adding required cache-level and cache-unified properties - Observed the issue after updating dtschema from 2023.1 to 2023.4 and yamllint from 1.26.3 to 1.30.0 v11 changes: - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v9 changes: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 117 +++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++ 6 files changed, 614 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..568bcc39ce9f --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2023 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1a615788f54e --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rstc: system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..9bffdf23511f --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2023 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "rsvd"; + reg = <0x0 0x10000>; + read-only; + }; + + partition@10000 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@6e00000 { + label = "spare"; + reg = <0x6e00000 0x1200000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..674890cf2a34 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Wed Sep 13 21:49:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 140107 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp784198vqi; Thu, 14 Sep 2023 20:46:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHnpTHh6g5FmVg2sDZWIhOOPcQREBcZfdATLAO9mCMAGgKq9LKJiH+4ZaStT9vSrsYnlKvm X-Received: by 2002:a05:6a00:1996:b0:68a:69ba:6789 with SMTP id d22-20020a056a00199600b0068a69ba6789mr545931pfl.16.1694749595076; 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Wed, 13 Sep 2023 16:51:55 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v16 6/6] soc: amd: Add support for AMD Pensando SoC Controller Date: Wed, 13 Sep 2023 14:49:44 -0700 Message-ID: <20230913214944.59804-7-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913214944.59804-1-blarson@amd.com> References: <20230913214944.59804-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|BY1PR12MB8448:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fe64117-396b-451e-4f95-08dbb4a3a7ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +uozfXiCRzDMkzYcYsHzNHCNNJukc+J60v+Khn1e7HIIBybalMCS9waC10/BXz7LAttvTQE9J6UD37SfLBlnLTiqdvm0E7zOp2ZZB0cfgpPEtgHADJz0KmH6+eaizj6jyWMN+VoFvjwGDHwOeeyNBZSBFIjL7vO4rrqC0oX3O5DyNfby5+TTpnmgVMz9RtsvHFGyTuXOjw9XHTGMxhoabsWByY2nepiKtd4hvA8R/csTqGcCRZh70GqPZIjnVzwgeVxGoVAueUuaU5UMByImbOZxpT11pg1a4/aHYZCU8sgfWeJCbqcVLmDOZDSsfZPjaf8Uoy9jhQ+lMl1g8aPvV0KgEaasUPO28ULEGYiisNT5W8fga1b1FVKAn31ymruvpOS2ppfcZWYNjm75uMVEVw1o2VAf5Er2dIq0Yynw8MeCD7MTqTdWuxZ0/OQwoeYyVSsozDlFKSb2Ka4J/AZEnI8WViwEdZdWSAKp0lfhkAetFAKl1tpIEU/CxjNf4kooYMSVGgUdg+XdYZjWI1etmACxn5mYspcI88Ybd5Iz/5XOLGRIv9Mr2SZowttViTmVhEaI1WZkRJ3/JKBfOlR569D9lAd78QoxlplSeMxb1iF+JOomLnhpj4pZsxk7hvrR4AWGVvcq4ILQfkYnSW5aDH9iYrIAahX6CAu0ycHigEN8JPhQ381BJMQutFX9iSqFxtCkDusryNG1LYZXNaU5YR0vRSgclpp839ydjK90MKMFOyhFdhg9gpNLhJoELuyzNW0zo5SP1o7NpeRJEsgIcQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(396003)(376002)(136003)(1800799009)(82310400011)(186009)(451199024)(36840700001)(46966006)(40470700004)(5660300002)(70206006)(70586007)(41300700001)(54906003)(4326008)(8676002)(8936002)(316002)(6916009)(81166007)(36756003)(40460700003)(478600001)(7406005)(7416002)(16526019)(83380400001)(26005)(2616005)(426003)(1076003)(336012)(30864003)(2906002)(356005)(82740400003)(47076005)(40480700001)(36860700001)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 21:51:59.1939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fe64117-396b-451e-4f95-08dbb4a3a7ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB8448 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Sep 2023 14:52:23 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777073751035291017 X-GMAIL-MSGID: 1777073751035291017 The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson --- v15 changes: - Drop custom ioctl and use existing miscdevice interface. - Delete unused definitions in amd-pensando-ctrl.h - Makefile change to compile for ARCH_PENSANDO v14 changes: - Save 8 bytes of code size by swapping spi_device and reset_controller_dev in penctrl_device - Code simplification and clarity from review inputs - Set penctrl_spi_driver.driver.name to match compatible pensando-elba-ctrl - Remove unused include in amd-pensando-ctrl.h - Rebase to linux-next 6.4.0-rc1 class_create() API change v13 changes: - Update include list in pensando-ctrl.c - Change variable spi_dev to spi throughout - Removed unneeded variable initialization, simplification of error checks, remove extra castings, and use dev_err_probe() - Sort the includes in amd-pensando-ctrl.h - Updates to cleanup if there is an error in penctrl_spi_probe() v12 changes: - Fix gcc-12.1.0 warning v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' v10 changes: - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 311 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 26 +++ 6 files changed, 357 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d21e75d69294..1a8a42141e78 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" +source "drivers/soc/amd/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 0706a27d13be..dbd651fcbecc 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,6 +3,7 @@ # Makefile for the Linux Kernel SOC specific device drivers. # +obj-$(CONFIG_ARCH_PENSANDO) += amd/ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig new file mode 100644 index 000000000000..011d5339d14e --- /dev/null +++ b/drivers/soc/amd/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "AMD Pensando SoC drivers" + +config AMD_PENSANDO_CTRL + tristate "AMD Pensando SoC Controller" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Enables AMD Pensando SoC controller device support. This is a SPI + attached companion device in all Pensando SoC board designs which + provides essential board control/status registers and management IO + support. +endmenu diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile new file mode 100644 index 000000000000..a2de0424f68d --- /dev/null +++ b/drivers/soc/amd/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c new file mode 100644 index 000000000000..0b5a3a54d624 --- /dev/null +++ b/drivers/soc/amd/pensando-ctrl.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC Controller + * + * Userspace interface and reset driver support for SPI connected Pensando SoC + * controller device. This device is present in all Pensando SoC designs and + * contains board control/status registers and management IO support. + * + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct penctrl_device { + struct reset_controller_dev rcdev; + struct spi_device *spi; +}; + +static struct penctrl_device *penctrl; +static DEFINE_MUTEX(spi_lock); + +static long +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct penctrl_device *penctrl; + u8 tx_buf[PENCTRL_MAX_MSG_LEN]; + u8 rx_buf[PENCTRL_MAX_MSG_LEN]; + struct spi_transfer t[2] = {}; + struct penctrl_spi_xfer *msg; + struct spi_device *spi; + unsigned int num_msgs; + struct spi_message m; + u32 size; + int ret; + + /* Get a reference to the SPI device */ + penctrl = filp->private_data; + if (!penctrl) + return -ESHUTDOWN; + + spi = spi_dev_get(penctrl->spi); + if (!spi) + return -ESHUTDOWN; + + /* Verify and prepare SPI message */ + size = _IOC_SIZE(cmd); + num_msgs = size / sizeof(struct penctrl_spi_xfer); + if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) { + ret = -EINVAL; + goto out_unlock; + } + msg = memdup_user((struct penctrl_spi_xfer *)arg, size); + if (IS_ERR(msg)) { + ret = PTR_ERR(msg); + goto out_unlock; + } + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto out_unlock; + } + + t[0].tx_buf = tx_buf; + t[0].len = msg->len; + if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) { + ret = -EFAULT; + goto out_unlock; + } + if (num_msgs > 1) { + msg++; + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto out_unlock; + } + t[1].rx_buf = rx_buf; + t[1].len = msg->len; + } + spi_message_init_with_transfers(&m, t, num_msgs); + + /* Perform the transfer */ + mutex_lock(&spi_lock); + ret = spi_sync(spi, &m); + mutex_unlock(&spi_lock); + + if (ret || (num_msgs == 1)) + goto out_unlock; + + if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len)) + ret = -EFAULT; + +out_unlock: + spi_dev_put(spi); + return ret; +} + +static int penctrl_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi; + u8 current_cs; + + filp->private_data = penctrl; + current_cs = iminor(inode); + spi = penctrl->spi; + spi->chip_select = current_cs; + spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[current_cs]); + spi_setup(spi); + return stream_open(inode, filp); +} + +static int penctrl_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + return 0; +} + +static const struct file_operations penctrl_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = penctrl_ioctl, + .open = penctrl_open, + .release = penctrl_release, + .llseek = no_llseek, +}; + +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t[2] = {}; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] = PENCTRL_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0; + t[0].tx_buf = txbuf; + t[0].len = sizeof(txbuf); + + rxbuf[0] = 0; + t[1].rx_buf = rxbuf; + t[1].len = sizeof(rxbuf); + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi, &m); + if (ret) + return ret; + + *val = rxbuf[0]; + return 0; +} + +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t = {}; + struct spi_message m; + u8 txbuf[4]; + + txbuf[0] = PENCTRL_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t.tx_buf = txbuf; + t.len = sizeof(txbuf); + spi_message_init_with_transfers(&m, &t, 1); + return spi_sync(spi, &m); +} + +static int penctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]); + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto out_unlock; + } + + val |= BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +out_unlock: + mutex_unlock(&spi_lock); + return ret; +} + +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]); + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto out_unlock; + } + + val &= ~BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +out_unlock: + mutex_unlock(&spi_lock); + return ret; +} + +static const struct reset_control_ops penctrl_reset_ops = { + .assert = penctrl_reset_assert, + .deassert = penctrl_reset_deassert, +}; + +static struct miscdevice penctrl_devices[] = { + { .minor = 0, .name = "penctrl.0", .fops = &penctrl_fops }, + { .minor = 1, .name = "penctrl.1", .fops = &penctrl_fops }, + { .minor = 2, .name = "penctrl.2", .fops = &penctrl_fops }, + { .minor = 3, .name = "penctrl.3", .fops = &penctrl_fops }, +}; + +static int penctrl_spi_probe(struct spi_device *spi) +{ + int i, ret; + + /* Allocate driver data */ + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL); + if (!penctrl) + return -ENOMEM; + + penctrl->spi = spi; + mutex_init(&spi_lock); + + for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) { + ret = misc_register(&penctrl_devices[i]); + if (ret) { + dev_err(&spi->dev, "Failed to register device %s\n", + penctrl_devices[i].name); + goto cleanup; + } + } + + /* Register reset controller */ + penctrl->rcdev.dev = &spi->dev; + penctrl->rcdev.ops = &penctrl_reset_ops; + penctrl->rcdev.owner = THIS_MODULE; + penctrl->rcdev.of_node = spi->dev.of_node; + penctrl->rcdev.nr_resets = 1; + device_set_node(penctrl->rcdev.dev, dev_fwnode(&spi->dev)); + + ret = reset_controller_register(&penctrl->rcdev); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register reset controller\n"); + return 0; + +cleanup: + for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) { + if (penctrl_devices[i].this_device) + misc_deregister(&penctrl_devices[i]); + } + return ret; +} + +static const struct of_device_id penctrl_dt_match[] = { + { .compatible = "amd,pensando-elba-ctrl" }, + { /* sentinel */ } +}; + +static struct spi_driver penctrl_spi_driver = { + .probe = penctrl_spi_probe, + .driver = { + .name = "pensando-elba-ctrl", + .of_match_table = penctrl_dt_match, + }, +}; +module_spi_driver(penctrl_spi_driver); + +MODULE_AUTHOR("Brad Larson "); +MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h new file mode 100644 index 000000000000..626b85e3fdb5 --- /dev/null +++ b/include/uapi/linux/amd-pensando-ctrl.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Userspace interface for /dev/penctrl + * + * This file can be used by applications that need to communicate + * with the AMD Pensando SoC controller device via the ioctl interface. + */ +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H + +#include + +#define PENCTRL_SPI_CMD_REGRD 0x0b +#define PENCTRL_SPI_CMD_REGWR 0x02 +#define PENCTRL_MAX_MSG_LEN 16 +#define PENCTRL_REG_CTRL0 0x10 + +struct penctrl_spi_xfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u64 compat; +}; + +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */