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Wed, 13 Sep 2023 09:47:18 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 13 Sep 2023 09:47:18 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Wed, 13 Sep 2023 09:47:15 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , Subject: [Patch v2 1/2] ACPI: thermal: Add Thermal fast Sampling Period (_TFP) support Date: Wed, 13 Sep 2023 22:16:58 +0530 Message-ID: <20230913164659.9345-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913164659.9345-1-sumitg@nvidia.com> References: <20230913164659.9345-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB76:EE_|PH7PR12MB7793:EE_ X-MS-Office365-Filtering-Correlation-Id: a3398da1-ee4f-45be-a3b0-08dbb4791ce5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 16:47:27.0036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3398da1-ee4f-45be-a3b0-08dbb4791ce5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB76.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7793 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Sep 2023 09:49:24 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776945453010429762 X-GMAIL-MSGID: 1776945453010429762 From: Jeff Brasen Add support of "Thermal fast Sampling Period (_TFP)" for Passive cooling. As per [1], _TFP overrides the "Thermal Sampling Period (_TSP)" if both are present in a Thermal zone. [1] ACPI Specification 6.4 - section 11.4.17. _TFP (Thermal fast Sampling Period)" Signed-off-by: Jeff Brasen Signed-off-by: Sumit Gupta --- drivers/acpi/thermal.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index f14e68266ccd..d0bbf42cae9c 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -102,7 +102,7 @@ struct acpi_thermal_passive { struct acpi_handle_list devices; unsigned long tc1; unsigned long tc2; - unsigned long tsp; + unsigned long passive_delay; }; struct acpi_thermal_active { @@ -287,11 +287,17 @@ static void __acpi_thermal_trips_update(struct acpi_thermal *tz, int flag) tz->trips.passive.tc2 = tmp; status = acpi_evaluate_integer(tz->device->handle, - "_TSP", NULL, &tmp); - if (ACPI_FAILURE(status)) - tz->trips.passive.trip.valid = false; - else - tz->trips.passive.tsp = tmp; + "_TFP", NULL, &tmp); + if (ACPI_FAILURE(status)) { + status = acpi_evaluate_integer(tz->device->handle, + "_TSP", NULL, &tmp); + if (ACPI_FAILURE(status)) + tz->trips.passive.trip.valid = false; + else + tz->trips.passive.passive_delay = tmp * 100; + } else { + tz->trips.passive.passive_delay = tmp; + } } } } @@ -683,7 +689,6 @@ static int acpi_thermal_register_thermal_zone(struct acpi_thermal *tz) { struct acpi_thermal_trip *acpi_trip; struct thermal_trip *trip; - int passive_delay = 0; int trip_count = 0; int result; int i; @@ -694,10 +699,8 @@ static int acpi_thermal_register_thermal_zone(struct acpi_thermal *tz) if (tz->trips.hot.valid) trip_count++; - if (tz->trips.passive.trip.valid) { + if (tz->trips.passive.trip.valid) trip_count++; - passive_delay = tz->trips.passive.tsp * 100; - } for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE && tz->trips.active[i].trip.valid; i++) trip_count++; @@ -746,7 +749,7 @@ static int acpi_thermal_register_thermal_zone(struct acpi_thermal *tz) 0, tz, &acpi_thermal_zone_ops, NULL, - passive_delay, + tz->trips.passive.passive_delay, tz->polling_frequency * 100); if (IS_ERR(tz->thermal_zone)) { result = PTR_ERR(tz->thermal_zone); From patchwork Wed Sep 13 16:46:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 138970 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9ecd:0:b0:3f2:4152:657d with SMTP id t13csp1224421vqx; Wed, 13 Sep 2023 09:59:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGRiZ8kc/fvYYK+9OmnLnab8ShUJQWy9pjLKzfsKyU3zvrnBiOlxI7rSJJ0+agY3+qhOnFd X-Received: by 2002:a05:6358:2489:b0:13c:cb1e:9081 with SMTP id m9-20020a056358248900b0013ccb1e9081mr3227170rwc.32.1694624375875; Wed, 13 Sep 2023 09:59:35 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1694624375; cv=pass; d=google.com; s=arc-20160816; b=DZ5/FfMplKncL3JkWhoBbuY65JkMc5o7FJGR7nhc4ImIJKEy9wGUuzoCTI6cRV7C/w FgJ+0+7xgPHyxNGmx5uoiIfE1WA8/XqnL5Ysg9sb9f2DqGfhuHKVnbauad4lc1VwOei4 4g4D4/7quBbjB3/Exa1tGiPudmOhOrPYhlneEctQTufWw1BMklOoAPyFDl9y5kr7mIru 2CtPSpk2s1GpGJbVpu6guOaa1R6W1bKmr6/+jEB/16fDvJenTPkH96TWoUTZPCQtS4u9 jBt2RZJIoL9v1xJauFavniNX6bhVulDZqmRVgCK27lHjsVZqZQL+uoeIJwHyJyhukQIB SrsA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=kwzzw8138+YZ3/lmiNY9SOdnltHoR4qUADwwJh2D/Qg=; fh=qe2i5VGhBVBBTue3PoCsy/W6UI/kVCds/fgUz/LbVRc=; b=joWFTfmdoZUbO7FjfyjDT4Y8A9ZztvhBC0jgZftut7Bcn+4d3zCOWtYlZbL/7gfAK9 3DpPcCGnpkJJ65Xg625Yd/iujRBzWBjFAZmOpaZSAlgZmqzNdO9GWOxjoSBiiKn3uG0t 2ol/a1cb6BsACWEihoDqC2m1CVsiH+AzW2lgnjJ5FmZtdf4GEuAUrq4jYmUMrWrms8P+ Rt8ysdGnNGI8GNcnSxjZdrMwAtgQpDRzUixf9fqxu9SfSD27hn0PdgHyqnpCVPMi4nqC kpMov7N6nAQBpnwmK35UlrwfCwyJNAuVjqr/MP4PgxgzGJm4x6SqznDPUuuBM0luq1tT 1s4Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=M9opHYfT; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from lipwig.vger.email (lipwig.vger.email. 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Wed, 13 Sep 2023 09:47:24 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 13 Sep 2023 09:47:24 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Wed, 13 Sep 2023 09:47:20 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , Subject: [Patch v2 2/2] ACPI: processor: reduce CPUFREQ thermal reduction pctg for Tegra241 Date: Wed, 13 Sep 2023 22:16:59 +0530 Message-ID: <20230913164659.9345-3-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230913164659.9345-1-sumitg@nvidia.com> References: <20230913164659.9345-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|DS7PR12MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: 3af7ba26-6a74-4522-d959-08dbb4792230 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 16:47:35.8851 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3af7ba26-6a74-4522-d959-08dbb4792230 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6119 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 13 Sep 2023 09:48:55 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776942449785756378 X-GMAIL-MSGID: 1776942449785756378 From: Srikar Srimath Tirumala Current implementation of processor_thermal performs software throttling in fixed steps of "20%" which can be too coarse for some platforms. We observed some performance gain after reducing the throttle percentage. Change the CPUFREQ thermal reduction percentage and maximum thermal steps to be configurable. Also, update the default values of both for Nvidia Tegra241 (Grace) SoC. The thermal reduction percentage is reduced to "5%" and accordingly the maximum number of thermal steps are increased as they are derived from the reduction percentage. Signed-off-by: Srikar Srimath Tirumala Signed-off-by: Sumit Gupta --- drivers/acpi/processor_thermal.c | 41 +++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c index b7c6287eccca..30f2801abce6 100644 --- a/drivers/acpi/processor_thermal.c +++ b/drivers/acpi/processor_thermal.c @@ -26,7 +26,16 @@ */ #define CPUFREQ_THERMAL_MIN_STEP 0 -#define CPUFREQ_THERMAL_MAX_STEP 3 + +static int cpufreq_thermal_max_step = 3; + +/* + * Minimum throttle percentage for processor_thermal cooling device. + * The processor_thermal driver uses it to calculate the percentage amount by + * which cpu frequency must be reduced for each cooling state. This is also used + * to calculate the maximum number of throttling steps or cooling states. + */ +static int cpufreq_thermal_pctg = 20; static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_pctg); @@ -71,7 +80,7 @@ static int cpufreq_get_max_state(unsigned int cpu) if (!cpu_has_cpufreq(cpu)) return 0; - return CPUFREQ_THERMAL_MAX_STEP; + return cpufreq_thermal_max_step; } static int cpufreq_get_cur_state(unsigned int cpu) @@ -113,7 +122,8 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) if (!policy) return -EINVAL; - max_freq = (policy->cpuinfo.max_freq * (100 - reduction_pctg(i) * 20)) / 100; + max_freq = (policy->cpuinfo.max_freq * + (100 - reduction_pctg(i) * cpufreq_thermal_pctg)) / 100; cpufreq_cpu_put(policy); @@ -126,10 +136,35 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state) return 0; } +#define SMCCC_SOC_ID_T241 0x036b0241 + +void acpi_thermal_cpufreq_config_nvidia(void) +{ +#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY + s32 soc_id = arm_smccc_get_soc_id_version(); + + /* Check JEP106 code for NVIDIA Tegra241 chip (036b:0241) */ + if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241)) + return; + + /* Reduce the CPUFREQ Thermal reduction percentage to 5% */ + cpufreq_thermal_pctg = 5; + + /* + * Derive the MAX_STEP from minimum throttle percentage so that the reduction + * percentage doesn't end up becoming negative. Also, cap the MAX_STEP so that + * the CPU performance doesn't become 0. + */ + cpufreq_thermal_max_step = ((100 / cpufreq_thermal_pctg) - 1); +#endif +} + void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy) { unsigned int cpu; + acpi_thermal_cpufreq_config_nvidia(); + for_each_cpu(cpu, policy->related_cpus) { struct acpi_processor *pr = per_cpu(processors, cpu); int ret;