From patchwork Thu Nov 3 17:58:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15061 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp682374wru; Thu, 3 Nov 2022 11:01:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM68gXLAN6kSsCuhlXDmHvDUDjqlS4wd2r5uo1LxDLDcxTEj/0ymHnecGhxLFaFvCZzBEnWC X-Received: by 2002:a65:4c0e:0:b0:46a:eeb1:e78a with SMTP id u14-20020a654c0e000000b0046aeeb1e78amr27073734pgq.193.1667498470560; Thu, 03 Nov 2022 11:01:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498470; cv=none; d=google.com; s=arc-20160816; b=YPaJvM/XZRfsR+66m/PrW1NE1QTFjXdwM0ETPsqfXnd7mv268eyMXnrY0blHAi3uBf d6rZkkYjqM/RnougSxR6Ebspo1+aq2WvduHe0og/cOSGM40UsqpYYfcDU+oIFs9y2rFd 40mkKZbRrFbppML5QFINw4F30KP0VyO7GJh5YsxGhOdo/4Fxe0fyUCr6ck+EmlKpKvDQ yJG6ztgLMpeo6DXiVht09QFKyZc3UxO1LCKTSdg1ZoeN5pMAE05thph7gnzrJAdLLeV7 joV1vXEzEEWE96d5TU9AhQkMC+cc9O3UXjBy1J0d0QvgWnz9bGaYgQnHIKXhN2n2BO3u 01tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZtRYN3/lWBQEhA9qI17tcYVOl/gNwOwCoS7CIHGd670=; b=ORjWKjvCzxdHco4D4ezlAMEztzGzIyKFV+IL2syF4uF2QBj5j9TB0CgVw3ChYMPpQJ lMzZltr2kP92Dnv3Z8DWd5DntrJk8D7/tm5ttifR/STZasEAVRaIP0MJFjYrnvcXgop5 WuegMpr508UxyI0okaZNg42icRBz/zvTbTTJWQIBB5HW3Y+dlEYT1MdwoDZuHNAOC9KZ TDHFMxQv87MNYQEPG2mvnRbci6/I8iD3hhbl+5+l4Mncu+IR6WD29ybjJ767nFj1RpDm uGEo10g3ZTTT3bI032DEYwj3h2GUbjUb0QllpwcxSX7N5VPlhO588jgbiZ04XBR3tKNM AR3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bIWFEOAe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h14-20020a63df4e000000b0045cbd4e43a1si1791388pgj.57.2022.11.03.11.00.57; Thu, 03 Nov 2022 11:01:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bIWFEOAe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232081AbiKCR75 (ORCPT + 99 others); Thu, 3 Nov 2022 13:59:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232042AbiKCR71 (ORCPT ); Thu, 3 Nov 2022 13:59:27 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53C972628 for ; Thu, 3 Nov 2022 10:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498359; x=1699034359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IRafYvcGTb3XRIZ8BF10OMlvhWCpsdfukSgZuf8/1v8=; b=bIWFEOAeCGrPWyjKFHyXRC4UxDwtcJ3DglJJHuWAwJfDXrfHh9E0/wzM trifDp6L+lVtU0fBUvQ5Q7Bm3oo8D9P1ku7GM/7Dof/TFIDbcEP5hbH2a bJx26hsohmpVTRpjjlsgmpOJuX3nS6ZgnQTD94ipwORzdSsjEyi7uOSK5 D4RGpriRcl2eKseFNp7gwzunTi9DEMmJbX5mcjBE0FH2eDDr3TcKFCarr Vu33aq6MzyuvE4diI2KHzIG84wOodvOrlVbp5Pt08yB7TLE6KxxwrsE4R lV2a0xwfrJE2c11Hmyn87LlaPGd6NmvLC4ewGKnUBYjJusjTp/HY3PLUw w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476963" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476963" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762540" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762540" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 01/13] x86/microcode/intel: Prevent printing updated microcode rev multiple times Date: Thu, 3 Nov 2022 17:58:49 +0000 Message-Id: <20221103175901.164783-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498876429794153?= X-GMAIL-MSGID: =?utf-8?q?1748498876429794153?= Commit b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") introduced a race where all CPUs follow this call chain: microcode_init()->schedule_on_each_cpu(setup_online_cpu)->collect_cpu_info This results in console spam where multiple CPUs print the signature. [ 33.688639] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 [ 33.688659] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 [ 33.688660] microcode: sig=0x50654, pf=0x80, revision=0x2006e05 Fix by making sure only boot CPU prints the message. Fixes: b6f86689d5b7 ("x86/microcode: Rip out the subsys interface gunk") Reported-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 8c35c70029bf..8f7f8dd6680e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -680,6 +680,7 @@ void reload_ucode_intel(void) static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { + bool bsp = cpu_num == boot_cpu_data.cpu_index; static struct cpu_signature prev; struct cpuinfo_x86 *c = &cpu_data(cpu_num); unsigned int val[2]; @@ -696,8 +697,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) csig->rev = c->microcode; - /* No extra locking on prev, races are harmless. */ - if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { + if (bsp && csig->rev != prev.rev) { pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n", csig->sig, csig->pf, csig->rev); prev = *csig; From patchwork Thu Nov 3 17:58:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp682424wru; Thu, 3 Nov 2022 11:01:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4VP1b9P6e4Ubbzai5CsUejMfv18pj+sQwXkLcN0j/2ertLlp2sV6PJOe7UMPb1O5Q5QrWC X-Received: by 2002:a65:6bc7:0:b0:44a:dcee:18a5 with SMTP id e7-20020a656bc7000000b0044adcee18a5mr26704263pgw.413.1667498474338; Thu, 03 Nov 2022 11:01:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498474; cv=none; d=google.com; s=arc-20160816; b=lS9N1NGVVFiHt9MWxEor+DdR/bX699lqUQAmJ1+CmIM7a5hGg4fe3DFvdk2MuB+d5D JpGBp9Qig0cXgjHT/vEUZ4oemXrtAqCou3oaYT4GrmIqfswkBwbKpK2e3PJS9ySN/CO+ lLgUt+rYd2Ob/JlmhIm/tni6GfL08IYKjRORqBfKJiwnw8y6VC00bdZuwsr/zU0NeCUc RYIF34oe42i4bvlCXuErGdCOItiTebcYBwd+Pthsal46BoN408WOgoCBCAdQ+pqS1DcU NBgtuG62och8kBc6EQyaDZJ2g5DXo8dDk0UdJMr4bQmGKc8IMWuLHq56G5Q0zz8awX+U m+Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HGYPBevIwftb57JarkNvl5VBq+n4GQD0WTeGu3SfO1c=; b=Y9B3j0UY3v2kI/yW62USiErI/W2E3OzVJUlOE8o0AtmMDBjn9zNu4jCBckFq5bfm1F FfwapNv77ram0ntu2a+eOLEWPKvOzkCjQn/4lOyfQaCh6iw0M9BUw/VaEJLtGB6t8s6V /TO8ryIYDuRryHcTcRZIt4OEYpVzVY3S145md08QXUtxagglqG1VGYmM2rV5n8kjiChU FCD2hZzwsg0cuYjbgZugwxon5ky1HB2rlyLTaaeYbAtjMnrvGnU5TZVhM/IYC90z94IM jTo9LBhcr1L3kLZQwJtxJPCjUHPIZjAMn+auVRwIXHWBQOaxmciPZJVH13S50PD8giQr vYTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nHG1xY6D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k128-20020a633d86000000b0044d72a10ab0si1651482pga.342.2022.11.03.11.01.01; Thu, 03 Nov 2022 11:01:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nHG1xY6D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231375AbiKCSAK (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232046AbiKCR72 (ORCPT ); Thu, 3 Nov 2022 13:59:28 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56D7921AA for ; Thu, 3 Nov 2022 10:59:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498360; x=1699034360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lKzd4BANu2bgNbu2ahohiJ2FtGh1ZWNJCmGjkxUmCxo=; b=nHG1xY6DflcvwbmEo/G9ydT0VEuCl/6t+lPle6eaxcw9ux/UaEoBOYSL FfL/srFnUKAmglho7bHlDnp3/fI1pXCAnbAzH0F7jFiPfnP4QBpTp7YLU T0JjHzR4AMVvJTeplEVgi8AnvP/3kEdZG05oiB58AgDE5tbtvRgzz58eV kIGY7JYlP2xKLgPTMuh0s+Je0X9svnHrJxyerluUVqMUIOA9GZ5QKw0I/ mudviqL3ezeBPB+y241/dTY8rcTsKKydZdVSemmyOe6dYDMKOVsrilEx5 evIUQkSXTtnayXSXm2H/OE1U1iPOQ0mNzhvDA2a0pfnG3CjFR9d6GVuj9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476964" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476964" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762544" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762544" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 02/13] x86/microcode/intel: Print old and new rev after early microcode update Date: Thu, 3 Nov 2022 17:58:50 +0000 Message-Id: <20221103175901.164783-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,PDS_OTHER_BAD_TLD, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498880196898593?= X-GMAIL-MSGID: =?utf-8?q?1748498880196898593?= Print the old and new versions of microcode after an early load is complete. This is useful to know what version was loaded by BIOS before an early microcode load. Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- v2: - (Boris) Fix microcode update message consistent for early and late. - apply_microcode_intel(): prev_rev isn't set until the first update. arch/x86/kernel/cpu/microcode/intel.c | 32 +++++++++++++++++---------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 8f7f8dd6680e..733b5eac0444 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -435,10 +435,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) * Print ucode update info. */ static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +print_ucode_info(u32 old_rev, struct ucode_cpu_info *uci, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - uci->cpu_sig.rev, + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, uci->cpu_sig.rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); @@ -448,6 +448,7 @@ print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) static int delay_ucode_info; static int current_mc_date; +static u32 early_old_rev; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -458,7 +459,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(early_old_rev, &uci, current_mc_date); delay_ucode_info = 0; } } @@ -467,11 +468,12 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(u32 old_rev, struct ucode_cpu_info *uci) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + u32 *old_rev_p; mc = uci->mc; if (!mc) @@ -479,13 +481,15 @@ static void print_ucode(struct ucode_cpu_info *uci) delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); + old_rev_p = (u32 *)__pa_nodebug(&early_old_rev); *delay_ucode_info_p = 1; *current_mc_date_p = mc->hdr.date; + *old_rev_p = old_rev; } #else -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(u32 old_rev, struct ucode_cpu_info *uci) { struct microcode_intel *mc; @@ -493,14 +497,14 @@ static inline void print_ucode(struct ucode_cpu_info *uci) if (!mc) return; - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(old_rev, uci, mc->hdr.date); } #endif static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 old_rev, rev; mc = uci->mc; if (!mc) @@ -517,6 +521,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) return UCODE_OK; } + old_rev = rev; /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -533,9 +538,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci); + print_ucode(old_rev, uci); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(old_rev, uci, mc->hdr.date); return 0; } @@ -739,6 +744,9 @@ static enum ucode_state apply_microcode_intel(int cpu) goto out; } + if (!prev_rev) + prev_rev = rev; + /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -757,8 +765,8 @@ static enum ucode_state apply_microcode_intel(int cpu) } if (bsp && rev != prev_rev) { - pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", - rev, + pr_info("update 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + prev_rev, rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); From patchwork Thu Nov 3 17:58:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15065 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp683551wru; Thu, 3 Nov 2022 11:02:53 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4H7iyOiRugNUTaXH7T+Vxcq8BgcZT+mxegCK2dZMl3ugsKXFoRmeCSat+kVKhEO/Orw0Sg X-Received: by 2002:a17:906:da86:b0:7ad:dc94:1b7 with SMTP id xh6-20020a170906da8600b007addc9401b7mr20208978ejb.288.1667498566108; Thu, 03 Nov 2022 11:02:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498566; cv=none; d=google.com; s=arc-20160816; b=lIFGF/b5Vr7hn2p39uNO7J/SiAnAE42IC/oK8IgLjg4jqPeAYcxS0gNzmZ2Mm6AVZ1 TYBiYNnRWzjk8tSaIUHwByBMikfokc7acYJK+p7PkGeP0Cu5QDMLvf10UgwM4uldLIGl 8ODY5wQcMGm00V9hxcRoR1KA58O+W8sD6Vs+LM8cawCf2zrx5j+C5yvyWmdT2lACgsM5 LJjXxO5FtWKkej1uxJvYREh5nw5GdbKQd/Hkv8EdS2MGGsCXVbT1bCqQABPSy0Q9O69/ TbOOzFgMJDFQ8YUa10Wlk6WezYKaTJmfoleU5GYKWLeY5T3QRtmD6zHkn41x+uoPNt54 8zsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=q/i7d/GFOXwLz0NcZsTXwIAcsUbDY8yxDLsOFsoNmaU=; b=nVnpC8H8/iDpKB6Ly2vklrO+tqpuSdfp3nmVMi9ia51cxDvVIVENGwMNd5ecJsDZpX irdL8X/tz8tJ1eXi0mZ89OX3ZppeThSMGtrZhPvkhoEBCJDh6GAwpMs+DwUnZx/ycCxk 2Z2FnN1TOsOp2pG3GmlXt64ezkr5HkL1WB0z6aqUDLazGaBI9I7bUey/qGxXzLUNZfh3 1y0DQOLkLCzb2ZpfBJRzZe6mEiOdXgPHBWE7zRmGblcEYzzecOU+NGTIr2FANmsYP9hv rEuUwwoDAkztbhWvovoTLeOW/tOzYnf81Ri+7g94l2OanFQgyw4Q5ES6XIno5j4w2YaW poKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fQxmtkdq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l9-20020a170906794900b0078dc5b2b6c4si2151929ejo.666.2022.11.03.11.02.21; Thu, 03 Nov 2022 11:02:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fQxmtkdq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231925AbiKCSAO (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232049AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 672FC2BC7 for ; Thu, 3 Nov 2022 10:59:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498360; x=1699034360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EQQs2oxMSF89nE0NdVO0VqxxpugPawYi9iOrJgEYQNQ=; b=fQxmtkdqLVlYUQtPsURxuiyIf8W2S/AVNxtMigVguLW0bGGZvd7q5pq3 ur6A4f9CaEZeu2LyHF4kh6lmv3UBXvVNRlccNjvJXhzFr5tSn5mGUsuKK 6I1msJSoLFsE6lwGeLFslrxV9f+l+cPh71wIW59M5+m1rcMJptssygFcs /5S6rfE5FxyLWq4Mr8QKFfX3oHb6D72wfMhwu16dXVpdxHRXmO+qtshka T7icyB4rP0JJa0PCJgiuIfCwmAlB7Bk0rXhG2DDZaonTKNZoAy9AVUzEo o/2FEpn4ItWoLPsMTfAEj1qvqLexQmK6STAqzOhc3xE0XhKn+ZBKiP05g g==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476966" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476966" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762547" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762547" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:17 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 03/13] x86/microcode/intel: Fix a hang if early loading microcode fails Date: Thu, 3 Nov 2022 17:58:51 +0000 Message-Id: <20221103175901.164783-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498975961117334?= X-GMAIL-MSGID: =?utf-8?q?1748498975961117334?= When early loading of microcode fails for any reason other than the wrong family-model-stepping, Linux can get into an infinite loop retrying the same failed load. A single retry is needed to handle any mixed stepping case. Assume we have a microcode that fails to load for some reason. load_ucode_ap() seems to retry if the loading fails. But it searches for a new rev, but ends up finding the same copy. Hence it appears to repeat the same load, retry loop for ever. load_ucode_intel_ap() { .. reget: if (!*iup) { patch = __load_ucode_intel(&uci); ^^^^^ Finds the same patch every time. if (!patch) return; *iup = patch; } uci.mc = *iup; if (apply_microcode_early(&uci, true)) { ^^^^^^^^^^^^ apply fails /* Mixed-silicon system? Try to refetch the proper patch: */ *iup = NULL; goto reget; ^^^^^ Rince repeat. } } Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 733b5eac0444..8ef04447fcf0 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -606,6 +606,7 @@ void __init load_ucode_intel_bsp(void) { struct microcode_intel *patch; struct ucode_cpu_info uci; + int rev, ret; patch = __load_ucode_intel(&uci); if (!patch) @@ -613,13 +614,18 @@ void __init load_ucode_intel_bsp(void) uci.mc = patch; - apply_microcode_early(&uci, true); + ret = apply_microcode_early(&uci, true); + if (ret) { + rev = patch->hdr.rev; + pr_err("Revision 0x%x failed during early loading\n", rev); + } } void load_ucode_intel_ap(void) { struct microcode_intel *patch, **iup; struct ucode_cpu_info uci; + bool retried = false; if (IS_ENABLED(CONFIG_X86_32)) iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); @@ -638,9 +644,13 @@ void load_ucode_intel_ap(void) uci.mc = *iup; if (apply_microcode_early(&uci, true)) { + if (retried) + return; + /* Mixed-silicon system? Try to refetch the proper patch: */ *iup = NULL; + retried = true; goto reget; } } From patchwork Thu Nov 3 17:58:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15064 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp683138wru; Thu, 3 Nov 2022 11:02:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4chEdc0oEDXLEmfyAXzQeD8z4IL3ULUC7XgiJe7ciFP5nXQYQY2fH448jyl2GaFXjJ0gRt X-Received: by 2002:a17:90b:2751:b0:20a:e437:a9e8 with SMTP id qi17-20020a17090b275100b0020ae437a9e8mr48491601pjb.181.1667498538232; Thu, 03 Nov 2022 11:02:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498538; cv=none; d=google.com; s=arc-20160816; b=WOn+QfDAuhYhOxl6xeBr5TsNp/KmpBVawvPow7Jg/gmaL+4mDOJItRMzJpJyrRleam qxN4Q8fmjspIm9PNwa8HV89zbddF6QxLBkRXf6x6spVnF3CButq9fX/HKA9zCcs229J1 GUoeK+HF23zZSrB4zg2t8dAnEuQp4+VaFvTbrv57DgW3WEK5IiQ7Jy6iKkm9ju0UCJpn k2LTTaY+5OP3cv7sCHI/V8trDB72aUo1D6oE6QlRWDH5jNZwJpn2WOAkHArcBMGB4TDT GbKb3bkeu7C9Rc0RNo45KKDDGHAGYkpjZUtt5ea8LSWnimULz9dwBdeEn28YxlkUW5GP qjAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Isn9lxb5OdxUT8BAQp62Bne6B8M04yiVPo1Mwi6tGCo=; b=QcHGw1tMkNb16c0IZ/tANWlCnZY/cGNzpqNeclpWtOrpO3XAH+0CaS2qPPZe7xERrr qyDU35+CHFCwyoVBVEHD3tf+nZ+nXWcTwsKWGy6lBx3X7WLAuhSGNLuBJp4lsDliY8h1 CLqSJ5KTfnSnjrXtjQ/Sh0ao7I6teLPBbCQvyalyg6okJYFmoZCbGj+fDVdD1FM+AkFw MRioJT9Hf4MdS34n+NuBdVgJhxp2wTarin2qbbbv+yCQ8iC7TBM8anX1d0VALlUBtssq i9AZmGWX3tf89CiolkRbZoUf4fvMxG4Iv+295O1okoorqk+h6v5Lvv+xosqdvhx+BBdK 4VwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YNnUTjkj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t16-20020a056a00139000b00558991a667esi1642281pfg.359.2022.11.03.11.02.02; Thu, 03 Nov 2022 11:02:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YNnUTjkj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231864AbiKCSAZ (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232055AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B85F2BC9 for ; Thu, 3 Nov 2022 10:59:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498360; x=1699034360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6ofiZPePB3pOVJyIuYvJbayrHFNZGL3ftaAhWziWnjE=; b=YNnUTjkjtWEyhiPdmQn1jOcGFpz4g2SC3SZEJFCkyuecQZ82RZSlnMxi fxXZquHrf2CVRmuNvigB2XDS9s4hbVv88oA7Rf/gWAXXwfMv0BNkE1k3M ARMMfQHe0ExTecK+0khIcJ4M2YSIvNgTKewyDQcysIaGhNCBc3L71gxSX OSwjNf1WBydMh+reLn7ft1kduv1d1FpB44+5PBKu5zAITaevEWIIozTmD zEbjCBJgRMQHJYknzl3x8Con9jkJX3DY0WbAUXyJO00mfUAahKmdif53/ Du7fqoaUp7Km7RrcFw4JuFEHWjBRUJ34CPpIK+uoHZORmm99TqpuS5NlU A==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476967" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476967" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762550" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762550" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 04/13] x86/microcode: Fix microcode_check() compare after a new uCode update Date: Thu, 3 Nov 2022 17:58:52 +0000 Message-Id: <20221103175901.164783-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498947028895765?= X-GMAIL-MSGID: =?utf-8?q?1748498947028895765?= microcode_check() seems to take a snapshot after an update to compare with previously cached values of x86_capabilities. Some capabilities can be turned off by OS as a result of certain command line parameters or due to some configuration. Even though there was no change in CPUID bits, reloading the same microcode threw a warning, that some CPUID bits changed. To eliminate the false warning, take a snapshot before the update and one after the update. This eliminates the miscompare. Also move the microcode_check() from cpu/common.c -> cpu/microcode/core.c Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/include/asm/processor.h | 1 - arch/x86/kernel/cpu/common.c | 32 ----------------- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 34 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 67c9d73b31fa..2acc8ae0bf47 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -835,7 +835,6 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..bbd362ead043 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2305,38 +2305,6 @@ void cpu_init_secondary(void) } #endif -#ifdef CONFIG_MICROCODE_LATE_LOADING -/* - * The microcode loader calls this upon late microcode load to recheck features, - * only when microcode has been updated. Caller holds microcode_mutex and CPU - * hotplug lock. - */ -void microcode_check(void) -{ - struct cpuinfo_x86 info; - - perf_check_microcode(); - - /* Reload CPUID max function as it might've changed. */ - info.cpuid_level = cpuid_eax(0); - - /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). - */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); - - get_cpu_cap(&info); - - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) - return; - - pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); - pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); -} -#endif - /* * Invoked from core CPU hotplug code after hotplug operations */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 712aafff96e0..9ed1f6e138d6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -40,6 +40,8 @@ #include #include +#include "../cpu.h" + #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; @@ -431,6 +433,51 @@ static int __reload_late(void *info) return ret; } +static void copy_cpu_caps(struct cpuinfo_x86 *info) +{ + /* Reload CPUID max function as it might've changed. */ + info->cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability)); + + get_cpu_cap(info); +} + +/* + * The microcode loader calls this upon late microcode load to recheck features, + * only when microcode has been updated. Caller holds microcode_mutex and CPU + * hotplug lock. + */ +static void microcode_check(struct cpuinfo_x86 *orig) +{ + struct cpuinfo_x86 info; + + perf_check_microcode(); + + /* Reload CPUID max function as it might've changed. */ + info.cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + + get_cpu_cap(&info); + + if (!memcmp(info.x86_capability, &orig->x86_capability, sizeof(info.x86_capability))) + return; + + pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); + pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); +} + /* * Reload microcode late on all CPUs. Wait for a sec until they * all gather together. @@ -438,6 +485,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old = boot_cpu_data.microcode, ret; + struct cpuinfo_x86 info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -445,9 +493,10 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); + copy_cpu_caps(&info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) - microcode_check(); + microcode_check(&info); pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); From patchwork Thu Nov 3 17:58:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15072 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp685140wru; Thu, 3 Nov 2022 11:05:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6pWsYcsBpKXJr/315tOpf8HVBJ2kXqrchu0qz/7ioRQnar8Wmi3JCjKFK5+z90wYOY5Az1 X-Received: by 2002:a17:906:9bd5:b0:7ae:2964:72c8 with SMTP id de21-20020a1709069bd500b007ae296472c8mr1537570ejc.494.1667498700856; Thu, 03 Nov 2022 11:05:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498700; cv=none; d=google.com; s=arc-20160816; b=pdTE245i4wUcM2PcWqeA6RgcOuCHQ1b+vpQLKnMxga5Wgud75zMh5jtMyn7Nqlh3H7 kE+ZoESkZbnmC4DIIX1QRi5QYA05iidl2Zmu0+hB2QT6P5Dh+edkztxVX5abmmJBEReU t7izW3CiOXVpwki3MjoS7YuKpFpgG7oeO0ml2HO6gZmFZZttEKg6TxFsIzPjPgfCxkc/ IiWffv3tzPMv5pyjM6GTfWsEiSE/7+5VY6lWQY8NP4j7JE5Iox1qDjKLHzlbvzge1rHF /zxUcAE4J8UHq1ybITk1zSwKN+5bxYd3oaqGqUjrG6/ybapLteYp4F8KY8SWmn3qqmq8 Fd/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uqk1QiI+feuT+a0iKgYJ73dVYoiiWQOjO3TNbCjS5ug=; b=Rj43bGpZQlIRk/FFB3cTz55cEBcEsdFXuWKU9CaYgQA+toUn3flV92J3msQTY9XzEB MaP5Ps9gdj4jIWvnYo1CwNB/KG+7I2sFUsLK+G5CQJNCoGZQkZyAA1KnUIx5aRbShyAg vObHX3ImGRLNj09IKBYKFDhBrB34msTKmJkbwTEi/QVF104uKxSItZE3Gj84uP37R40p YU+x0RUHqxjQt++Egcu8dQZndx0ELfne0am7D/En2NbrhBnOMSvUuf4RvJjusB7irI8o JapZmoIhqYVAv8iDu0hHN4Azzwjqmg578aBPQJiIJUd6SG5sPRVXj5z2R9iNx0N+nFF6 kP4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GkUHW4+h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ji10-20020a170907980a00b007330c08fe49si2013305ejc.206.2022.11.03.11.04.34; Thu, 03 Nov 2022 11:05:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GkUHW4+h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232016AbiKCSAe (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317262DFB for ; Thu, 3 Nov 2022 10:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498361; x=1699034361; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KpdhtG2RZ4I61tK91zuLU/1Q/Ncurh7LzYmq24qDOyw=; b=GkUHW4+hgeuoIMhUC4SaeyzCgnd/fW3eQyscCCXthi3AhGne7qYHujOT qXqNltNdnsYHcVC1c/KztdR/7KuVEydKa5eFHkw0GMdHLASg0UYW6luLW nVly9a01Su3Fh6pLTxLH69Jwu+Q2QWfzahA+UHtviKZyjesrEiIDX2b0W hLitQdiLT9TNFeI+65op+zQoFFrCf3kindQfya534jfQJh+6SFdLGDPI7 urE4F/PLhYbdgXdHKxRQ+omvhNVCf5/3gjp28MEr5WxP2TjlKH2/mDDYU M9LJhI6AgIyBGnOsb470PVeTXnClYFA6c38zEXXhZE8wiC5k/9/jyoUCk g==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476968" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476968" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762553" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762553" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 05/13] x86/microcode: Move late-load warning to earlier where kernel taint happens Date: Thu, 3 Nov 2022 17:58:53 +0000 Message-Id: <20221103175901.164783-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499117740486925?= X-GMAIL-MSGID: =?utf-8?q?1748499117740486925?= Move where the late loading warning is being issued to earlier in the call. This would put the warn and taint in the same function. Just a tidy thing, no functional changes. Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 9ed1f6e138d6..d41207e50ee6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -487,9 +487,6 @@ static int microcode_reload_late(void) int old = boot_cpu_data.microcode, ret; struct cpuinfo_x86 info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); @@ -530,6 +527,9 @@ static ssize_t reload_store(struct device *dev, if (tmp_ret != UCODE_NEW) goto put; + pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); + pr_err("You should switch to early loading, if possible.\n"); + mutex_lock(µcode_mutex); ret = microcode_reload_late(); mutex_unlock(µcode_mutex); From patchwork Thu Nov 3 17:58:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15076 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp685634wru; Thu, 3 Nov 2022 11:05:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5NESGOcxHetZSNW5xvvIA5ZRw4pZoQhNh4lk0pn3r3cpLUcdf9JKSaCA6q3ky6ZBBchQO8 X-Received: by 2002:a17:906:858a:b0:7ad:d164:bc45 with SMTP id v10-20020a170906858a00b007add164bc45mr22717996ejx.113.1667498741159; Thu, 03 Nov 2022 11:05:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498741; cv=none; d=google.com; s=arc-20160816; b=N2U6eWZfV++IRbH28djhREsqxpOsZptgc4ZjpmUUY//poYQHZhxSQbwfsLIcrAsyx6 eRH78Jbi5BsbkhMv11WhJ19venT3krey7Ppwtqix6uxN7zgzRrL9eLeNNgg8v6g4HRnn 3BEjnq4/Q2h5iIYDsE4+/0MhhNuOK1DXji7GUFB9pl2KIkpZTUvRttxroOzfPth9b0cC BMh3mGMd2Lr2bt8DFcRb9YGNgsyNbhWbpJSQR6qxwA4WYbKgPE7CFMoanwZ70i30tbMO LhIkt5zKEhKAiUPAgLSxkaOfqiay1mldCIpdAAsLXy703ZnFLrEmBXXY9cs1kNZy5UjE kWdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aPPaxjH35SoWYCwWl8gpmUGlfIRCLejs0BLA/USNSM0=; b=dsVQjuxmJlhxIZPWIfgAbAp1eaVqLJMgliv5LTY5H1BFSrRjm5ljwZtP/vUHQM5ojO JvoLxjpJZ0t0noaewlZjLbKCxvbtQcPYhER5sv1PR0zGkRxWq8Ih0bcOJhEXiBp3gFkR pvHipowtRmCvna9OZL37S4iHIcunYo5UfCb5x0QPDgGEUpAchumq3rIzU9vnRjAI2J+4 UJ1vB5rd0QXqRJYX2Gr0UWKW0LmpDEG/43iy7y9PVOa1KLWsgMVEmP2V3CeCWNTZqwxo YSpKXbJDQLhKChxrQ0bIzlmg5nb7xSO5BAER3lO85YfnMKoPhF+Cop7iFCeln95xA0Y0 lT8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mpx6SJJZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id eb6-20020a0564020d0600b0045ce40540ebsi2192454edb.269.2022.11.03.11.05.17; Thu, 03 Nov 2022 11:05:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mpx6SJJZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231222AbiKCSAm (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232072AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7107E5F97 for ; Thu, 3 Nov 2022 10:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498362; x=1699034362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OZimIu89EeGi5tqLMGLYWDXCZnDY709jANJn7l/dlDM=; b=Mpx6SJJZHPkR7EsUdeLIiScHl6ObAm4/NLI9wgNZcQJJcNmBFCe8Nl5u 2BsdYZMKpQ5W6VF2+kgw0xuSB6PU8Q7yb0/A3YjNHcl/lsE2Je445wBDo fBdNHNWctgZeShvO8hK3UPEyrSrYQNt7GDjO2N4zvln1rnOnzPCN5ItvN NnBK8Hch3qUxuF3B7jG33sK3oTQzsLI0A5XoSKY1NcJxNwVobsWI9gWOL 3FyjBrprcT+VRX8hZj6NAaMicXj5Wi/JaF7Zk2sH6f/NDryWx/fWQ3VKO EsV3fNZXODjIjY+YJpyvrKg5O35vjZxvZdVF4yuNAuxhrAknYLO4Y4ctd w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476972" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476972" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762556" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762556" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Jacob Pan , Ashok Raj Subject: [v2 06/13] x86/ipi: Support sending NMI_VECTOR as self ipi Date: Thu, 3 Nov 2022 17:58:54 +0000 Message-Id: <20221103175901.164783-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499159669951989?= X-GMAIL-MSGID: =?utf-8?q?1748499159669951989?= From: Jacob Pan apic->send_IPI_self() can be used to send any general vector as a self IPI. The function uses a SHORTCUT specifier, but it can't be used to send a vector with delivery mode as NMI. Chapter 10, Advanved Programmable Interrupt Controller (APIC) Table 10-3 indicates that the shortcut isn't a legal combination for NMI delivery. The same is true for x2apic implementations as well, the self IPI MSR can only specify the vector number, but no delivery mode. The helper adds proper handling if the vector is NMI_VECTOR. Suggested-by: Ashok Raj Signed-off-by: Jacob Pan Co-developed-by: Ashok Raj Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/apic/ipi.c | 6 +++++- arch/x86/kernel/apic/x2apic_phys.c | 6 +++++- arch/x86/kernel/nmi_selftest.c | 32 ++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 2a6509e8c840..e967c49609ef 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -239,7 +239,11 @@ void default_send_IPI_all(int vector) void default_send_IPI_self(int vector) { - __default_send_IPI_shortcut(APIC_DEST_SELF, vector); + if (unlikely(vector == NMI_VECTOR)) + apic->send_IPI_mask(cpumask_of(smp_processor_id()), + NMI_VECTOR); + else + __default_send_IPI_shortcut(APIC_DEST_SELF, vector); } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 6bde05a86b4e..cf187f1906b2 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -149,7 +149,11 @@ int x2apic_phys_pkg_id(int initial_apicid, int index_msb) void x2apic_send_IPI_self(int vector) { - apic_write(APIC_SELF_IPI, vector); + if (unlikely(vector == NMI_VECTOR)) + apic->send_IPI_mask(cpumask_of(smp_processor_id()), + NMI_VECTOR); + else + apic_write(APIC_SELF_IPI, vector); } static struct apic apic_x2apic_phys __ro_after_init = { diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index a1a96df3dff1..f4b813821208 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -105,6 +105,36 @@ static void __init local_ipi(void) test_nmi_ipi(to_cpumask(nmi_ipi_mask)); } +static void __init self_nmi_test(void) +{ + unsigned long timeout; + + cpumask_clear(to_cpumask(nmi_ipi_mask)); + cpumask_set_cpu(smp_processor_id(), to_cpumask(nmi_ipi_mask)); + + if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, + NMI_FLAG_FIRST, "nmi_selftest", __initdata)) { + nmi_fail = FAILURE; + return; + } + + /* sync above data before sending NMI */ + wmb(); + + apic->send_IPI_self(NMI_VECTOR); + + /* Don't wait longer than a second */ + timeout = USEC_PER_SEC; + while (!cpumask_empty(to_cpumask(nmi_ipi_mask)) && --timeout) + udelay(1); + + /* What happens if we timeout, do we still unregister?? */ + unregister_nmi_handler(NMI_LOCAL, "nmi_selftest"); + + if (!timeout) + nmi_fail = TIMEOUT; +} + static void __init reset_nmi(void) { nmi_fail = 0; @@ -157,6 +187,8 @@ void __init nmi_selftest(void) print_testname("local IPI"); dotest(local_ipi, SUCCESS); printk(KERN_CONT "\n"); + print_testname("Self NMI IPI"); + dotest(self_nmi_test, SUCCESS); cleanup_nmi_testsuite(); From patchwork Thu Nov 3 17:58:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15068 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp684625wru; Thu, 3 Nov 2022 11:04:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4glb1/WtzRj5YBUJMexOlg0D8a3PxId/bOtz7oTzHR26y6FpqiQRnuVShuTg9r8LlMCZDM X-Received: by 2002:a05:6402:51a:b0:461:970e:2adc with SMTP id m26-20020a056402051a00b00461970e2adcmr31234841edv.44.1667498658539; Thu, 03 Nov 2022 11:04:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498658; cv=none; d=google.com; s=arc-20160816; b=FG5S0d4jsX1JPY1RFYm1OsItQ0rMcgHKBXO6AMISo/yUe499gmcElZkdQrYwtvUUB8 MYAkb2+CpcAaNeJUcbaGBaNKda7Ja8Q2D1grm8FfjJlVFOVuN6FJu1IH2K9p+dsvtIRA qX+G0EDs2XFu71Gd+JrQVeeeYHg4rK+obkd3HdZdpVru1U7ppwgaNc5IAn5mHOgfxvFh C9W5LoMsTNKvVZ2PqyTE+wBLuk7tvr8n3FQOlHq5svFxldy5D1gdsC6cNE35vIxg91f/ g9taPH8LIVFaCBFG14lu0AK7a4MKvITA5Xp47HpzS9Q8l5g72frbiHTV8W9vQK4Pp174 W9ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bMUR5sD8O9rtk/7sKuRuzykcg31e/bLyabjcIq2Wv5E=; b=bhjq/maprzhvstCesBGvO7nN9+yNFGqA6XVlNDkaZaEs336F/4BWbk6leK1y87HLci 3WtIUH7X0oDtjOOVhGDpbwFEPYSwVrAeSvXpAf/kfS+uLhx5rSzEn6bXdd317NeELkcZ Ba6oVSiAoUhl0jiHTha+cttr49O7DmEZggY4VsUFx7FuuFnwNfTCDDRCbSODLC7ae2A/ IGCOPAqREvBLInPnrT+aGXBiTlwcfFpzmqzWeXTA+wd+IT/3xE6aqeN8E0fsscluDlPC edpSi6oUvg86/2/A8MHIvzllR8EgLBf4wiQEUK8W844RwyDo383kE/Cm/+P0vFGMg+oV CcSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DAeYtUL9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hg6-20020a1709072cc600b0078d4b2754b5si2284241ejc.332.2022.11.03.11.03.51; Thu, 03 Nov 2022 11:04:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DAeYtUL9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232129AbiKCSAh (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231961AbiKCR7a (ORCPT ); Thu, 3 Nov 2022 13:59:30 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B6D45F4B for ; Thu, 3 Nov 2022 10:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498362; x=1699034362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l5Os29/ppjad/9iy+qu+cEfFUnnSmf25B2n89ch0efI=; b=DAeYtUL9vdItvnMJPjl83NSlmemZNPvBiOiR/lizOfK8vTtYMZg5EB28 ZsnWksVBExo3/irx/9/xAWQwrXJk2C7NTY8CUGUS2Uf2FONu+PJRbASPO GAMMnbLWMOUM2ET35MNvJ8KN3/iwyYt0ozGCvtKqa0/FGP/u8WTdTPAdt FsB06I19pEmzTXZo1yhqF2rm+I360XSB4O60NQNlF4DBZBAbEmH8dMTZC 8vbhLOx8HSupW6xSeMnLJVNrkYZu2ZiaYFl/27zGqQS8mKv4x84orh4r/ BUCGgFh9hdYJY14QLOZy8e5fdqU3bHePJal372vtiXAZXWzBke3sg64yN w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476970" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476970" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762559" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762559" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 07/13] x86/microcode: Place siblings in NMI loop while update in progress Date: Thu, 3 Nov 2022 17:58:55 +0000 Message-Id: <20221103175901.164783-8-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499073261034302?= X-GMAIL-MSGID: =?utf-8?q?1748499073261034302?= Microcode updates affect the state of the running CPU. In the case of hyper-threads, the thread initiating the update is in a known state (performing wrmsr 0x79), but its HT sibling can be executing arbitrary instructions. If one of these arbitrary instruction is being patched by the update at the same time the sibling is trying to execute from it, its using microcode in an unstable state. Ensuring a rendezvous of all CPUs using stop_machine() ensures that siblings are not executing any random user space code, and stop_machine() also masks interrupts that can be masked. The ones that can still slip in are the exceptions. They are: NMI entry code and NMI handlers can also execute relatively arbitrary instructions. This is an effort to ensure NMI doesn't slip until the wrmsr has completed. == Solution: NMI prevention during update == Before the stop_machine() rendezvous, an NMI handler is registered. The handler is placed at the beginning of all other handlers. The siblings then kick themselves into NMI by doing a self NMI IPI. The handler does two things: - Informs the primary thread that it has entered the NMI handler. Only after all siblings of a core have entered NMI, the primary proceeds with wrmsr to update microcode. - It spins until the primary CPU has completed the wrmsr and informs the sibling to quit the NMI loop. Also an important thing to remember is the microcode requests for exclusive access to the core before performing an update. This effectively pulls the sibling into microcode control until the wrmsr has released exclusive access. Since the sibling is not executing any instructions while the wrmsr completes, no other exceptions will surface on the sibling CPU. Breakpoints can be another source that can lead do taking exceptions. But on NMI entry, the kernel seems to be save/clear/restore the breakpoint control register (DR7). local_db_save() and local_db_restore(). This effectively eliminates any breakpoints leading the sibling into uncontrolled execution. The algorithm is something like this: After stop_machine() all threads are executing __reload_late() hold_sibling_in_nmi() { /* Not a candidate for uCode NMI Sync */ if (cpu has no nmi_primary_ptr) return; update sibling reached NMI for primary to continue while (primary not done with update) wait; return; } exc_nmi:IDT() { .... hold_sibling_in_nmi(); ... } __reload_late() { entry_rendezvous(&late_cpus_in); if (this_cpu is first_cpu in the core) wait for core siblings to drop in NMI apply_microcode() set completion to release sibling from NMI else set sibling info to drop into NMI send self_IPI(NMI_VECTOR); wait_for_siblings: exit_rendezvous(&late_cpus_out); } reload_late() { register_nmi_handler() stop_machine(__reload_late); unregister_nmi_handler(); } Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/include/asm/microcode.h | 37 ++++++++++ arch/x86/kernel/cpu/microcode/core.c | 98 ++++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/nmi.c | 71 +++++++++++++++++++ arch/x86/kernel/nmi.c | 7 ++ arch/x86/kernel/cpu/microcode/Makefile | 1 + 5 files changed, 210 insertions(+), 4 deletions(-) create mode 100644 arch/x86/kernel/cpu/microcode/nmi.c diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index d5a58bde091c..ffb46f2b0354 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -6,6 +6,37 @@ #include #include +/* + * Although this is a per-cpu structure, both the primary and siblings use + * only the primary structure to communicate. + * All core siblings set an indication they all reached NMI handler. + * Once primary has completed the microcode update, sets core_done to + * release all core siblings out of NMI. + * + * num_core_cpus - Number of CPUs in the core. + * callin - Siblings set to inform primary once they reach NMI. + * core_done - Set by primary once microcode update has completed. + * failed - Set when there is a timeout situation during rendezvous + */ +struct core_rendez { + int num_core_cpus; + atomic_t callin; + atomic_t core_done; + atomic_t failed; +}; + +DECLARE_PER_CPU(struct core_rendez, core_sync); + +/* + * The following structure is only used by secondary. + * Sets the primary per_cpu variable to be found inside the NMI handler to + * indicate this CPU is supposed to drop into NMI. Its consulted in the + * NMI handler before entering the loop waiting for primary to finish the + * loading process. Once loading is complete the NMI handler clears this + * pointer. + */ +DECLARE_PER_CPU(struct core_rendez *, nmi_primary_ptr); + struct ucode_patch { struct list_head plist; void *data; /* Intel uses only this one */ @@ -135,4 +166,10 @@ static inline void reload_early_microcode(void) { } static inline void microcode_bsp_resume(void) { } #endif +#ifdef CONFIG_MICROCODE_LATE_LOADING +extern void hold_sibling_in_nmi(void); +#else +static inline void hold_sibling_in_nmi(void) { } +#endif + #endif /* _ASM_X86_MICROCODE_H */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index d41207e50ee6..6084a87ea8f3 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -39,6 +39,8 @@ #include #include #include +#include +#include #include "../cpu.h" @@ -380,6 +382,59 @@ static int __wait_for_cpus(atomic_t *t, long long timeout) return 0; } +/* + * This simply ensures that the self IPI with NMI to siblings is marked as + * handled. + */ +static int ucode_nmi_cb(unsigned int val, struct pt_regs *regs) +{ + return NMI_HANDLED; +} + +/* + * Primary thread waits for all siblings to report that they have enterered + * the NMI handler + */ +static int __wait_for_core_siblings(struct core_rendez *rendez) +{ + int num_sibs = rendez->num_core_cpus - 1; + unsigned long long timeout = NSEC_PER_MSEC; + atomic_t *t = &rendez->callin; + int cpu = smp_processor_id(); + + while (atomic_read(t) < num_sibs) { + cpu_relax(); + ndelay(SPINUNIT); + touch_nmi_watchdog(); + timeout -= SPINUNIT; + if (timeout < SPINUNIT) { + pr_err("CPU%d timedout waiting for siblings\n", cpu); + atomic_inc(&rendez->failed); + return 1; + } + } + return 0; +} + +static void prepare_for_nmi(void) +{ + int cpu, first_cpu; + struct core_rendez *pcpu_core; + + for_each_online_cpu(cpu) { + first_cpu = cpumask_first(topology_sibling_cpumask(cpu)); + if (cpu != first_cpu) + continue; + + pcpu_core = &per_cpu(core_sync, first_cpu); + pcpu_core->num_core_cpus = + cpumask_weight(topology_sibling_cpumask(cpu)); + atomic_set(&pcpu_core->callin, 0); + atomic_set(&pcpu_core->core_done, 0); + atomic_set(&pcpu_core->failed, 0); + } +} + /* * Returns: * < 0 - on error @@ -387,14 +442,15 @@ static int __wait_for_cpus(atomic_t *t, long long timeout) */ static int __reload_late(void *info) { - int cpu = smp_processor_id(); + int first_cpu, cpu = smp_processor_id(); + struct core_rendez *pcpu_core; enum ucode_state err; int ret = 0; /* * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. - * */ + */ if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) return -1; @@ -405,10 +461,32 @@ static int __reload_late(void *info) * loading attempts happen on multiple threads of an SMT core. See * below. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) + first_cpu = cpumask_first(topology_sibling_cpumask(cpu)); + pcpu_core = &per_cpu(core_sync, first_cpu); + + /* + * Set the CPUs that we should hold in NMI until the primary has + * completed the microcode update. + */ + if (first_cpu == cpu) { + /* + * Wait for all siblings to enter + * NMI before performing the update + */ + ret = __wait_for_core_siblings(pcpu_core); + if (ret || atomic_read(&pcpu_core->failed)) { + pr_err("CPU %d core lead timeout waiting for siblings\n", cpu); + ret = -1; + } + pr_debug("Primary CPU %d proceeding with update\n", cpu); err = microcode_ops->apply_microcode(cpu); - else + atomic_set(&pcpu_core->core_done, 1); + } else { + /* We set the per-cpu of sibling in this case */ + this_cpu_write(nmi_primary_ptr, pcpu_core); + apic->send_IPI_self(NMI_VECTOR); goto wait_for_siblings; + } if (err >= UCODE_NFOUND) { if (err == UCODE_ERROR) @@ -490,6 +568,15 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); + prepare_for_nmi(); + + ret = register_nmi_handler(NMI_LOCAL, ucode_nmi_cb, NMI_FLAG_FIRST, + "ucode_nmi"); + if (ret) { + pr_err("Unable to register NMI handler\n"); + goto done; + } + copy_cpu_caps(&info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) @@ -498,6 +585,9 @@ static int microcode_reload_late(void) pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); + unregister_nmi_handler(NMI_LOCAL, "ucode_nmi"); + +done: return ret; } diff --git a/arch/x86/kernel/cpu/microcode/nmi.c b/arch/x86/kernel/cpu/microcode/nmi.c new file mode 100644 index 000000000000..8899659cc5d6 --- /dev/null +++ b/arch/x86/kernel/cpu/microcode/nmi.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2022 Ashok Raj + * + * X86 CPU microcode update NMI handler. + * + */ + +#include +#include +#include +#include + +#include + +#define SPINUNIT 100 /* 100 nsec */ + +DEFINE_PER_CPU(struct core_rendez, core_sync); +DEFINE_PER_CPU(struct core_rendez *, nmi_primary_ptr); + +#define SPINUNIT 100 /* 100 nsec */ + +static void delay(int ms) +{ + unsigned long timeout = jiffies + ((ms * HZ) / 1000); + + while (time_before(jiffies, timeout)) + cpu_relax(); +} + +/* + * Siblings wait until microcode update is completed by the primary thread. + */ +static int __wait_for_update(atomic_t *t) +{ + unsigned long long timeout = NSEC_PER_MSEC; + + while (!arch_atomic_read(t)) { + cpu_relax(); + delay(1); + timeout -= SPINUNIT; + if (timeout < SPINUNIT) + return 1; + } + return 0; +} + +noinstr void hold_sibling_in_nmi(void) +{ + struct core_rendez *pcpu_core; + int ret = 0; + + pcpu_core = this_cpu_read(nmi_primary_ptr); + if (likely(!pcpu_core)) + return; + + /* + * Increment the callin to inform primary thread that the sibling + * has arrived and parked in the NMI handler + */ + arch_atomic_inc(&pcpu_core->callin); + + ret = __wait_for_update(&pcpu_core->core_done); + if (ret) + atomic_inc(&pcpu_core->failed); + + /* + * Clear the nmi_trap, so future NMI's won't be affected + */ + this_cpu_write(nmi_primary_ptr, NULL); +} diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index cec0bfa3bc04..619afeaef07c 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -505,6 +506,12 @@ DEFINE_IDTENTRY_RAW(exc_nmi) this_cpu_write(nmi_dr7, local_db_save()); + /* + * If microcodeupdate is in progress, check and hold the sibling in + * the NMI until primary has completed the update + */ + hold_sibling_in_nmi(); + irq_state = irqentry_nmi_enter(regs); inc_irq_stat(__nmi_count); diff --git a/arch/x86/kernel/cpu/microcode/Makefile b/arch/x86/kernel/cpu/microcode/Makefile index 34098d48c48f..e469990bba73 100644 --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -3,3 +3,4 @@ microcode-y := core.o obj-$(CONFIG_MICROCODE) += microcode.o microcode-$(CONFIG_MICROCODE_INTEL) += intel.o microcode-$(CONFIG_MICROCODE_AMD) += amd.o +microcode-$(CONFIG_MICROCODE_LATE_LOADING) += nmi.o From patchwork Thu Nov 3 17:58:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15067 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp684187wru; Thu, 3 Nov 2022 11:03:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6L7uEO5B6i6nwlX06O1v0KzAN5dAiYyWt/INwKL7x4tRkpLeI6Tizn+nVjkd06d1BBRpqi X-Received: by 2002:a17:90b:1bd2:b0:213:2d7:3162 with SMTP id oa18-20020a17090b1bd200b0021302d73162mr31820207pjb.91.1667498624638; Thu, 03 Nov 2022 11:03:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498624; cv=none; d=google.com; s=arc-20160816; b=Tp2bu0xLHjjr8hdyvRoKn2r4QMmJx9oSKkHk8ZiblW3EkQq9Flm2+cU5zlyuNkzULt qjRFXkMDi5khgOkM6LD9e6vmuvinscpI6Wmgm3O/e2oMR+eh4yTe9Kn+SmWun+cnPwmL ved34bUnww097FRS+vnG/VhnU/jJcYLqo/CWVfiSiE/Tcwj5amlT9GlfCqbl8iFkR8Vn WWo87Q9gQWaYAMnm/NXLSfzlOm/wyMk1dol1SWQKpBeqSHiYl3LxXDDSkQuCDLq5gjNj 8vqoZxGJucWsdYwDxkpxOINTWRnc/hF6DwUHOYsKcVGA0lELDYRCIQDRI8jIp3XXkBZH oW7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8vo5d4/69DGHvKHyq9fj89veEiD+jKq1OPZW9BTwcTs=; b=1HzJnZShaPalGBtUAOmBwM+XWExzgZBnnCvwgL2B+feFmdeiJ/f9rDMUm5WkLtPPnv JelzsCJ8KV2wRSZbW7HKSJQkZ3vw5Tr6b68UT0ujhY4NeAWS8ailxGKGF6+lrTF4AJTW KR3vVYg5O7KJPfUGsQdjh9d5rAnvWQSTMv7Fp3MzorPakKk/HunjEKeIR9EXy5ZUHqhq nzyoW5nz7JjjuDCfVeFZ96N00ULFUHORJMlMRBx8xVeLKsQ7/uQOmQU6rwhFrJbzfBy2 qTn6+q7e1Ibzx+p/UM+JkMv6nlMQ9hB3T2eJYq2xOUD1P96wbIMwUb3P+9jsd5XHrd4F X/8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LLMuadPU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t24-20020a634618000000b0046ff70b1cf3si1796006pga.463.2022.11.03.11.03.28; Thu, 03 Nov 2022 11:03:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LLMuadPU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232013AbiKCSAa (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232070AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B5F15F48 for ; Thu, 3 Nov 2022 10:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498362; x=1699034362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mK6qh3yJ3vr/2ZaLvzn6GOkotoEzPEIyO1PLPBrI3fk=; b=LLMuadPUnawCndMTQqgJceku9Kl57nmuAAYCV5IT8W3HlAfZvfe+ZtX7 6s5rci4S/N2UBod66MjupKWG+8O71OBHNa5ZH4voDZXv/jK/4zfMBS2oY xzeJ4dYipisAu9/PLD07ndN7a5bq4u44cTHigCHqkLWhn3kidg5JJUVt+ lsWFUcn16rOIqmcyf3X4MTIAruPlgVL5XXRcqqS0ltWBhIu49UX2fLdCE 09UjhKdo8EpoRHX98HUlP35qCElKytGC3Z55Ywhh/G5nqRKUQyCaSykIU UxybQhUHCr5hIO4IMir51GCG4xqV6sPPMrAOs7+qc9HVYdpus368vGF1J g==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476971" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476971" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762562" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762562" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 08/13] x86/mce: Warn of a microcode update is in progress when MCE arrives Date: Thu, 3 Nov 2022 17:58:56 +0000 Message-Id: <20221103175901.164783-9-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499037914837273?= X-GMAIL-MSGID: =?utf-8?q?1748499037914837273?= Due to the nature of microcode updates to long flow instructions, its possible if an MCE is taken when microcode update is in progress could be dangerous. There is nothing the kernel can do to mitigate safely. Drop some bread crumbs to note that a MCE happened while a microcode update is also in progress. Suggested-by: Boris Petkov Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/include/asm/microcode.h | 2 ++ arch/x86/kernel/cpu/mce/core.c | 5 +++++ arch/x86/kernel/cpu/microcode/core.c | 9 +++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index ffb46f2b0354..f16973fb7330 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -167,8 +167,10 @@ static inline void microcode_bsp_resume(void) { } #endif #ifdef CONFIG_MICROCODE_LATE_LOADING +extern int ucode_update_in_progress(void); extern void hold_sibling_in_nmi(void); #else +static inline int ucode_update_in_progress(void) { return 0; } static inline void hold_sibling_in_nmi(void) { } #endif diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2c8ec5c71712..67669686fab4 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -46,6 +46,7 @@ #include #include +#include #include #include #include @@ -1425,6 +1426,10 @@ noinstr void do_machine_check(struct pt_regs *regs) else if (unlikely(!mca_cfg.initialized)) return unexpected_machine_check(regs); + instrumentation_begin(); + if (ucode_update_in_progress()) + pr_warn("MCE triggered while microcode update is in progress\n"); + instrumentation_end(); if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov()) goto clear; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 6084a87ea8f3..6f59ffdf2881 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -327,6 +327,8 @@ void reload_early_microcode(void) static struct platform_device *microcode_pdev; #ifdef CONFIG_MICROCODE_LATE_LOADING +static int ucode_updating; + /* * Late loading dance. Why the heavy-handed stomp_machine effort? * @@ -556,6 +558,11 @@ static void microcode_check(struct cpuinfo_x86 *orig) pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); } +int ucode_update_in_progress(void) +{ + return ucode_updating; +} + /* * Reload microcode late on all CPUs. Wait for a sec until they * all gather together. @@ -578,7 +585,9 @@ static int microcode_reload_late(void) } copy_cpu_caps(&info); + ucode_updating = 1; ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + ucode_updating = 0; if (ret == 0) microcode_check(&info); From patchwork Thu Nov 3 17:58:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15070 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp684814wru; Thu, 3 Nov 2022 11:04:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4zQ7P5OmUz4Kc7t5AtdJwPPw8ttyhB/IedqE3ct32i2rub21CL5T1EfPbVAfjkMyVahtJP X-Received: by 2002:a17:907:a429:b0:7a6:a48b:5e52 with SMTP id sg41-20020a170907a42900b007a6a48b5e52mr29991842ejc.411.1667498677743; Thu, 03 Nov 2022 11:04:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498677; cv=none; d=google.com; s=arc-20160816; b=jYwM/DwluuXzaUE/4DfTSvrWlaawE+4JiUDiRbC6wGwGZLX3cpOxUtBh5Bv6y7Xszf QUeZY7bnkp97qL8o8uluI+wR3lzcbYpcqDT2EUZO0hdksur3PSc9mnsHYBZIBK/1RstR +1JC6EIuEbSB2HzfsmFsLOnBzy8lSCzW2kNpL9RKmLEjsjD6s+RuykTrspT1X4NzFFjJ 7AQBVhRykhiGM5SYoBLlMV0IY0i/8hsfLza3uSxt7OCpDCx5iee01FKrXNCaEisUzbjy EzeuhWa/7qthPsCMp2qOdVT+onCtsyxuD9OykeIJ2xoiWOFQL4GIKoeW7/zx6/UgKSrt mmbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=11CNIb8L/ocrMmOf5mRk74JKJq5oHm2kmXsiLsVK0NQ=; b=qQhaYH+2dGToelLP85tGXh9zGza+bTS3C+N0oPKG4z3qkBb+Ic3cR9eBhlJTB3FD/d jIFvV07Wu04GhNWpV8DXgRHVVeDlCfPe1+6TKRXboazLMJ6SGdHtFxdr+7M0gIw0Pbn2 5QDDK3Mvp+NtPxhcmVzPHIDTBxoqO3x7p1XDAv3LJRBLUT5PZeq4ywAJij5p2dtbccgx h/RzfXiM6O+jHAH08jBaKl7+UhDOu2OQOFJ+EnOLxv/iF3DIAwZ6UfQVENjnOSauPJhv pOkh1TTBBVzIucIuqmju8biVnQeK4xi4AOtHAlaYU0wbPxwUPAz3/7ImbsTKJocLh1K2 fZ5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MdAV8qxC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qw12-20020a1709066a0c00b0078db70cc9b8si1974942ejc.606.2022.11.03.11.04.12; Thu, 03 Nov 2022 11:04:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MdAV8qxC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231217AbiKCSAq (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231962AbiKCR7a (ORCPT ); Thu, 3 Nov 2022 13:59:30 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F15185FE5 for ; Thu, 3 Nov 2022 10:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498362; x=1699034362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bF+UOfIOr6mZm7+jXKRYrpF9ErB2atj/R0xUVsOO12A=; b=MdAV8qxCZkaqxWw08eNDBP3AJVhC6xVEUJxWMyqgjvMWNWI777zFn3ZT X8mnqSRu0Jvx/hwxh+pH2usyrvP6/iaUITaBqKvdxwoUhuOoz9QSJJEcl GzZOHQPpsvOv80tGPlAXty9hQWvJo8mSwYNlTvVLMUQlTKCAhczL2RHw+ XSzDfkgP+0pEd7wkP/QBm3N77HD3gdgaowF9bbySwEpUh0RVoTAGWLElf wDkJrD3B1v8KV7UKbuqP8i/x37i+wbCVyMLDy5Vp9b/GyZySBOYla3cXa kje14kPnaJx1wenz2if+OdOA2gYp6XupqDsnu80PxQNI0SueZRXTMwq1K g==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476973" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476973" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762565" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762565" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 09/13] x86/microcode/intel: Add minimum required revision to microcode header Date: Thu, 3 Nov 2022 17:58:57 +0000 Message-Id: <20221103175901.164783-10-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499093505926587?= X-GMAIL-MSGID: =?utf-8?q?1748499093505926587?= In general users don't have the necessary information to determine whether a late loading of a new microcode version has removed any feature (MSR, CPUID etc) between what is currently loaded and this new microcode. To address this issue, Intel has added a "minimum required version" field to a previously reserved field in the file header. Microcode updates should only be applied if the current microcode version is equal to, or greater than this minimum required version. Thomas made some suggestions[1] on how meta-data in the microcode file could provide Linux with information to decide if the new microcode is suitable candidate for late loading. But even the "simpler" option#1 requires a lot of metadata and corresponding kernel code to parse it. The proposal here is an even simpler option. Simply "OS visible features" such as CPUID and MSRs are the only two examples. The microcode must not change these OS visible features because they cause problems after late loading. When microcode changes features, microcode will change the min_rev to prevent such microcodes from being late loaded. Pseudo code for late loading is as follows: if header.min_required_id == 0 This is old format microcode, block late loading else if current_ucode_version < header.min_required_id Current version is too old, block late loading of this microcode. else OK to proceed with late loading. Any microcode that modifies the interface to an OS-visible feature will set the min_version to itself. This will enforce this microcode is not suitable for late loading unless the currently loaded revision is greater or equal to the new microcode affecting the change. The enforcement is not in hardware and limited to kernel loader enforcing the requirement. It is not required for early loading of microcode to enforce this requirement, since the new features are only evaluated after early loading in the boot process. Test cases covered: 1. With new kernel, attempting to load an older format microcode with the min_rev=0 should be blocked by kernel. [ 210.541802] Late loading denied: Microcode header does not specify a required min version. 2. New microcode with a non-zero min_rev in the header, but the specified min_rev is greater than what is currently loaded in the CPU should be blocked by kernel. 245.139828] microcode: Late loading denied: Current revision 0x8f685300 is too old to update, must be at 0xaa000050 version or higher. Use early loading instead. 3. New microcode with a min_rev < currently loaded should allow loading the microcode 4. Build initrd with microcode that has min_rev=0, or min_rev > currently loaded should permit early loading microcode from initrd. [1] https://lore.kernel.org/linux-kernel/alpine.DEB.2.21.1909062237580.1902@nanos.tec.linutronix.de/ Tested-by: William Xie Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/include/asm/microcode_intel.h | 4 +++- arch/x86/kernel/cpu/microcode/intel.c | 29 +++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h index 4c92cea7e4b5..bc893dd68b82 100644 --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -14,7 +14,9 @@ struct microcode_header_intel { unsigned int pf; unsigned int datasize; unsigned int totalsize; - unsigned int reserved[3]; + unsigned int reserved1; + unsigned int min_req_ver; + unsigned int reserved3; }; struct microcode_intel { diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 8ef04447fcf0..020d0feed3cc 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -163,13 +163,14 @@ static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigne intel_ucode_patch = p->data; } -static int microcode_sanity_check(void *mc, int print_err) +static int microcode_sanity_check(void *mc, int print_err, bool late_loading) { unsigned long total_size, data_size, ext_table_size; struct microcode_header_intel *mc_header = mc; struct extended_sigtable *ext_header = NULL; u32 sum, orig_sum, ext_sigcount = 0, i; struct extended_signature *ext_sig; + struct ucode_cpu_info uci; total_size = get_totalsize(mc_header); data_size = get_datasize(mc_header); @@ -240,6 +241,24 @@ static int microcode_sanity_check(void *mc, int print_err) return -EINVAL; } + /* + * When late-loading, enforce that the current revision loaded on + * the CPU is equal or greater than the value specified in the + * new microcode header + */ + if (late_loading) { + if (!mc_header->min_req_ver) { + pr_warn("Late loading denied: Microcode header does not specify a required min version\n"); + return -EINVAL; + } + intel_cpu_collect_info(&uci); + if (uci.cpu_sig.rev < mc_header->min_req_ver) { + pr_warn("Late loading denied: Current revision 0x%x too old to update, must be at 0x%x or higher. Use early loading instead\n", + uci.cpu_sig.rev, mc_header->min_req_ver); + return -EINVAL; + } + } + if (!ext_table_size) return 0; @@ -281,7 +300,7 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) mc_size = get_totalsize(mc_header); if (!mc_size || mc_size > size || - microcode_sanity_check(data, 0) < 0) + microcode_sanity_check(data, 0, false) < 0) break; size -= mc_size; @@ -838,7 +857,8 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) memcpy(mc, &mc_header, sizeof(mc_header)); data = mc + sizeof(mc_header); if (!copy_from_iter_full(data, data_size, iter) || - microcode_sanity_check(mc, 1) < 0) { + microcode_sanity_check(mc, 1, true) < 0) { + ret = UCODE_ERROR; break; } @@ -861,6 +881,9 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) return UCODE_ERROR; } + if (ret == UCODE_ERROR) + return ret; + if (!new_mc) return UCODE_NFOUND; From patchwork Thu Nov 3 17:58:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15071 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp684935wru; Thu, 3 Nov 2022 11:04:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7rk5FP0eFTWAOSaq8rNxUNh4jQTR15R1OoiQZE31o3nKv9E7mBEqDXNJHP/II7mZ6oOFN+ X-Received: by 2002:a17:907:1de0:b0:7a7:6a8:1e61 with SMTP id og32-20020a1709071de000b007a706a81e61mr29890463ejc.468.1667498687642; Thu, 03 Nov 2022 11:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498687; cv=none; d=google.com; s=arc-20160816; b=eYPZsad2wg8FI/YWeHm8sT/Hfc2a+kq2bEq4r+RTR0Pv9Jff+SVUF/3wTIvezrLUql W/bUxZK2Iq57Qq6woptZ1jbp7bgMENo4Ff9U3bJDRXfXyOLLtBjqDeJojJ/M1zM9wNCy uLmHMHDdF7gAEo+rguXmLYQeCyfY+j6Tp8m9GASG5kcuh+QgREHrrnIdY4w93k1SO+wX NJSBG2OjrSiRk9znRt/EbkAcG8ZKo3yvd7Fhzv4b/WU3JzoYOvnKEccp582nBq6M3lMb a6iSdK1xVjKkSaGG2mawPQH21YIG1fKFTy1mgfyWDQ97AWakL4k7PWVc16WkGLgPcbcZ 8GpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NmdHG7Dwmeq4lwFbG+wnt/icOtUev+jR0hOUMar++js=; b=cWVKW/ylSHUbRF7M+v+1HGi/Q+PFM+elCXAyiGUwi8B1M0D9xdRLL7px4U87U7dGW5 NNWDJYn7YaP/jLRmtvS/gWyCxOhYNirEokGbxjAVJfeTnT+zkYZj+pFM4kfAeJgna0nm ibUol3wccZiUOmgQC5WhMj9S/ieIMFcSfodVevZxjHa9Y6g7a47AKKWJ+8NcPIoeariX TDxoGtJGMf7mahwyLm3xeFIsCQuG+ad5ibFV6RG8BcdIasB0Em2PSi5Z1IW96Zw5lLcF 78F2ItsN9/BN5qAPWsgxqE91TtcxC4Uf/cHbkYbfuM/8HWT3NdBqvclvSsLvaL4FvTpL HUqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TpVF8ONV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oq19-20020a170906cc9300b007ada2ec1a28si1586427ejb.165.2022.11.03.11.04.22; Thu, 03 Nov 2022 11:04:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TpVF8ONV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232148AbiKCSA6 (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231774AbiKCR7b (ORCPT ); Thu, 3 Nov 2022 13:59:31 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2AB72BEB for ; Thu, 3 Nov 2022 10:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498363; x=1699034363; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R6mbf+XQukOLH0HwR/RFX95V03exlKMqldLbjsezTU0=; b=TpVF8ONV/NqmFCRuw1KRWTbXePZgr7Ls59h1x33l4riKVeW6K4X1mftW 0eCdMAXQwMwVfQGmb03lcBJee8WH5N1mYY7u8K3loZDd32lJX/4hs5XLF VEDULS+uTn936FBOfjPI8H6Ztw/9tEyJoPTdX9DrgfWnSVPq0leZ3EG4T eCrbAtQI4oRnkH+ghkdeh5FlMsD5jU4jSjPpMFsBUZziq4PeqBOxbpl9E Ow3ZNY/XqNj7IFZ6e7Zy04MDPShe60x4ME/uYoxqTOfkQrdIIi9BKucey TZiCwHtnKLa5ZjTl5rBdPJ70irkxXmi4AOkCrPXvqWAuxJ4UNDiMxcAgZ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476974" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476974" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762568" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762568" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 10/13] x86/microcode: Add a generic mechanism to declare support for minrev Date: Thu, 3 Nov 2022 17:58:58 +0000 Message-Id: <20221103175901.164783-11-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499104020671712?= X-GMAIL-MSGID: =?utf-8?q?1748499104020671712?= Intel microcode adds some meta-data to report a minimum required revision before this new microcode can be late-loaded. There are no generic mechanism to declare support for all vendors. Add generic support to microcode to declare support, so the tainting and late-loading can be permitted in those architectures that support reporting a minrev in some form. Late loading has added support for - New images declaring a required minimum base version before a late-load is performed. - Improved NMI handling during update to avoid sibling threads taking NMI's while primary is still not complete with the microcode update. With these changes, late-loading can be re-enabled. Tainting only happens on architectures that don't support minimum required version reporting. Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- v2: (Kai) Add missing initialization local variable minrev arch/x86/include/asm/microcode.h | 2 ++ arch/x86/kernel/cpu/microcode/core.c | 15 +++++++++++---- arch/x86/kernel/cpu/microcode/intel.c | 6 ++++++ arch/x86/Kconfig | 7 ++++--- 4 files changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index f16973fb7330..6286b4056792 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -64,6 +64,8 @@ enum ucode_state { }; struct microcode_ops { + int (*check_minrev) (void); + enum ucode_state (*request_microcode_fw) (int cpu, struct device *); void (*microcode_fini_cpu) (int cpu); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 6f59ffdf2881..17dba13d397d 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -607,6 +607,7 @@ static ssize_t reload_store(struct device *dev, enum ucode_state tmp_ret = UCODE_OK; int bsp = boot_cpu_data.cpu_index; unsigned long val; + int minrev = 0; ssize_t ret = 0; ret = kstrtoul(buf, 0, &val); @@ -622,13 +623,18 @@ static ssize_t reload_store(struct device *dev, if (ret) goto put; + if (microcode_ops->check_minrev) + minrev = microcode_ops->check_minrev(); + + if (!minrev) { + pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); + pr_err("You should switch to early loading, if possible.\n"); + } + tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) goto put; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); - mutex_lock(µcode_mutex); ret = microcode_reload_late(); mutex_unlock(µcode_mutex); @@ -639,7 +645,8 @@ static ssize_t reload_store(struct device *dev, if (ret == 0) ret = size; - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + if (!minrev) + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); return ret; } diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 020d0feed3cc..5d2ee76cd36c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -956,7 +956,13 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device) return ret; } +static int intel_check_minrev(void) +{ + return 1; +} + static struct microcode_ops microcode_intel_ops = { + .check_minrev = intel_check_minrev, .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_intel, diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6d1879ef933a..b53626bff5f7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1353,15 +1353,16 @@ config MICROCODE_AMD processors will be enabled. config MICROCODE_LATE_LOADING - bool "Late microcode loading (DANGEROUS)" - default n + bool "Late microcode loading" + default y depends on MICROCODE help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence of synchronizing all cores and SMT threads is one fragile dance which does not guarantee that cores might not softlock after the loading. Therefore, - use this at your own risk. Late loading taints the kernel too. + use this at your own risk. Late loading taints the kernel, if it + doesn't support a minimum required base version before an update. config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" From patchwork Thu Nov 3 17:58:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15062 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp682388wru; Thu, 3 Nov 2022 11:01:11 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6epKP+2GobUNj2s3nqw0vWe8KFMdNTMZ4/AGk9GwlQ0fJet/THCQv6zCeB7yAkdslwZ9vt X-Received: by 2002:a17:90b:48c3:b0:213:b5ad:742d with SMTP id li3-20020a17090b48c300b00213b5ad742dmr29024536pjb.172.1667498471305; Thu, 03 Nov 2022 11:01:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498471; cv=none; d=google.com; s=arc-20160816; b=fDyttUwaFoJaKZfoCdbT6Y6qc6dsOkSjumYbhr0MV2eM9rb9t9f8yCHACm/5gQsSjo c2r0n7FXxxXoUwt28sGKwz0qblx+sRrmKsXzimgVez8SVwJtVX0XXh/QZHFGLimrlUOu q4aIOrkWPN9AvBzLvDfsHPy4hkHKVIk0L1NUfyIqHuh5wsx5IGcim+JuZ7gwvZBe04nI RwBWIJW9gq35wKnX9uAuOqsqa0c7tfe72JriPxAWzmCSaUOe374BLbVFfujclj+a1277 gaLo3w62K/54Qgb/ws51cv73LFRtBx+l4v5amksHeFMrbxx0JtbjEJpGelh52/v67vIx rmGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BScW8Z8jKiCX3elbaE4+XJThI+jDX+M9RCvDbIrZ8/M=; b=gUAk3SCeE/wCY+STX0Q/OYFWF2hjp5iZXfd2FW9B1nZKAr3GeTi97xMLUeJb+NXtvG wxDemyvd2ykJNamk8VJBbCyM2F79P5YabQ4vg5+v+wu0LkbAvz2azLcX+YumSvp5HdCx rpE6KjrUGEySMj4Ia12XaYTg3o9MHkeprjSpJqT9TR+dUyV3hpzy2Fp00wvgqDT7G7fA lLKjjch26D6DR9l01ONKelPi2vuB4zbU7eTgqSxTlgo1ANkVo59piBA/0V5D2ZV7gCc7 IJ6r9Fb/Uo0dOYLGVCzpcZxF348yzJimN/sq+utIOnllurcVSzKEII1heLmrIkhv+YYq YlzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ar9go5MU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c14-20020a170902d48e00b001729146e418si1681680plg.388.2022.11.03.11.00.57; Thu, 03 Nov 2022 11:01:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ar9go5MU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbiKCSAC (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231942AbiKCR71 (ORCPT ); Thu, 3 Nov 2022 13:59:27 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD6EC219B for ; Thu, 3 Nov 2022 10:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498359; x=1699034359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0V5W1QoeZ7jgTpO6yb+rrh5iM/UlFsilbmyJNleFWWA=; b=ar9go5MU9n8Up/U4gf0nzQpEQzOMzRgdQfWwkvQgxEdfI0JCIxnUUh+y ytyrzLsBpQhk+CpOlxZCpfnMOdfZL8rK73Q0Gw4R26s6HWEh9F5KSDbZC gZzpY6o2B9fzkNua25EucdxRVJZ3kZHYcIQZOERvCGxmQWXvdl3JHuW9I pwr7pzHShrfILTGa5AebMSqo+zoBI5jErx1o86CxaYdSNWaeX46HnPdv4 n7SVpAzbPRHnU96ILYt6wwN1JHaCeJG6dtQwZRkb1IYts+qHzXf0ZjGa1 J1J3W28yKBeiEfTFSnMcEZ0ajZMJcK5uKyg34P6sKMLIfPcYZwAexKlD8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="310878483" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="310878483" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762571" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762571" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 11/13] x86/microcode/intel: Drop wbinvd() from microcode loading Date: Thu, 3 Nov 2022 17:58:59 +0000 Message-Id: <20221103175901.164783-12-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498877093192517?= X-GMAIL-MSGID: =?utf-8?q?1748498877093192517?= Some older processors had a bad interaction when updating microcode if the caches were dirty causing machine checks. The wbinvd() was added to mitigate that before performing microcode updates. Now that Linux checks for the minimum version before performing an update, those microcode revisions can't be loaded. Remove calls to wbinvd(). Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 5d2ee76cd36c..7086670da606 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -541,11 +541,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) } old_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -776,12 +771,6 @@ static enum ucode_state apply_microcode_intel(int cpu) if (!prev_rev) prev_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); From patchwork Thu Nov 3 17:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15066 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp683802wru; Thu, 3 Nov 2022 11:03:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7B152RRHIgwnbjX/6j994ObQQY3QfAnmfZrmlNvAxTDKCIXk5Fo1vKCms0iASrOS6nMtJc X-Received: by 2002:a63:e907:0:b0:46f:f7bb:b513 with SMTP id i7-20020a63e907000000b0046ff7bbb513mr11346964pgh.147.1667498592861; Thu, 03 Nov 2022 11:03:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498592; cv=none; d=google.com; s=arc-20160816; b=LbEX6Q3Me4YX0ISAljR9p7WzYEw/FdPM394M3B78MoYiBxeqqitsVf13Xur4mfE0kn PqhoI9Bu0ANdb3EQJA37BDNLIRCxHcn+1TK/GVGKvMpGm/fJevc780YSJeaEk63Skl/B p7Zd1C0Ai6A2eFnke+w+9XkYECASjYqvI45tvFGP0Sd9jrXxax7RdXsmCNkgEhE7hpg1 /dOW+3l3xw1xXhKvdZHbFJ1LCMT5CKpVFH8+Ei3B4O8ecHBeNlXSaFriPcHwuW8ui+av 7suw9S/L45/TybYtpgJ2NmNp1cn7boKL3ugFL3SRedTRIbgGFy7mL2oerOUpo20zizGP vnEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ik0pri6zGV1mRWDNnK3M8vaYIvhz7OIvr/WuXYsyja4=; b=koyYNWPlnxi5QDK/wKZuez7Nl9f4iMsausRG/J78p3O0IuvcTtSxlkf64QxTlJPXkh /KrthoGLkwRUUqgxzQ5RSY4SAT5truK0Zn1vrRx9mtpbzSE6DftkzhD19j+QRkfvLnNb kaGbeIP24SKqVcUpkb5hEUYuHVorPLtroHnHTWY7xELrrA+bgGV4Pv6C2kURohtk9iM9 Htj+73BzYG8PXL3ju5k53k7n26edcTi/bsuMysX7oZg/hI4vUurbBkMOvAkd54lk2Zu6 jyaGgy5y8G8uJilgb5B5xzZ7L2/ItJ8ubNE5vuAlgehBEuK/Ds+mnXdvI8fwaHaYOCzS Prrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=S0IhcWb8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t16-20020a170902e85000b00174eef66680si1664002plg.120.2022.11.03.11.02.56; Thu, 03 Nov 2022 11:03:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=S0IhcWb8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232049AbiKCSAU (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232059AbiKCR73 (ORCPT ); Thu, 3 Nov 2022 13:59:29 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAE662BE9 for ; Thu, 3 Nov 2022 10:59:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498360; x=1699034360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tprEQhizZvNJCMWGXO2qdM0qzd8PBoK3akX16cVKTX0=; b=S0IhcWb82g6gPmeGXgWVm8G8YpKbKEoNpaWSdjG0t4iuJSBLCTMZR7BM SHWCFga6P2Bajv0dM13PE2we5ZsZ7tdhhqMidPTZb82HS0dFPDIP4iHUz x/5/wDSZs2LzLXkOc2OscVPxoffkurZpmwCjpBA7z25pfZ2pgT9d3C6y5 lK32tE2D15+V+Jw+6GWfl75jOvgjo/JWNUWMXZrGc/AiCK2VGZ313hSGm StFKDdam9JUdvoYLOjZcoIIwpcOm9H9UEQHkUvGUeVxp7PDbbYW4LzE8S Z58ABG2ZendIBDnAlYQ1VXGQGBFQjhFvfIuGo6g87S8ZAnvbVbGVB3HbL Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="310878484" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="310878484" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762574" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762574" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 12/13] x86/microcode: Display revisions only when update is successful Date: Thu, 3 Nov 2022 17:59:00 +0000 Message-Id: <20221103175901.164783-13-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499004687637966?= X-GMAIL-MSGID: =?utf-8?q?1748499004687637966?= Display the update message only when its successful Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 17dba13d397d..a7d0cbbb2505 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -591,11 +591,11 @@ static int microcode_reload_late(void) if (ret == 0) microcode_check(&info); - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); - unregister_nmi_handler(NMI_LOCAL, "ucode_nmi"); + if (!ret) + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); done: return ret; } From patchwork Thu Nov 3 17:59:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 15069 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp684739wru; Thu, 3 Nov 2022 11:04:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7iGTPcusaDdBXUEK3Fmqb+Nb3KCM9yPlOlNxyYrZetdQnfWmsnKn+rU5jGAN4Z1mRPCuiT X-Received: by 2002:a17:903:32d1:b0:187:143f:4c5b with SMTP id i17-20020a17090332d100b00187143f4c5bmr26629847plr.54.1667498670231; Thu, 03 Nov 2022 11:04:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667498670; cv=none; d=google.com; s=arc-20160816; b=rGzWeTDC/l9/lGwooo1c57vPO7G0X1TN5VBMXTCpKoJXwc1SOwCgzNTkQsUnkhdU21 GVEGB0LqYK0wWlR1d75zaMRkafFrtD/UEmwsZiWZ2kMam3Xnrce7f+ymRw1L8+KEumtI rvbl84bNBDLywAgduNCMDM+PPTPCszWqsboxxDBV8tuVGpAUVpuqp03Y97Lfgg5xfW1W KKjTIh5MbQH5n6F8Nmjgi9dkI8sHnCZiCjKOYWogY7rVAZxliVPaQOOfY/fmHchMsxT2 GbBMOKU1JS+RwFJL9/7bQmHEgfS3U9p0dvJqF89lsSZYACQ7T+GwW/dL8ciQQqMeAunG MeaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JemHcj1oFOZhTEcbUIAakdURX4eIvOkeIrUFOpbCp9w=; b=QXpcvf/f545QOb1Tx+UjlU1FUMALC5XsK/sk8m7SQeZkVG76XebuHHpu0mfqoQgKXa o6q+YLZ36vndu5mHvs6hlOAwhw1398toTe29Lpxu427RowQ34MEOOkLpc39JihylBxpT NQP4laRxrz2tthhkmffVLVDnEQ8tevRrwqJfnfIhECPaIjhuRhJNZ5UI5smXbvBM+3VX DqCWdu8tkrJBYlus+FwRvBaGSlsyCpAISR7vexx6dfzLhGTpgXocKZLCCeB0pB9CzyEC CJOxTIelUC4oCdhhYyn8SaFx4WCGRZDqlDIOcEx+8dPgA9C1CEx0yfR3cNcT6dmqjEd+ 70mQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EPdtqU23; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u192-20020a6279c9000000b0056285c5a37asi1761641pfc.55.2022.11.03.11.04.16; Thu, 03 Nov 2022 11:04:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EPdtqU23; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232083AbiKCSAz (ORCPT + 99 others); Thu, 3 Nov 2022 14:00:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231625AbiKCR7b (ORCPT ); Thu, 3 Nov 2022 13:59:31 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2B1B60CE for ; Thu, 3 Nov 2022 10:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667498363; x=1699034363; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=99EX+KA4C5DAnZxHjIR5rQZoeQgiDfbcKnY78sWqUNw=; b=EPdtqU23Iur7VVr/x6qJUeCZIQFc4qTv4YYz6tiAFTKMpfAo7TOEt9PM kbcFKi5f9xcQPfRpDwzVDTU+sXXDce1acraUx5tIL+6YUFRPcR7QhLMrh yYHhDrjcnP+J6uW8GZQrmBBXqD5dKZEgZI8KFw0dXC8VGdIeN4t+PADYB yh+eFfluvw+DIESm8zxSujC9FfOpVQyCQ6D+P7XFIv5PHlIsZ573A+KTz lTJRrqdtrRadiEzoW2RyE+LVCVDsofIciRwCbdYW055ub/bh0jWcc3K4B CJe702jqRsP+5sA3LWsWA6RADQPwtaG0o3NjyxluABliZAOe9+2++oD6s Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="308476975" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="308476975" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10520"; a="809762577" X-IronPort-AV: E=Sophos;i="5.96,134,1665471600"; d="scan'208";a="809762577" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2022 10:59:18 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: "LKML Mailing List" , X86-kernel , Tony Luck , Dave Hansen , Arjan van de Ven , Andy Lutomirski , Jacon Jun Pan , Tom Lendacky , Kai Huang , Andrew Cooper , Ashok Raj Subject: [v2 13/13] x86/microcode/intel: Add ability to update microcode even if rev is unchanged Date: Thu, 3 Nov 2022 17:59:01 +0000 Message-Id: <20221103175901.164783-14-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221103175901.164783-1-ashok.raj@intel.com> References: <20221103175901.164783-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,PDS_OTHER_BAD_TLD, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748499085626199056?= X-GMAIL-MSGID: =?utf-8?q?1748499085626199056?= This comes in handy for testing without the need for a new microcode file. Default is OFF. It can be switched dynamically at run time via debugfs file /sys/kernel/debug/microcode/load_same. NOT_FOR_INCLUSION: Leave it to the discretion of Boris if its suitable for inclusion. It will at least serve to validate some parts of the series without the need for a new microcode, since it goes through all the renedezvous parts except not updating the microcode itself. Reviewed-by: Tony Luck Signed-off-by: Ashok Raj --- arch/x86/include/asm/microcode.h | 2 ++ arch/x86/kernel/cpu/microcode/amd.c | 2 +- arch/x86/kernel/cpu/microcode/core.c | 23 ++++++++++++++++++----- arch/x86/kernel/cpu/microcode/intel.c | 4 ++-- 4 files changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 6286b4056792..a356a6a5207e 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -47,6 +47,8 @@ struct ucode_patch { extern struct list_head microcode_cache; +extern bool ucode_load_same; + struct cpu_signature { unsigned int sig; unsigned int pf; diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index b103d5e5f447..802212e194b3 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -694,7 +694,7 @@ static enum ucode_state apply_microcode_amd(int cpu) rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); /* need to apply patch? */ - if (rev >= mc_amd->hdr.patch_id) { + if (rev >= mc_amd->hdr.patch_id && !ucode_load_same) { ret = UCODE_OK; goto out; } diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index a7d0cbbb2505..2d0cd8ca3ea2 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -48,6 +49,7 @@ static struct microcode_ops *microcode_ops; static bool dis_ucode_ldr = true; +bool ucode_load_same; bool initrd_gone; @@ -490,11 +492,12 @@ static int __reload_late(void *info) goto wait_for_siblings; } - if (err >= UCODE_NFOUND) { - if (err == UCODE_ERROR) + if (ret || err >= UCODE_NFOUND) { + if (err == UCODE_ERROR || + (err == UCODE_NFOUND && !ucode_load_same)) { pr_warn("Error reloading microcode on CPU %d\n", cpu); - - ret = -1; + ret = -1; + } } wait_for_siblings: @@ -632,9 +635,13 @@ static ssize_t reload_store(struct device *dev, } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); - if (tmp_ret != UCODE_NEW) + if (tmp_ret == UCODE_ERROR || + (tmp_ret != UCODE_NEW && !ucode_load_same)) goto put; + if (tmp_ret != UCODE_NEW) + pr_info("Force loading ucode\n"); + mutex_lock(µcode_mutex); ret = microcode_reload_late(); mutex_unlock(µcode_mutex); @@ -781,6 +788,7 @@ static const struct attribute_group cpu_root_microcode_group = { static int __init microcode_init(void) { struct cpuinfo_x86 *c = &boot_cpu_data; + static struct dentry *dentry_ucode; int error; if (dis_ucode_ldr) @@ -815,7 +823,12 @@ static int __init microcode_init(void) cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); + dentry_ucode = debugfs_create_dir("microcode", NULL); + debugfs_create_bool("load_same", 0644, dentry_ucode, &ucode_load_same); + pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); + pr_info("ucode_load_same is %s\n", + ucode_load_same ? "enabled" : "disabled"); return 0; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 7086670da606..08ba6e009d54 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -763,7 +763,7 @@ static enum ucode_state apply_microcode_intel(int cpu) * already. */ rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { + if (rev >= mc->hdr.rev && !ucode_load_same) { ret = UCODE_OK; goto out; } @@ -782,7 +782,7 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_ERROR; } - if (bsp && rev != prev_rev) { + if (bsp && (rev != prev_rev || ucode_load_same)) { pr_info("update 0x%x -> 0x%x, date = %04x-%02x-%02x\n", prev_rev, rev, mc->hdr.date & 0xffff,