From patchwork Thu Nov 3 17:47:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 15047 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp677879wru; Thu, 3 Nov 2022 10:51:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7/0ZrNkZVFucYy8+SVhJbH7uJXNvD77umUXv7vpKlC/PL+HcKZQNuIQwAGE7wi8m9EVCbX X-Received: by 2002:a05:6a00:2315:b0:56d:a084:a77d with SMTP id h21-20020a056a00231500b0056da084a77dmr18909405pfh.53.1667497867907; Thu, 03 Nov 2022 10:51:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667497867; cv=none; d=google.com; s=arc-20160816; b=Iv8F/H/RV1KSy52YBpP2jlEKpjMZBT0M29z2gJSnbpvdA5XGJygkU1fIX8ITMDMZVv 68rpO6rjriTS2vypeHr9NbroDwwbwffmp9wAVbg4k6moUQhPbPVfLPwE9b31zJWQdr6C mLiqR/MzxQiCIW7q5iAH4bUvj8AMKSb4/981icq6g06tfm/u9+lOzaaBhfeGiG3PGHdv 332HK6tPQ2m8UkRSBQqqHBfJQ62KwlxC9ZB5QwnIYxOUVv0mrZW6hCgnfcsyB88cU6PY 8nenp19VVC5DmqCPht86ThEeTukru9qJxRFLJbkKryGMmsU2pLO1fngoiNp5B0XXoPfT sYtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bfif87wg+UZ5LRcuTBAAJkNhHmkMh8GtayVffgUF4js=; b=EDJogjCpj5UyZTMeC0lrsryUdUCWSORYEu9JX/O1icxh/qG8pr+jzvLeFwyVe7R7do M3/1ZvHkLI67UwOoPMCa/qrH1fIzLBQEhjk1x2JRSddHDpTPTo3k0Ck/Q6XkbMNZs68O 9RYta1OvoHiN+I8yZraDOKT/sdE8KeHbSRWI28yh7dfrlCO+dv77t5+xeJugbYMbZfkS jgdXsUelFikoJ+XmxaFH17vNBoNc0vaPVCWsqj3b3Qh+ASprHHnmPeVQfv5hoczZrMbP 9RmPsiV39Cm/aGPnJ12mOoZts6/yd4NgO3wnbt26nTUG4lNq/xJs2LyNwaVUsE39uosV gy1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=r44Fg1pf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Thu, 3 Nov 2022 12:47:49 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A3Hlmq1090755; Thu, 3 Nov 2022 12:47:49 -0500 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v7 1/2] arm64: dts: ti: k3-j721e-main: Add dts nodes for EHRPWMs Date: Thu, 3 Nov 2022 23:17:42 +0530 Message-ID: <20221103174743.16827-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221103174743.16827-1-r-ravikumar@ti.com> References: <20221103174743.16827-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498244368588442?= X-GMAIL-MSGID: =?utf-8?q?1748498244368588442?= From: Vijay Pothukuchi Add dts nodes for 6 EHRPWM instances on SoC Signed-off-by: Vijay Pothukuchi Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 68 ++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5c4a0e28cde5..bc3146e24816 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -66,7 +66,73 @@ usb_serdes_mux: mux-controller@4000 { #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { From patchwork Thu Nov 3 17:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 15048 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp677946wru; Thu, 3 Nov 2022 10:51:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6CGXc81CF+X+yypZOH8kS1v/NZqKW9gUARgw4UXye/zKSuRPdLzeEtdINroRJdLmoVqQJA X-Received: by 2002:a17:90a:660d:b0:215:eee3:bb15 with SMTP id l13-20020a17090a660d00b00215eee3bb15mr4711511pjj.155.1667497876809; Thu, 03 Nov 2022 10:51:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667497876; cv=none; d=google.com; s=arc-20160816; b=B4Pxd39Qom29DUjHF9M6ZEAwlu+9EoD6KPhpNC6Q0tZxL2owG8y3hGkvbDMNRZttn1 u2UxOYQIFetNcKfhdrTgpGZ9zWEKFwUvUzscfMelyK0T1C5lyCqmffb3a9jL4XrD3VQ7 VV6c2/lmLC4JwmeNiY4otBEcPevT15yHew0y7PB0a4JfeqIfgeT8mmdKd1tysh3Vxh2I 9ULO4e4YUOsKsSFR6vjhEq+oXSsSfH1780nyku0JreE4YlRcKIL7ap2lRF4kfGhUi1Wp aUQ5968+UHwmaRa14ztLSGlGltycti75NVWtyLl1cxdj2IKN0Ra3XpeIaoJMgjkuOOBX bfGQ== ARC-Message-Signature: i=1; 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Thu, 3 Nov 2022 12:47:51 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A3HloMU018947; Thu, 3 Nov 2022 12:47:50 -0500 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v7 2/2] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Date: Thu, 3 Nov 2022 23:17:43 +0530 Message-ID: <20221103174743.16827-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221103174743.16827-1-r-ravikumar@ti.com> References: <20221103174743.16827-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748498253803877229?= X-GMAIL-MSGID: =?utf-8?q?1748498253803877229?= Add pinmux required to bring out i2c5 and gpios on 40 pin RPi header on sk board Signed-off-by: Sinthu Raja Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 78aa4aa4de57..4640d280c85c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -400,6 +400,47 @@ ekey_reset_pins_default: ekey-reset-pns-pins-default { J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; }; &wkup_pmx0 { @@ -600,6 +641,24 @@ i2c@1 { }; }; +&main_i2c5 { + /* Brought out on RPi Header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; + &main_gpio2 { status = "disabled"; };