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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d2-20020a1709064c4200b009935121ecd6si11446193ejw.644.2023.09.13.05.33.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 05:33:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1DB13853839 for ; Wed, 13 Sep 2023 12:32:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 742573858C31 for ; Wed, 13 Sep 2023 12:31:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 742573858C31 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1694608278t59ovxl4 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 13 Sep 2023 20:31:17 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: +ynUkgUhZJmQJ8amucva61ww26DTddkw4ABB9OyriEu+igAig1C+UY/s5/car NKdv1eIkIITFzDZaCnKAWzB9HHFz+ZKCxJI1BAUc+GCY6yOKrkMlbj8gl6IAbr5E6EN3S8n PJzNGL0s6QBxZgE+H42e/0o5eVdL3exgnQnvmsb9ImXoAOhfbFf+IUeLDD8m77Q3kxM1bh+ Rrq40mNfZkMPx3XtDz2y8+h+5+xlAVI+mU4vLLFsLTEyy/URQVApI59c8WJ89aGLiYJDLLF UrG5eZgvZAylQMzd35frfXBynsN0h061JGOKc5bkVESspm8hWzTRtAKFWTT696VYD24RMkE BwV03hc0PhoP05SJQztzRNORA5608Kml9jcKjzvMQYjdkUPdHE0vuiGwE4lyfjr3/vr5UAJ YYmgBViFP8s= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14492568302541415132 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode Date: Wed, 13 Sep 2023 20:31:17 +0800 Message-Id: <20230913123117.3580126-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776925694386305754 X-GMAIL-MSGID: 1776925694386305754 This patch cleanups redundant reduction patterns after Juzhe change vector mode from fixed-size to scalable-size. For example, whether it is zvl32b, zvl64b, zvl128b, RVVM1SI indicates that it occupies a vector register. Therefore, it is easy to map vector modes to LMUL1 vector modes with define_mode_attr without creating a separate pattern for each LMUL1 Mode. For example, this patch can combine four patterns (@pred_reduc_, @pred_reduc_ @pred_reduc_, @pred_reduc_) to a single pattern @pred_reduc_. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_reduction): Adjust call. * config/riscv/riscv-vector-builtins-bases.cc: Adjust call. * config/riscv/vector-iterators.md: New iterators and attrs. * config/riscv/vector.md (@pred_reduc_): Removed. (@pred_reduc_): Removed. (@pred_reduc_): Removed. (@pred_reduc_): Removed. (@pred_reduc_): Added. (@pred_widen_reduc_plus): Removed. (@pred_widen_reduc_plus): Removed. (@pred_widen_reduc_plus): Added. (@pred_widen_reduc_plus): Removed. (@pred_reduc_): Removed. (@pred_reduc_): Removed. (@pred_reduc_): Removed. (@pred_reduc_plus): Removed. (@pred_reduc_plus): Removed. (@pred_reduc_plus): Added. (@pred_reduc_plus): Removed. (@pred_widen_reduc_plus): Removed. (@pred_widen_reduc_plus): Removed. (@pred_widen_reduc_plus): Added. --- gcc/config/riscv/riscv-v.cc | 4 +- .../riscv/riscv-vector-builtins-bases.cc | 15 +- gcc/config/riscv/vector-iterators.md | 47 ++- gcc/config/riscv/vector.md | 369 +++--------------- 4 files changed, 101 insertions(+), 334 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 76e6094f45b..68b36d9dc4f 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3230,7 +3230,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) = code_for_pred_reduc_plus (type == reduction_type::UNORDERED ? UNSPEC_UNORDERED : UNSPEC_ORDERED, - vmode, m1_mode); + vmode); if (type == reduction_type::MASK_LEN_FOLD_LEFT) { rtx mask = ops[3]; @@ -3243,7 +3243,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) } else { - insn_code icode = code_for_pred_reduc (code, vmode, m1_mode); + insn_code icode = code_for_pred_reduc (code, vmode); emit_vlmax_insn (icode, REDUCE_OP, reduc_ops); } diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ee218a03017..c54ea6f0560 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1541,8 +1541,7 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn ( - code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ())); + return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ())); } }; @@ -1555,9 +1554,8 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC, - e.vector_mode (), - e.ret_mode ())); + return e.use_exact_insn ( + code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ())); } }; @@ -1576,7 +1574,7 @@ public: rtx expand (function_expander &e) const override { return e.use_exact_insn ( - code_for_pred_reduc_plus (UNSPEC, e.vector_mode (), e.ret_mode ())); + code_for_pred_reduc_plus (UNSPEC, e.vector_mode ())); } }; @@ -1594,9 +1592,8 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC, - e.vector_mode (), - e.ret_mode ())); + return e.use_exact_insn ( + code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ())); } }; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e70a9bc5c74..deb89cbcedc 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -671,6 +671,15 @@ RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") ]) +(define_mode_iterator VF_HS [ + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") + (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +]) + (define_mode_iterator V_VLSI_QHS [ RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") @@ -1237,32 +1246,32 @@ (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") ]) -(define_mode_iterator VQI_LMUL1 [ - RVVM1QI -]) +(define_mode_attr V_LMUL1 [ + (RVVM8QI "RVVM1QI") (RVVM4QI "RVVM1QI") (RVVM2QI "RVVM1QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVM1QI") (RVVMF4QI "RVVM1QI") (RVVMF8QI "RVVM1QI") -(define_mode_iterator VHI_LMUL1 [ - RVVM1HI -]) + (RVVM8HI "RVVM1HI") (RVVM4HI "RVVM1HI") (RVVM2HI "RVVM1HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVM1HI") (RVVMF4HI "RVVM1HI") -(define_mode_iterator VSI_LMUL1 [ - RVVM1SI -]) + (RVVM8SI "RVVM1SI") (RVVM4SI "RVVM1SI") (RVVM2SI "RVVM1SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVM1SI") -(define_mode_iterator VDI_LMUL1 [ - (RVVM1DI "TARGET_VECTOR_ELEN_64") -]) + (RVVM8DI "RVVM1DI") (RVVM4DI "RVVM1DI") (RVVM2DI "RVVM1DI") (RVVM1DI "RVVM1DI") -(define_mode_iterator VHF_LMUL1 [ - (RVVM1HF "TARGET_ZVFH") -]) + (RVVM8HF "RVVM1HF") (RVVM4HF "RVVM1HF") (RVVM2HF "RVVM1HF") (RVVM1HF "RVVM1HF") (RVVMF2HF "RVVM1HF") (RVVMF4HF "RVVM1HF") -(define_mode_iterator VSF_LMUL1 [ - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF") + + (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF") ]) -(define_mode_iterator VDF_LMUL1 [ - (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") +(define_mode_attr V_EXT_LMUL1 [ + (RVVM8QI "RVVM1HI") (RVVM4QI "RVVM1HI") (RVVM2QI "RVVM1HI") (RVVM1QI "RVVM1HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVM1HI") (RVVMF8QI "RVVM1HI") + + (RVVM8HI "RVVM1SI") (RVVM4HI "RVVM1SI") (RVVM2HI "RVVM1SI") (RVVM1HI "RVVM1SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVM1SI") + + (RVVM8SI "RVVM1DI") (RVVM4SI "RVVM1DI") (RVVM2SI "RVVM1DI") (RVVM1SI "RVVM1DI") (RVVMF2SI "RVVM1DI") + + (RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF") + + (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF") ]) (define_mode_attr VINDEX [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 58e659e5cd4..b6c8e63b0b2 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7725,265 +7725,78 @@ ;; - 14.4 Vector Widening Floating-Point Reduction Instructions ;; ------------------------------------------------------------------------------- -;; For reduction operations, we should have seperate patterns for -;; different types. For each type, we will cover MIN_VLEN == 32, MIN_VLEN == 64 -;; and the MIN_VLEN >= 128 from the well defined iterators. -;; Since reduction need LMUL = 1 scalar operand as the input operand -;; and they are different. - -;; Integer Reduction for QI -(define_insn "@pred_reduc_" - [(set (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VQI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VQI - (vec_duplicate:VQI - (vec_select: - (match_operand:VQI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VQI 3 "register_operand" " vr, vr")) - (match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] - "TARGET_VECTOR" - "vred.vs\t%0,%3,%4%p1" - [(set_attr "type" "vired") - (set_attr "mode" "")]) - -;; Integer Reduction for HI -(define_insn "@pred_reduc_" - [(set (match_operand:VHI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VHI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VHI - (vec_duplicate:VHI - (vec_select: - (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VHI 3 "register_operand" " vr, vr")) - (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] - "TARGET_VECTOR" - "vred.vs\t%0,%3,%4%p1" - [(set_attr "type" "vired") - (set_attr "mode" "")]) - -;; Integer Reduction for SI -(define_insn "@pred_reduc_" - [(set (match_operand:VSI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VSI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VSI - (vec_duplicate:VSI - (vec_select: - (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VSI 3 "register_operand" " vr, vr")) - (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] - "TARGET_VECTOR" - "vred.vs\t%0,%3,%4%p1" - [(set_attr "type" "vired") - (set_attr "mode" "")]) - -;; Integer Reduction for DI -(define_insn "@pred_reduc_" - [(set (match_operand:VDI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VDI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") +;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs) +(define_insn "@pred_reduc_" + [(set (match_operand: 0 "register_operand" "=vr, vr") + (unspec: + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VDI - (vec_duplicate:VDI + (any_reduc:VI + (vec_duplicate:VI (vec_select: - (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VDI 3 "register_operand" " vr, vr")) - (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] + (match_operand:VI 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") - (set_attr "mode" "")]) - -;; Integer Reduction Widen for QI, HI = QI op HI -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand:VHI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VHI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VQI 3 "register_operand" " vr, vr") - (match_operand:VHI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VHI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] - "TARGET_VECTOR" - "vwredsum.vs\t%0,%3,%4%p1" - [(set_attr "type" "viwred") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -;; Integer Reduction Widen for HI, SI = HI op SI -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand:VSI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VSI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") +;; Integer Reduction Sum Widen (vwredsum[u].vs) +(define_insn "@pred_widen_reduc_plus" + [(set (match_operand: 0 "register_operand" "=&vr,&vr") + (unspec: + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VHI 3 "register_operand" " vr, vr") - (match_operand:VSI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VSI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] + (match_operand:VI_QHS 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 2 "vector_merge_operand" " vu, 0")] WREDUC))] "TARGET_VECTOR" "vwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "viwred") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -;; Integer Reduction Widen for SI, DI = SI op DI -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand:VDI_LMUL1 0 "register_operand" "=&vr,&vr") - (unspec:VDI_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VSI 3 "register_operand" " vr, vr") - (match_operand:VDI_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VDI_LMUL1 2 "vector_merge_operand" " vu, 0")] WREDUC))] - "TARGET_VECTOR" - "vwredsum.vs\t%0,%3,%4%p1" - [(set_attr "type" "viwred") - (set_attr "mode" "")]) - -;; Float Reduction for HF -(define_insn "@pred_reduc_" - [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VHF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VHF - (vec_duplicate:VHF - (vec_select: - (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VHF 3 "register_operand" " vr, vr")) - (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] - "TARGET_VECTOR" - "vfred.vs\t%0,%3,%4%p1" - [(set_attr "type" "vfredu") - (set_attr "mode" "")]) - -;; Float Reduction for SF -(define_insn "@pred_reduc_" - [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VSF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VSF - (vec_duplicate:VSF - (vec_select: - (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VSF 3 "register_operand" " vr, vr")) - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] - "TARGET_VECTOR" - "vfred.vs\t%0,%3,%4%p1" - [(set_attr "type" "vfredu") - (set_attr "mode" "")]) - -;; Float Reduction for DF -(define_insn "@pred_reduc_" - [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VDF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") +;; Float Reduction (vfred(max|min).vs) +(define_insn "@pred_reduc_" + [(set (match_operand: 0 "register_operand" "=vr, vr") + (unspec: + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VDF - (vec_duplicate:VDF + (any_freduc:VF + (vec_duplicate:VF (vec_select: - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VDF 3 "register_operand" " vr, vr")) - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") - (set_attr "mode" "")]) - -;; Float Ordered Reduction Sum for HF -(define_insn "@pred_reduc_plus" - [(set (match_operand:VHF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VHF_LMUL1 - [(unspec:VHF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus:VHF - (vec_duplicate:VHF - (vec_select: - (match_operand:VHF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VHF 3 "register_operand" " vr, vr")) - (match_operand:VHF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] - "TARGET_VECTOR" - "vfredsum.vs\t%0,%3,%4%p1" - [(set_attr "type" "vfred") - (set_attr "mode" "") - (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + (set_attr "mode" "")]) -;; Float Ordered Reduction Sum for SF -(define_insn "@pred_reduc_plus" - [(set (match_operand:VSF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VSF_LMUL1 - [(unspec:VSF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") +;; Float Ordered Reduction Sum (vfred[ou]sum.vs) +(define_insn "@pred_reduc_plus" + [(set (match_operand: 0 "register_operand" "=vr,vr") + (unspec: + [(unspec: + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") @@ -7991,93 +7804,41 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus:VSF - (vec_duplicate:VSF + (plus:VF + (vec_duplicate:VF (vec_select: - (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VSF 3 "register_operand" " vr, vr")) - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") - (set_attr "mode" "") - (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) - -;; Float Ordered Reduction Sum for DF -(define_insn "@pred_reduc_plus" - [(set (match_operand:VDF_LMUL1 0 "register_operand" "=vr,vr") - (unspec:VDF_LMUL1 - [(unspec:VDF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus:VDF - (vec_duplicate:VDF - (vec_select: - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VDF 3 "register_operand" " vr, vr")) - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] - "TARGET_VECTOR" - "vfredsum.vs\t%0,%3,%4%p1" - [(set_attr "type" "vfred") - (set_attr "mode" "") - (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) - -;; Float Widen Reduction for HF, aka SF = HF op SF -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand:VSF_LMUL1 0 "register_operand" "=&vr, &vr") - (unspec:VSF_LMUL1 - [(unspec:VSF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VHF 3 "register_operand" " vr, vr") - (match_operand:VSF_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VSF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] - "TARGET_VECTOR" - "vfwredsum.vs\t%0,%3,%4%p1" - [(set_attr "type" "vfwred") - (set_attr "mode" "") + (set_attr "mode" "") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) -;; Float Widen Reduction for SF, aka DF = SF * DF -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand:VDF_LMUL1 0 "register_operand" "=&vr, &vr") - (unspec:VDF_LMUL1 - [(unspec:VDF_LMUL1 - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") +;; Float Widen Reduction Sum (vfwred[ou]sum.vs) +(define_insn "@pred_widen_reduc_plus" + [(set (match_operand: 0 "register_operand" "=&vr, &vr") + (unspec: + [(unspec: + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VSF 3 "register_operand" " vr, vr") - (match_operand:VDF_LMUL1 4 "register_operand" " vr, vr") - (match_operand:VDF_LMUL1 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] + (match_operand:VF_HS 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] "TARGET_VECTOR" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") - (set_attr "mode" "") + (set_attr "mode" "") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) From patchwork Wed Sep 13 12:31:37 2023 Content-Type: text/plain; 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[8.43.85.97]) by mx.google.com with ESMTPS id gt9-20020a1709072d8900b009ad8a9e0354si4041920ejc.390.2023.09.13.05.32.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 05:32:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DFC7A385559C for ; Wed, 13 Sep 2023 12:32:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id EB9943858C31 for ; Wed, 13 Sep 2023 12:31:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB9943858C31 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp81t1694608298txd7pjda Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 13 Sep 2023 20:31:37 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: RrZlkntZBfnHNeH75+hEljjMiM8/UZeyLvdKvCBpWz4ZcFiDExSfQLwGDln3O HiG4VFdZkXfcUWKdiloqy7OEEiKhD/UlwQhc06Rf6awQENgTn74kuR7Kjs+fNdOsYrJh05e KsDb+IfPtXwb2SqD4IatXlC4i1sWVU5lyIm3rlwQb2WrLZ30u1HBLYQBh2tSnBdxHp1b8af mNS+RutO0f0u/7LSC7SvpzQvMyU6zU0G/OO237ZP0wrm0nAcw+sUvbwloMb3HvGHShMXiC0 rTDGOQbFxcsPeRJu+myHlqg1hn+DJhU1wsNUQxay8iBP6eHiFOxFg+pJ2mJusO2VJe2cBcc WxGBckflWbzkEPnvmieBi4kykauHSK7gVaw3crtwm0YyLyXJPVmintSnggv8W9nNNatzF5D 1PGlqxO8iQiD/ODMCDnrQg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10878095668521093807 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns Date: Wed, 13 Sep 2023 20:31:37 +0800 Message-Id: <20230913123137.3580445-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776925647623673986 X-GMAIL-MSGID: 1776925647623673986 This patch adjust reduction patterns struct, change it from: (any_reduc:VI (vec_duplicate:VI (vec_select: (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) (match_operand:VI 3 "register_operand" " vr, vr")) to: (unspec: [ (match_operand:VI 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") ] ANY_REDUC) The reason for the change is that the semantics of the previous pattern is incorrect. GCC does not have a standard rtx code to express the reduction calculation process. It makes more sense to use UNSPEC. Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)), so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop and widen_freducop are redundant. gcc/ChangeLog: * config/riscv/autovec.md: Change rtx code to unspec. * config/riscv/riscv-protos.h (expand_reduction): Change prototype. * config/riscv/riscv-v.cc (expand_reduction): Change prototype. * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop): Removed. (class widen_freducop): Removed. * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs. * config/riscv/vector.md (@pred_reduc_): Change name. (@pred_): New name. (@pred_widen_reduc_plus): Change name. (@pred_reduc_plus): Change name. (@pred_widen_reduc_plus): Change name. --- gcc/config/riscv/autovec.md | 27 ++-- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 13 +- .../riscv/riscv-vector-builtins-bases.cc | 82 ++++-------- gcc/config/riscv/vector-iterators.md | 62 +++++++-- gcc/config/riscv/vector.md | 118 +++++++++--------- 6 files changed, 152 insertions(+), 152 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 4a6b8f8c939..16ac125f53f 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2091,7 +2091,7 @@ (match_operand:VI 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (mode)); DONE; }) @@ -2102,7 +2102,7 @@ { int prec = GET_MODE_PRECISION (mode); rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode); - riscv_vector::expand_reduction (SMAX, operands, min); + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min); DONE; }) @@ -2111,7 +2111,7 @@ (match_operand:VI 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX (mode)); DONE; }) @@ -2122,7 +2122,7 @@ { int prec = GET_MODE_PRECISION (mode); rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode); - riscv_vector::expand_reduction (SMIN, operands, max); + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max); DONE; }) @@ -2133,7 +2133,7 @@ { int prec = GET_MODE_PRECISION (mode); rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode); - riscv_vector::expand_reduction (UMIN, operands, max); + riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max); DONE; }) @@ -2142,7 +2142,7 @@ (match_operand:VI 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX (mode)); DONE; }) @@ -2151,7 +2151,7 @@ (match_operand:VI 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX (mode)); DONE; }) @@ -2160,7 +2160,7 @@ (match_operand:VI 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX (mode)); DONE; }) @@ -2178,7 +2178,8 @@ (match_operand:VF 1 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode)); + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands, + CONST0_RTX (mode)); DONE; }) @@ -2190,7 +2191,7 @@ REAL_VALUE_TYPE rv; real_inf (&rv, true); rtx f = const_double_from_real_value (rv, mode); - riscv_vector::expand_reduction (SMAX, operands, f); + riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, f); DONE; }) @@ -2202,7 +2203,7 @@ REAL_VALUE_TYPE rv; real_inf (&rv, false); rtx f = const_double_from_real_value (rv, mode); - riscv_vector::expand_reduction (SMIN, operands, f); + riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, f); DONE; }) @@ -2220,7 +2221,7 @@ (match_operand:VF 2 "register_operand")] "TARGET_VECTOR" { - riscv_vector::expand_reduction (PLUS, operands, + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands, operands[1], riscv_vector::reduction_type::FOLD_LEFT); DONE; @@ -2239,7 +2240,7 @@ if (rtx_equal_p (operands[4], const0_rtx)) emit_move_insn (operands[0], operands[1]); else - riscv_vector::expand_reduction (PLUS, operands, + riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands, operands[1], riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT); DONE; diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index d08d5dfeef4..44fa36c32ab 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -433,7 +433,7 @@ void expand_vec_cmp (rtx, rtx_code, rtx, rtx); bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); void expand_cond_len_unop (unsigned, rtx *); void expand_cond_len_binop (unsigned, rtx *); -void expand_reduction (rtx_code, rtx *, rtx, +void expand_reduction (unsigned, rtx *, rtx, reduction_type = reduction_type::UNORDERED); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 68b36d9dc4f..1bf5471beaf 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3208,7 +3208,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) /* Expand reduction operations. */ void -expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) +expand_reduction (unsigned unspec, rtx *ops, rtx init, reduction_type type) { rtx vector = type == reduction_type::UNORDERED ? ops[1] : ops[2]; machine_mode vmode = GET_MODE (vector); @@ -3224,13 +3224,10 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) rtx m1_tmp2 = gen_reg_rtx (m1_mode); rtx reduc_ops[] = {m1_tmp2, vector, m1_tmp}; - if (FLOAT_MODE_P (vmode) && code == PLUS) + if (unspec == UNSPEC_REDUC_SUM_ORDERED + || unspec == UNSPEC_REDUC_SUM_UNORDERED) { - insn_code icode - = code_for_pred_reduc_plus (type == reduction_type::UNORDERED - ? UNSPEC_UNORDERED - : UNSPEC_ORDERED, - vmode); + insn_code icode = code_for_pred (unspec, vmode); if (type == reduction_type::MASK_LEN_FOLD_LEFT) { rtx mask = ops[3]; @@ -3243,7 +3240,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, reduction_type type) } else { - insn_code icode = code_for_pred_reduc (code, vmode); + insn_code icode = code_for_pred (unspec, vmode); emit_vlmax_insn (icode, REDUCE_OP, reduc_ops); } diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index c54ea6f0560..ab12e130907 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1533,7 +1533,7 @@ public: }; /* Implements reduction instructions. */ -template +template class reducop : public function_base { public: @@ -1541,26 +1541,12 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ())); - } -}; - -/* Implements widen reduction instructions. */ -template -class widen_reducop : public function_base -{ -public: - bool apply_mask_policy_p () const override { return false; } - - rtx expand (function_expander &e) const override - { - return e.use_exact_insn ( - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ())); + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ())); } }; /* Implements floating-point reduction instructions. */ -template +template class freducop : public function_base { public: @@ -1573,27 +1559,7 @@ public: rtx expand (function_expander &e) const override { - return e.use_exact_insn ( - code_for_pred_reduc_plus (UNSPEC, e.vector_mode ())); - } -}; - -/* Implements widening floating-point reduction instructions. */ -template -class widen_freducop : public function_base -{ -public: - bool has_rounding_mode_operand_p () const override - { - return FRM_OP == HAS_FRM; - } - - bool apply_mask_policy_p () const override { return false; } - - rtx expand (function_expander &e) const override - { - return e.use_exact_insn ( - code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ())); + return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ())); } }; @@ -2281,26 +2247,26 @@ static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; static CONSTEXPR const vfncvt_f vfncvt_f_obj; static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj; static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj; -static CONSTEXPR const reducop vredsum_obj; -static CONSTEXPR const reducop vredmaxu_obj; -static CONSTEXPR const reducop vredmax_obj; -static CONSTEXPR const reducop vredminu_obj; -static CONSTEXPR const reducop vredmin_obj; -static CONSTEXPR const reducop vredand_obj; -static CONSTEXPR const reducop vredor_obj; -static CONSTEXPR const reducop vredxor_obj; -static CONSTEXPR const widen_reducop vwredsum_obj; -static CONSTEXPR const widen_reducop vwredsumu_obj; -static CONSTEXPR const freducop vfredusum_obj; -static CONSTEXPR const freducop vfredusum_frm_obj; -static CONSTEXPR const freducop vfredosum_obj; -static CONSTEXPR const freducop vfredosum_frm_obj; -static CONSTEXPR const reducop vfredmax_obj; -static CONSTEXPR const reducop vfredmin_obj; -static CONSTEXPR const widen_freducop vfwredusum_obj; -static CONSTEXPR const widen_freducop vfwredusum_frm_obj; -static CONSTEXPR const widen_freducop vfwredosum_obj; -static CONSTEXPR const widen_freducop vfwredosum_frm_obj; +static CONSTEXPR const reducop vredsum_obj; +static CONSTEXPR const reducop vredmaxu_obj; +static CONSTEXPR const reducop vredmax_obj; +static CONSTEXPR const reducop vredminu_obj; +static CONSTEXPR const reducop vredmin_obj; +static CONSTEXPR const reducop vredand_obj; +static CONSTEXPR const reducop vredor_obj; +static CONSTEXPR const reducop vredxor_obj; +static CONSTEXPR const reducop vwredsum_obj; +static CONSTEXPR const reducop vwredsumu_obj; +static CONSTEXPR const freducop vfredusum_obj; +static CONSTEXPR const freducop vfredusum_frm_obj; +static CONSTEXPR const freducop vfredosum_obj; +static CONSTEXPR const freducop vfredosum_frm_obj; +static CONSTEXPR const reducop vfredmax_obj; +static CONSTEXPR const reducop vfredmin_obj; +static CONSTEXPR const freducop vfwredusum_obj; +static CONSTEXPR const freducop vfwredusum_frm_obj; +static CONSTEXPR const freducop vfwredosum_obj; +static CONSTEXPR const freducop vfwredosum_frm_obj; static CONSTEXPR const vmv vmv_x_obj; static CONSTEXPR const vmv_s vmv_s_obj; static CONSTEXPR const vmv vfmv_f_obj; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index deb89cbcedc..c9d0a501910 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -67,9 +67,6 @@ UNSPEC_UNSIGNED_VFCVT UNSPEC_ROD - UNSPEC_REDUC - UNSPEC_WREDUC_SUM - UNSPEC_WREDUC_USUM UNSPEC_VSLIDEUP UNSPEC_VSLIDEDOWN UNSPEC_VSLIDE1UP @@ -83,6 +80,24 @@ UNSPEC_MODIFY_VL UNSPEC_VFFMA + + ;; Integer and Float Reduction + UNSPEC_REDUC + UNSPEC_REDUC_SUM + UNSPEC_REDUC_SUM_ORDERED + UNSPEC_REDUC_SUM_UNORDERED + UNSPEC_REDUC_MAXU + UNSPEC_REDUC_MAX + UNSPEC_REDUC_MINU + UNSPEC_REDUC_MIN + UNSPEC_REDUC_AND + UNSPEC_REDUC_OR + UNSPEC_REDUC_XOR + + UNSPEC_WREDUC_SUM + UNSPEC_WREDUC_SUMU + UNSPEC_WREDUC_SUM_ORDERED + UNSPEC_WREDUC_SUM_UNORDERED ]) (define_c_enum "unspecv" [ @@ -1274,6 +1289,36 @@ (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF") ]) +(define_int_iterator ANY_REDUC [ + UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU + UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR +]) + +(define_int_iterator ANY_WREDUC [ + UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU +]) + +(define_int_iterator ANY_FREDUC [ + UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN +]) + +(define_int_iterator ANY_FREDUC_SUM [ + UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED +]) + +(define_int_iterator ANY_FWREDUC_SUM [ + UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED +]) + +(define_int_attr reduc_op [ + (UNSPEC_REDUC_SUM "redsum") + (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum") + (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin") + (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor") + (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu") + (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum") +]) + (define_mode_attr VINDEX [ (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI") @@ -2271,8 +2316,6 @@ (RVVM2DF "vector_gs_scale_operand_64") (RVVM1DF "vector_gs_scale_operand_64") ]) -(define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM]) - (define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED]) (define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU]) @@ -2301,12 +2344,13 @@ (define_int_attr order [ (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u") + (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u") + (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u") ]) (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su") (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u") - (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u") - (UNSPEC_WREDUC_SUM "") (UNSPEC_WREDUC_USUM "u")]) + (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")]) (define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd") (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub") (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl") @@ -2392,10 +2436,6 @@ (define_code_iterator any_fix [fix unsigned_fix]) (define_code_iterator any_float [float unsigned_float]) -(define_code_iterator any_reduc [plus umax smax umin smin and ior xor]) -(define_code_iterator any_freduc [smax smin]) -(define_code_attr reduc [(plus "sum") (umax "maxu") (smax "max") (umin "minu") - (smin "min") (and "and") (ior "or") (xor "xor")]) (define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")]) (define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b6c8e63b0b2..3dd54509315 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7726,7 +7726,7 @@ ;; ------------------------------------------------------------------------------- ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs) -(define_insn "@pred_reduc_" +(define_insn "@pred_" [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: @@ -7736,39 +7736,39 @@ (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_reduc:VI - (vec_duplicate:VI - (vec_select: - (match_operand: 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VI 3 "register_operand" " vr, vr")) + (unspec: [ + (match_operand:VI 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + ] ANY_REDUC) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" - "vred.vs\t%0,%3,%4%p1" + "v.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) -;; Integer Reduction Sum Widen (vwredsum[u].vs) -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand: 0 "register_operand" "=&vr,&vr") +;; Integer Widen Reduction Sum (vwredsum[u].vs) +(define_insn "@pred_" + [(set (match_operand: 0 "register_operand" "=&vr,&vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:VI_QHS 3 "register_operand" " vr, vr") - (match_operand: 4 "register_operand" " vr, vr") - (match_operand: 2 "vector_merge_operand" " vu, 0")] WREDUC))] + (unspec: [ + (match_operand:VI_QHS 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + ] ANY_WREDUC) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" - "vwredsum.vs\t%0,%3,%4%p1" + "v.vs\t%0,%3,%4%p1" [(set_attr "type" "viwred") (set_attr "mode" "")]) ;; Float Reduction (vfred(max|min).vs) -(define_insn "@pred_reduc_" +(define_insn "@pred_" [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: @@ -7778,65 +7778,61 @@ (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_freduc:VF - (vec_duplicate:VF - (vec_select: - (match_operand: 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr")) + (unspec: [ + (match_operand:VF 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + ] ANY_FREDUC) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" - "vfred.vs\t%0,%3,%4%p1" + "vf.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) -;; Float Ordered Reduction Sum (vfred[ou]sum.vs) -(define_insn "@pred_reduc_plus" +;; Float Reduction Sum (vfred[ou]sum.vs) +(define_insn "@pred_" [(set (match_operand: 0 "register_operand" "=vr,vr") (unspec: - [(unspec: - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (plus:VF - (vec_duplicate:VF - (vec_select: - (match_operand: 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (unspec: [ + (match_operand:VF 3 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr, vr") + ] ANY_FREDUC_SUM) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" - "vfredsum.vs\t%0,%3,%4%p1" + "vf.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) ;; Float Widen Reduction Sum (vfwred[ou]sum.vs) -(define_insn "@pred_widen_reduc_plus" - [(set (match_operand: 0 "register_operand" "=&vr, &vr") +(define_insn "@pred_" + [(set (match_operand: 0 "register_operand" "=&vr, &vr") (unspec: - [(unspec: - [(unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + [(unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (unspec: [ (match_operand:VF_HS 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") - (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))] + ] ANY_FWREDUC_SUM) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" - "vfwredsum.vs\t%0,%3,%4%p1" + "vf.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") (set_attr "mode" "") (set (attr "frm_mode")