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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f16-20020a056402195000b0052fc773a47bsi970142edz.690.2023.09.12.23.07.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 23:07:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kUbRuIm1; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E93A5385DC17 for ; Wed, 13 Sep 2023 06:07:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E93A5385DC17 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694585240; bh=HMVMaP3f2W4cS+piqGUppifeHdMZlL/NTPxap2J8qv8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=kUbRuIm1CTcdZLWRwJ25xe26u7lGLx72l4M7GscIVqRw6JvH3cFRgr/L/DopQRe/U g2A9jKa32+X09LHxbcBuGgjjZ/NVcCZ8QSYP9el99DRejGJP+NaipbZOnnOtLIeCI8 NptKxnr9JO8pKvmY9bt/j7BxuQ2XFYrSzJv+atkM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 725EB3858281 for ; Wed, 13 Sep 2023 06:06:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 725EB3858281 X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="358848223" X-IronPort-AV: E=Sophos;i="6.02,142,1688454000"; d="scan'208";a="358848223" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2023 23:06:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="917705862" X-IronPort-AV: E=Sophos;i="6.02,142,1688454000"; d="scan'208";a="917705862" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 12 Sep 2023 23:06:32 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 12EA8100568B; Wed, 13 Sep 2023 14:06:32 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit Date: Wed, 13 Sep 2023 14:06:30 +0800 Message-Id: <20230913060630.3930824-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776901416414665866 X-GMAIL-MSGID: 1776901416414665866 From: Pan Li When the mode switching from NONE to CALL, we will restore the frm but lack some check if we have static frm insn in cfun. This patch would like to fix this by adding static frm insn check. gcc/ChangeLog: * PR target/111362 * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix. gcc/testsuite/ChangeLog: * PR target/111362 * gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 2 +- .../gcc.target/riscv/rvv/base/no-honor-frm-1.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9d04ddd69e0..762937b0e37 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode) rtx frm = gen_int_mode (mode, SImode); if (mode == riscv_vector::FRM_DYN_CALL - && prev_mode != riscv_vector::FRM_DYN) + && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun)) /* No need to emit when prev mode is DYN already. */ emit_insn (gen_fsrmsi_restore_volatile (backup_reg)); else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c new file mode 100644 index 00000000000..b2e0f217bfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +void foo (void) { + for (unsigned i = 0; i < sizeof(foo); i++) + __builtin_printf("%d", i); +} + +/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */ +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */