From patchwork Wed Sep 6 14:28:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 137583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ab0a:0:b0:3f2:4152:657d with SMTP id m10csp2349421vqo; Wed, 6 Sep 2023 07:28:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4s1TEBNPfdBjrFjpRxPEc7LOGR73nbIxnstWK8O7UdBDAeQmjgts0/S6AnL99N8wd3HKF X-Received: by 2002:a17:906:8a74:b0:9a5:bcea:a53a with SMTP id hy20-20020a1709068a7400b009a5bceaa53amr2284415ejc.33.1694010523665; Wed, 06 Sep 2023 07:28:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694010523; cv=none; d=google.com; s=arc-20160816; b=YHMFvHalFKWVnR6EDdwYM4A1MxyQcHYrVSkbQni1s6RR9agtLH1iWMuX6S4gmp6BWs aSHr9QfU8hwNYSPITN/n2vb4O0KXrhA5tMqP+x+mXdBChgnEn7r/ytWxjSX1SVOrLY19 PFAFEmq+3vZlZxnwYtJhBFvUqrpsCMI1xetKSgN9/NcIn/H1isJAhHIlq/7Xrgn9ssL0 zydsh9uLlPJgLwGljYO91dC9+oZQqM9p3tAUqDHcEWp6aWmu08f2XXzjHM6tqHhUtT3v IKy8MOvYik/UF0b3G0jIRvJo/GO9VGKfyoCdlLD97OVjurr8mypZDOOJZQQt+u510Uxv ig7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:to :from:dmarc-filter:delivered-to; bh=twwHSV0yyoEQAMSh55EWbgJt1wZEy42st701IEmTpCM=; fh=arl273cIQBNH1P6XLxHQvF0scgitfd773vOV+bwQx3o=; b=WV9K+OWNap8mwLdG47AxuZ82v8f+Qx19EIZR7grPh3CuNNerg0eJCggvF6DvdYWPf5 kFf5yuBxmkYoTW80Zvq3nYSo8WPqjrdpKS0eVdnHXm6np9j+5cy/XfvjhUUKCuL4iRnI bGZzAO+6WLB2LYWyJ5kEaGrvn0/L9u1Pi3LA+rkZVTlWit7wX0YFxZ617DLNzmEaOxDg qADz62ghYYnOomtjTl+aaBNojUUXAmZpV7FvT4kY+YxuGv1JOkyOLjTBBWJvAeUMqX2f S0+Vm6kWCjtKFO+stOy7u+VdSMrtQ6WGfYLKf7AYmv5OwbqX/gyB28IFvwencti0YSpQ btnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h23-20020a1709063c1700b00997eac101casi9017127ejg.509.2023.09.06.07.28.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 07:28:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 763773857706 for ; Wed, 6 Sep 2023 14:28:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 5D12D3858401 for ; Wed, 6 Sep 2023 14:28:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5D12D3858401 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp77t1694010485tkye1y8v Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 06 Sep 2023 22:28:04 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: cBG5oJqo1Ozgw467jRTtKEt1XjnDJ2bG3aoQNMBRjAYVKILqhq9oSrE7g6Vit 9EL63duvF80bfMDViCqhZCQU3OiK9PfqAKxBCkjEPZvErSLiR3cZmSklhbVOr2Ux8Bi7y6C O4U70b2zHoqCrRcuj34QoeeMvxe9v1or/ya9OHhUoAd0gtGOf9ys8lZpBliQX+6So3/ni35 0NFIELHtljD3aPv6S53RSBCjQqlEtWjHK94jz8LyEIemIo8r0Ibz3Lt94tpXggRfyuiahL1 nXyvWZGSBziggexpbloHfA/iun1PyC+6NCdyhfem+0PBToxOdPPA5F2M0jQdc4mst+FWlAN atkOmWsThdV4i/cdpQLXpmqQU8/JhuRNcybBn+OUcBl8Lry/u5b7Lk4LOBE4yQZR0HnmPur 96dW6xgqDmrYhRqUAwyquQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6968390070582531543 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [Committed V2] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] Date: Wed, 6 Sep 2023 22:28:03 +0800 Message-Id: <20230906142803.499510-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776298778573341005 X-GMAIL-MSGID: 1776298778573341005 This patch fix incorrect mode tieable between DI and V2SI which cause ICE in RA. PR target/111296 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode tieable for RVV modes. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: New test. --- gcc/config/riscv/riscv.cc | 5 +++++ .../g++.target/riscv/rvv/base/pr111296.C | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 228515acc1f..a3d3389e7e2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7648,6 +7648,11 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) static bool riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) { + /* We don't allow different REG_CLASS modes tieable since it + will cause ICE in register allocation (RA). + E.g. V2SI and DI are not tieable. */ + if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2)) + return false; return (mode1 == mode2 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT && GET_MODE_CLASS (mode2) == MODE_FLOAT)); diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C new file mode 100644 index 00000000000..6eb14fd83a8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */ + +struct a +{ + int b; + int c; +}; +int d; +a +e () +{ + a f; + int g = d - 1, h = d / 2 - 1; + f.b = g; + f.c = h; + return f; +}