From patchwork Tue Sep 5 09:08:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 137493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ab0a:0:b0:3f2:4152:657d with SMTP id m10csp1555831vqo; Tue, 5 Sep 2023 02:10:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG9p24sTyLbHbk+ZeD4Mbjv7QBo49oNfNlPYi5YSDv8tY1udmHUlvGuRE+3cRoV/C/20BMU X-Received: by 2002:a17:906:74d2:b0:9a1:d1a0:41ad with SMTP id z18-20020a17090674d200b009a1d1a041admr13748550ejl.21.1693905057766; Tue, 05 Sep 2023 02:10:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693905057; cv=none; d=google.com; s=arc-20160816; b=wDFXeBc+czuvDlO46qHwBv4lzxZOX8KSwI6J/n5xBJqlWxkOASE5u63ma9gwHQssUQ hZaiyRUVeDMLCBhTJbfSqLBbJ2mttDjvreJTyeyG2dXdK3ytextnwq2t/Bx2kUb0t3Ll bq8LkFY/85bK/xy3qN6mY22SJIw/jFnmlYFT4ZlmjglApiKDqL8CAwBw6J9fswlqVQdD GEwtwryONyP9bJiS6cW2J2UE/gyJ6O0VPfmT0iaSoWo9UihEDp8aRNyvpzSwVNwmY3L6 Cc+rht301FnJMGKTmLYyLCNsz6GK2GjCgMkeqBKqRsDswkfdYTJBPMDHZIee+ybswga9 DPcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=xjAIHpsr87RT+TnqyzhrAXnOgLKUNhnI/rybZNfG4lI=; fh=lMz0tc6bjmUz1Gwj2ppdH/A+guv79ykg2fc+XnZhGVU=; b=Ld1grdm7uk+KNZOXT/wf/2CJwbfoJ2Q082v+WNs2RHpQUJRg2Gf+TKhoV9hmTKFhem K0o1de60pwyuJ65wq2hyuc+hJGNmVl1J9gOTBuT0Ov177ToFLyX4U/f+fv57b3LEiLuP wDd0SQSPX/GmMtl8ufeolhgqg7r6mw/xNlmbxV2xSvlb1PxUAyt02RFsJQI2aRJsyKSO ZZXtYWe4VeEMXP/StZu/wQA3j0LC191tbwkpz2aC3R9AXS8cYOVqOTBFibSGpuhW3lRe Zj0dXU03eqYhi0n1Q55RMsc+bGVjzzvnWnV4B6dxZO9OVx9oZ1JWulTZMCvD6KySHtkd hMpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=VO6Gien3; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id i9-20020a1709061cc900b00992d0de8760si7319550ejh.911.2023.09.05.02.10.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 02:10:57 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=VO6Gien3; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F36DF3853570 for ; Tue, 5 Sep 2023 09:10:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F36DF3853570 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693905007; bh=xjAIHpsr87RT+TnqyzhrAXnOgLKUNhnI/rybZNfG4lI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=VO6Gien3Fk4e1QAHEss/Wbc87bdEL+eg+2L8yypAgOxV9Ng0dtKC4PhwqRGJ/If0Y bG+x/a8U0GdT1p7cCriK0nS/KuZTN4WYSertYJrgiyFfvJzijIqofz9YG2fo8tf9Sb k0fF1NlcdcARVfGDwhXHPtLAslrTRs9XPBL8HG8w= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 8D59D3857721; Tue, 5 Sep 2023 09:08:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D59D3857721 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 842A7300089; Tue, 5 Sep 2023 09:08:56 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 1/3] RISC-V: Remove RV64E conflict Date: Tue, 5 Sep 2023 09:08:35 +0000 Message-ID: <3d3c4716e1524875ae356f6d7be47e3c32f68f31.1693904909.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772357713453272838 X-GMAIL-MSGID: 1776188189344388062 From: Tsukasa OI Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed. --- bfd/elfxx-riscv.c | 7 ------- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 --- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- 3 files changed, 12 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e642a05fe5b8..4553075735f8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1946,13 +1946,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) int xlen = *rps->xlen; bool no_conflict = true; - if (riscv_lookup_subset (rps->subset_list, "e", &subset) - && xlen > 32) - { - rps->error_handler - (_("rv%d does not support the `e' extension"), xlen); - no_conflict = false; - } if (riscv_subset_supports (rps, "e") && riscv_subset_supports (rps, "h")) { diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d deleted file mode 100644 index cfe085ab21aa..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv64e -#source: empty.s -#error_output: march-fail-base-02.l diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l deleted file mode 100644 index 52fee96af368..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.l +++ /dev/null @@ -1,2 +0,0 @@ -.*Assembler messages: -.*Error: rv64 does not support the `e' extension From patchwork Tue Sep 5 09:08:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 137491 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ab0a:0:b0:3f2:4152:657d with SMTP id m10csp1554806vqo; Tue, 5 Sep 2023 02:09:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFBdJeKCjGHnvTashPBuNxlI8up5tyWxZMhFJ2fj9vm6FqltdlPDepLBBdn6qGd8I1977IW X-Received: by 2002:a17:906:1010:b0:99d:f6e9:1cf8 with SMTP id 16-20020a170906101000b0099df6e91cf8mr8777145ejm.20.1693904975101; Tue, 05 Sep 2023 02:09:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693904975; cv=none; d=google.com; s=arc-20160816; b=VlO1ibZwifTVvg1o0ALNSKsYBeonk60EmGEQ+2QWxthRqHsdmtPO6NxDirtuLfDagJ 0CWQC8+SpLxMZI5x0+4o4CspaxZjeepRk8SbxEUYqATk+cWLCizRbWsqmJJMvqFXQeV2 v3iHa++578OFwh/A9Bcu3Gz2rg11G2beIN89n+wv+LEeBEcW4yXyGFFu9LmUL5rz2qj0 OPMZOpCQWmUZQKGTv7oVHphdIOc18EksXCiR25kHq7niIXqBP+38cQAGm9k4GewFVcg8 cCP1WrVdZobASwkPB0lWHAhrUeinLe9mhi65msbAKcUltrEKAikpVEhJQk3RZJljHmuN +goA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=jlI6m0er38GZscTM8fcr/N21EDMxUlgYejM66hhfzfI=; fh=lMz0tc6bjmUz1Gwj2ppdH/A+guv79ykg2fc+XnZhGVU=; b=vRyL+xKXuha4LzmQX176tKVUJFEPOwTbSWiKw57LQd3K7geoXejZiEoqkNHJN1mMzz 7YFPAi+YMhGR1WMwpMHBqzhe4G4qQemdZ0lH5UG/TPVHcGPGf/EqFCjufOOWzEa9TlxV vnr64AJSDT152kx9N/DPWltldxwZdlSfDgjUdSPVHmuErXODpbxuLcgqKu6h/xJIARh/ 8nlKxICjpUoXp8VkakRaf312sa3FI9xxK/RWkAsJS6u9SbobYkhsHbEpVv9W1KoVEO+c mwi/Cfuih/Gwm1I9yZqoZTIvKfDxS9yow97RD0QWSzSeq1doRM+MoCCcu1VAMq8kyT0t YDYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=HCrXwkB7; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id rh16-20020a17090720f000b00992ae4db3c9si7333843ejb.15.2023.09.05.02.09.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 02:09:35 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=HCrXwkB7; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ED52B3857BB2 for ; Tue, 5 Sep 2023 09:09:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ED52B3857BB2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693904963; bh=jlI6m0er38GZscTM8fcr/N21EDMxUlgYejM66hhfzfI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=HCrXwkB7FPzZF2VAQdd+GVDXVq+Qky+RYaCbmUHChJbwlRxJheqxqmn1tYVCR+Erp tVPAdMoP/z9xCqz8LukX/0aOgVKxO1NeO375hTHL1roHT/uxNqsGpRuYBCzyDx75bY m9kH13w4coiaxHndI1UaRKu3EbcCsBPsvy1DoWZM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 0477C3857359; Tue, 5 Sep 2023 09:09:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0477C3857359 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5E511300089; Tue, 5 Sep 2023 09:09:07 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 2/3] RISC-V: Add "lp64e" ABI support Date: Tue, 5 Sep 2023 09:08:36 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772357774806256207 X-GMAIL-MSGID: 1776188103062245459 From: Tsukasa OI Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise. --- gas/config/tc-riscv.c | 4 +++- gas/doc/c-riscv.texi | 5 ++--- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e3bcf8b280eb..f2a031735eb4 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -386,7 +386,7 @@ riscv_set_abi_by_arch (void) as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) - as_bad ("only the ilp32e ABI is supported for e extension"); + as_bad ("only ilp32e/lp64e ABI are supported for e extension"); if (float_abi == FLOAT_ABI_SINGLE && !riscv_subset_supports (&riscv_rps_as, "f")) @@ -3871,6 +3871,8 @@ md_parse_option (int c, const char *arg) riscv_set_abi (32, FLOAT_ABI_QUAD, false); else if (strcmp (arg, "lp64") == 0) riscv_set_abi (64, FLOAT_ABI_SOFT, false); + else if (strcmp (arg, "lp64e") == 0) + riscv_set_abi (64, FLOAT_ABI_SOFT, true); else if (strcmp (arg, "lp64f") == 0) riscv_set_abi (64, FLOAT_ABI_SINGLE, false); else if (strcmp (arg, "lp64d") == 0) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b175ba0a7293..e7fdbfa22afb 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting @item -mabi=ABI Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or -quad-precision floating-point calling convention, or none to indicate -the soft-float calling convention. Also, "ilp32" can optionally be followed -by "e" to indicate the RVE ABI, which is always soft-float. +quad-precision floating-point calling convention, or none or "e" to indicate +the soft-float calling convention ("e" indicates a soft-float RVE ABI). @cindex @samp{-mrelax} option, RISC-V @item -mrelax diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l index f7306cb24d20..419a01d5d53a 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l index 706690ac9c64..7b2fcda8d685 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l index ab64b1546f63..a06e9ea1aa93 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported From patchwork Tue Sep 5 09:08:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 137492 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ab0a:0:b0:3f2:4152:657d with SMTP id m10csp1554961vqo; Tue, 5 Sep 2023 02:09:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF74LH0+Gq2ys8zPqwed3i9PMooDLPjWgU9Vn9MppvSIm4Gddw8qd2yNmEE3mPynITE2Vc/ X-Received: by 2002:a17:906:32d9:b0:9a1:688f:cf2d with SMTP id k25-20020a17090632d900b009a1688fcf2dmr8650020ejk.39.1693904995487; Tue, 05 Sep 2023 02:09:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693904995; cv=none; d=google.com; s=arc-20160816; b=isiQrYro2qd8JGkubeuPPcVVtYRv78N8LmrBmQAmUxTcP0b9s7jNJYlBqdnWHF/DwR mkOIue3WEpuA/4b8TmPJH1UU/aGTZsDYw6AJTdi9Q2mTBkNs625GSwAOWukFk7K6/lPi w9a4Xb83+UXefEwpTok1l9g8d6HBBzGGjR94380TxY0L1dKwk3W8RTycZ5vNWcfU/p2/ 6ALo/mqMVDCZetAmvduF5HrbOzi8aZ9SwVJqEnhwZr8rhO2ODMjVCAlK2xclAYhTo6IO HA3w7AZniOMVVGHXTxKbed77ytr6f34dsjK6/GaBAOwlS7sESLdR/Zo3Zso9UMCId0ll 2bKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=VnWs0K+9KHEZ9cbflpgDfs4aNi3zzC0VfrZ0dj1yqCw=; fh=lMz0tc6bjmUz1Gwj2ppdH/A+guv79ykg2fc+XnZhGVU=; b=B37zWVvJDZK3L9UoXTkjsozkmaepDw0sWM3OwOUsRxxEacgba4cAg7nLI2qql45rea GsQWzm02Y27XlUaDMgLtlS59bKBEzIM+wk5O73RtbUFxdR8frYCLqbOCqYOyQvnEK5+G ViqFGDcsykNeWlkeMrN13emrZqIJAo28sIkYuxGXBrDyVZj3vhN2EOdGjxCysDZIxnDU 9pCHi916hd/15mlDHn6bZvM5uB8TuVymbaGefHHBn3/euwlsxPIp5riuQAbNJ5PZwSFY 7S/sXBKx5i6uDb0y9AOKnhV63pgsa7dfC5x4ie5AU5VJIKt3fgRli1oVi9SPR2tlMtYM clPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=mv9Oqcbe; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id r12-20020a170906c28c00b0099d974b86eesi7415862ejz.379.2023.09.05.02.09.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 02:09:55 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=mv9Oqcbe; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C7C4038555AB for ; Tue, 5 Sep 2023 09:09:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C7C4038555AB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693904972; bh=VnWs0K+9KHEZ9cbflpgDfs4aNi3zzC0VfrZ0dj1yqCw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=mv9OqcbeZPhIvviBZSF7D8o3VbJtBjPf+ttgCtmifv8rEXbvBRUVQd8frUZaLZu12 9oPi03F+V8+t0dzYzCXfPyVh7VgjSxgNEra2SkMtniktUkuDUWxNLh8Cpz7U9BSISY hBmflnP/gGQCdU1r+dJntOePv9VdQ1cIWsihQ3pU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 4F5A13856967; Tue, 5 Sep 2023 09:09:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4F5A13856967 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 68DC9300089; Tue, 5 Sep 2023 09:09:18 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 3/3] RISC-V: Add RV64E support to GDB Date: Tue, 5 Sep 2023 09:08:37 +0000 Message-ID: <559ca2571e44464b2d133d79b8c755f2e4afa0e4.1693904909.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775713430951656365 X-GMAIL-MSGID: 1776188124612061813 From: Tsukasa OI Since RV32E and RV64E are ratified, RV64E is no longer invalid. So, this commit adds RV64E support for various parts. --- gdb/arch/riscv.c | 15 +++++++++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 +++++++++++++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 ++++++++++++++++++++++++++++++ gdb/riscv-tdep.c | 9 +-------- 6 files changed, 77 insertions(+), 11 deletions(-) create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c index 6f6fcb081e81..346fc1d0230d 100644 --- a/gdb/arch/riscv.c +++ b/gdb/arch/riscv.c @@ -25,6 +25,7 @@ #include "../features/riscv/32bit-fpu.c" #include "../features/riscv/64bit-fpu.c" #include "../features/riscv/rv32e-xregs.c" +#include "../features/riscv/rv64e-xregs.c" #ifndef GDBSERVER #define STATIC_IN_GDB static @@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) arch_name.append (":rv32i"); } else if (features.xlen == 8) - arch_name.append (":rv64i"); + { + if (features.embedded) + arch_name.append (":rv64e"); + else + arch_name.append (":rv64i"); + } else if (features.xlen == 16) arch_name.append (":rv128i"); @@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum); } else if (features.xlen == 8) - regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + { + if (features.embedded) + regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum); + else + regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + } /* For now we only support creating 32-bit or 64-bit f-registers. */ if (features.flen == 4) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index e1965da69ebb..abbac59aa09b 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -53,7 +53,7 @@ struct riscv_gdbarch_features vector size. */ int vlen = 0; - /* When true this target is RV32E. */ + /* When true this target is RV32E or RV64E. */ bool embedded = false; /* Track if the target description has an fcsr, fflags, and frm diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 32341f718156..a2719d0cd813 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -238,6 +238,7 @@ FEATURE_XMLFILES = aarch64-core.xml \ loongarch/base64.xml \ loongarch/fpu.xml \ riscv/rv32e-xregs.xml \ + riscv/rv64e-xregs.xml \ riscv/32bit-cpu.xml \ riscv/32bit-fpu.xml \ riscv/64bit-cpu.xml \ diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c new file mode 100644 index 000000000000..4346c3004ba8 --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.c @@ -0,0 +1,30 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: rv64e-xregs.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu"); + tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr"); + return regnum; +} diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml new file mode 100644 index 000000000000..103588fd7f2d --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.xml @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index ae18eb644527..b230ba634147 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3847,14 +3847,7 @@ riscv_features_from_bfd (const bfd *abfd) features.flen = 4; if (e_flags & EF_RISCV_RVE) - { - if (features.xlen == 8) - { - warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit")); - features.xlen = 4; - } - features.embedded = true; - } + features.embedded = true; } return features;