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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q20-20020a170906361400b0099c9e68e3b4si3603865ejb.325.2023.09.02.01.54.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Sep 2023 01:54:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=iabuhXCx; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 011D23858296 for ; Sat, 2 Sep 2023 08:54:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 011D23858296 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693644853; bh=Skg2ysuWPw9rqiqEUHqf4XPU7XSuNpZPtKNfMRSDXcs=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=iabuhXCxKwx4JOnkedyaZ+QmNmuTzeltx/YPZU9EkVdxDI+8KFpprmezIWWmZHKLD ZEaFhnwPo8ROnGkkqQenT3rITXxOd2sAkzQOwufsrNJ1yGUHsJDh3WAyjeGXF5Ml3m taR7Fb11BxIC3fj9l2Y7yuXNJ98PK1Ug8RmYIzAA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 54AB93858D39 for ; Sat, 2 Sep 2023 08:53:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 54AB93858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="440330956" X-IronPort-AV: E=Sophos;i="6.02,222,1688454000"; d="scan'208";a="440330956" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2023 01:53:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="740170224" X-IronPort-AV: E=Sophos;i="6.02,222,1688454000"; d="scan'208";a="740170224" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 02 Sep 2023 01:53:16 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 339C6100570E; Sat, 2 Sep 2023 16:53:15 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH v1] RISC-V: Support FP MAX/MIN autovec for VLS mode Date: Sat, 2 Sep 2023 16:53:13 +0800 Message-Id: <20230902085313.801607-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Cc: yanzhang.wang@intel.com, kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775915347032765280 X-GMAIL-MSGID: 1775915347032765280 From: Pan Li This patch would like to allow the VLS mode autovec for the floating-point binary operation MAX/MIN. Given below code example: test (float *out, float *in1, float *in2) { for (int i = 0; i < 128; i++) out[i] = in1[i] > in2[i] ? in1[i] : in2[i]; // Or out[i] = fmax (in1[i], in2[i]); } Before this patch: test: csrr a4,vlenb slli a4,a4,1 li a5,128 bleu a5,a4,.L2 mv a5,a4 .L2: vsetvli zero,a5,e32,m8,ta,ma vle32.v v16,0(a1) vle32.v v8,0(a2) vsetvli a3,zero,e32,m8,ta,ma vmfgt.vv v0,v16,v8 vmerge.vvm v8,v8,v16,v0 vsetvli zero,a5,e32,m8,ta,ma vse32.v v8,0(a0) ret After this patch: test: li a5,128 vsetvli zero,a5,e32,m1,ta,ma vle32.v v1,0(a1) vle32.v v2,0(a2) vfmax.vv v1,v1,v2 vse32.v v1,0(a0) ret This MAX/MIN autovec acts on function call like fmaxf/fmax in math.h too. And it depends on the option -ffast-math. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-vls.md (3): New pattern for fmax/fmin * config/riscv/vector.md: Add VLS modes to vfmax/vfmin. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: New macros. * gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: New test. Signed-off-by: Pan Li > --- gcc/config/riscv/autovec-vls.md | 23 ++++++++++ gcc/config/riscv/vector.md | 12 +++--- .../gcc.target/riscv/rvv/autovec/vls/def.h | 16 +++++++ .../rvv/autovec/vls/floating-point-max-1.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-max-2.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-max-3.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-max-4.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-max-5.c | 31 +++++++++++++ .../rvv/autovec/vls/floating-point-min-1.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-min-2.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-min-3.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-min-4.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-min-5.c | 31 +++++++++++++ 13 files changed, 451 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 4ca640c11e2..7ef29637e33 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -232,6 +232,29 @@ (define_insn_and_split "3" [(set_attr "type" "vector")] ) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfmin.vv/vfmax.vv +;; - vfmin.vf/vfmax.vf +;; - fmax/fmaxf in math.h +;; ------------------------------------------------------------------------- +(define_insn_and_split "3" + [(set (match_operand:VLSF 0 "register_operand") + (any_float_binop_nofrm:VLSF + (match_operand:VLSF 1 "") + (match_operand:VLSF 2 "")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + riscv_vector::emit_vlmax_insn (code_for_pred (, mode), + riscv_vector::BINARY_OP, operands); + DONE; +} +[(set_attr "type" "vector")] +) + ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations ;; ------------------------------------------------------------------------------- diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6fe750ca8a4..9d7b4bbe1d4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6050,8 +6050,8 @@ (define_insn "@pred_" (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6060,10 +6060,10 @@ (define_insn "@pred_" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_float_binop_nofrm:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_binop_nofrm:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 476f966c427..2e07e908736 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -143,6 +143,14 @@ typedef double v512df __attribute__ ((vector_size (4096))); a[i] = b[i] OP c[i] ? b[i] : c[i]; \ } +#define DEF_MINMAX_VX(PREFIX, NUM, TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = b[i] OP c ? b[i] : c; \ + } + #define DEF_OP_VI_7(PREFIX, NUM, TYPE, OP) \ void __attribute__ ((noinline, noclone)) \ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \ @@ -159,6 +167,14 @@ typedef double v512df __attribute__ ((vector_size (4096))); a[i] = OP b[i]; \ } +#define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = CALL (b[i], c[i]); \ + } + #define DEF_CONST(TYPE, VAL, NUM) \ void const_##TYPE##_##NUM (TYPE *restrict a) \ { \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c new file mode 100644 index 00000000000..8d3cd2aa538 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VV (max, 1, _Float16, >) +DEF_MINMAX_VV (max, 2, _Float16, >) +DEF_MINMAX_VV (max, 4, _Float16, >) +DEF_MINMAX_VV (max, 8, _Float16, >) +DEF_MINMAX_VV (max, 16, _Float16, >) +DEF_MINMAX_VV (max, 32, _Float16, >) +DEF_MINMAX_VV (max, 64, _Float16, >) +DEF_MINMAX_VV (max, 128, _Float16, >) +DEF_MINMAX_VV (max, 256, _Float16, >) +DEF_MINMAX_VV (max, 512, _Float16, >) +DEF_MINMAX_VV (max, 1024, _Float16, >) +DEF_MINMAX_VV (max, 2048, _Float16, >) + +DEF_MINMAX_VV (max, 1, float, >) +DEF_MINMAX_VV (max, 2, float, >) +DEF_MINMAX_VV (max, 4, float, >) +DEF_MINMAX_VV (max, 8, float, >) +DEF_MINMAX_VV (max, 16, float, >) +DEF_MINMAX_VV (max, 32, float, >) +DEF_MINMAX_VV (max, 64, float, >) +DEF_MINMAX_VV (max, 128, float, >) +DEF_MINMAX_VV (max, 256, float, >) +DEF_MINMAX_VV (max, 512, float, >) +DEF_MINMAX_VV (max, 1024, float, >) + +DEF_MINMAX_VV (max, 1, double, >) +DEF_MINMAX_VV (max, 2, double, >) +DEF_MINMAX_VV (max, 4, double, >) +DEF_MINMAX_VV (max, 8, double, >) +DEF_MINMAX_VV (max, 16, double, >) +DEF_MINMAX_VV (max, 32, double, >) +DEF_MINMAX_VV (max, 64, double, >) +DEF_MINMAX_VV (max, 128, double, >) +DEF_MINMAX_VV (max, 256, double, >) +DEF_MINMAX_VV (max, 512, double, >) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c new file mode 100644 index 00000000000..a13de042041 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VX (max, 1, _Float16, >) +DEF_MINMAX_VX (max, 2, _Float16, >) +DEF_MINMAX_VX (max, 4, _Float16, >) +DEF_MINMAX_VX (max, 8, _Float16, >) +DEF_MINMAX_VX (max, 16, _Float16, >) +DEF_MINMAX_VX (max, 32, _Float16, >) +DEF_MINMAX_VX (max, 64, _Float16, >) +DEF_MINMAX_VX (max, 128, _Float16, >) +DEF_MINMAX_VX (max, 256, _Float16, >) +DEF_MINMAX_VX (max, 512, _Float16, >) +DEF_MINMAX_VX (max, 1024, _Float16, >) +DEF_MINMAX_VX (max, 2048, _Float16, >) + +DEF_MINMAX_VX (max, 1, float, >) +DEF_MINMAX_VX (max, 2, float, >) +DEF_MINMAX_VX (max, 4, float, >) +DEF_MINMAX_VX (max, 8, float, >) +DEF_MINMAX_VX (max, 16, float, >) +DEF_MINMAX_VX (max, 32, float, >) +DEF_MINMAX_VX (max, 64, float, >) +DEF_MINMAX_VX (max, 128, float, >) +DEF_MINMAX_VX (max, 256, float, >) +DEF_MINMAX_VX (max, 512, float, >) +DEF_MINMAX_VX (max, 1024, float, >) + +DEF_MINMAX_VX (max, 1, double, >) +DEF_MINMAX_VX (max, 2, double, >) +DEF_MINMAX_VX (max, 4, double, >) +DEF_MINMAX_VX (max, 8, double, >) +DEF_MINMAX_VX (max, 16, double, >) +DEF_MINMAX_VX (max, 32, double, >) +DEF_MINMAX_VX (max, 64, double, >) +DEF_MINMAX_VX (max, 128, double, >) +DEF_MINMAX_VX (max, 256, double, >) +DEF_MINMAX_VX (max, 512, double, >) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c new file mode 100644 index 00000000000..108a883bba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VV (max, 1, _Float16, >=) +DEF_MINMAX_VV (max, 2, _Float16, >=) +DEF_MINMAX_VV (max, 4, _Float16, >=) +DEF_MINMAX_VV (max, 8, _Float16, >=) +DEF_MINMAX_VV (max, 16, _Float16, >=) +DEF_MINMAX_VV (max, 32, _Float16, >=) +DEF_MINMAX_VV (max, 64, _Float16, >=) +DEF_MINMAX_VV (max, 128, _Float16, >=) +DEF_MINMAX_VV (max, 256, _Float16, >=) +DEF_MINMAX_VV (max, 512, _Float16, >=) +DEF_MINMAX_VV (max, 1024, _Float16, >=) +DEF_MINMAX_VV (max, 2048, _Float16, >=) + +DEF_MINMAX_VV (max, 1, float, >=) +DEF_MINMAX_VV (max, 2, float, >=) +DEF_MINMAX_VV (max, 4, float, >=) +DEF_MINMAX_VV (max, 8, float, >=) +DEF_MINMAX_VV (max, 16, float, >=) +DEF_MINMAX_VV (max, 32, float, >=) +DEF_MINMAX_VV (max, 64, float, >=) +DEF_MINMAX_VV (max, 128, float, >=) +DEF_MINMAX_VV (max, 256, float, >=) +DEF_MINMAX_VV (max, 512, float, >=) +DEF_MINMAX_VV (max, 1024, float, >=) + +DEF_MINMAX_VV (max, 1, double, >=) +DEF_MINMAX_VV (max, 2, double, >=) +DEF_MINMAX_VV (max, 4, double, >=) +DEF_MINMAX_VV (max, 8, double, >=) +DEF_MINMAX_VV (max, 16, double, >=) +DEF_MINMAX_VV (max, 32, double, >=) +DEF_MINMAX_VV (max, 64, double, >=) +DEF_MINMAX_VV (max, 128, double, >=) +DEF_MINMAX_VV (max, 256, double, >=) +DEF_MINMAX_VV (max, 512, double, >=) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c new file mode 100644 index 00000000000..d74801887b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VX (max, 1, _Float16, >=) +DEF_MINMAX_VX (max, 2, _Float16, >=) +DEF_MINMAX_VX (max, 4, _Float16, >=) +DEF_MINMAX_VX (max, 8, _Float16, >=) +DEF_MINMAX_VX (max, 16, _Float16, >=) +DEF_MINMAX_VX (max, 32, _Float16, >=) +DEF_MINMAX_VX (max, 64, _Float16, >=) +DEF_MINMAX_VX (max, 128, _Float16, >=) +DEF_MINMAX_VX (max, 256, _Float16, >=) +DEF_MINMAX_VX (max, 512, _Float16, >=) +DEF_MINMAX_VX (max, 1024, _Float16, >=) +DEF_MINMAX_VX (max, 2048, _Float16, >=) + +DEF_MINMAX_VX (max, 1, float, >=) +DEF_MINMAX_VX (max, 2, float, >=) +DEF_MINMAX_VX (max, 4, float, >=) +DEF_MINMAX_VX (max, 8, float, >=) +DEF_MINMAX_VX (max, 16, float, >=) +DEF_MINMAX_VX (max, 32, float, >=) +DEF_MINMAX_VX (max, 64, float, >=) +DEF_MINMAX_VX (max, 128, float, >=) +DEF_MINMAX_VX (max, 256, float, >=) +DEF_MINMAX_VX (max, 512, float, >=) +DEF_MINMAX_VX (max, 1024, float, >=) + +DEF_MINMAX_VX (max, 1, double, >=) +DEF_MINMAX_VX (max, 2, double, >=) +DEF_MINMAX_VX (max, 4, double, >=) +DEF_MINMAX_VX (max, 8, double, >=) +DEF_MINMAX_VX (max, 16, double, >=) +DEF_MINMAX_VX (max, 32, double, >=) +DEF_MINMAX_VX (max, 64, double, >=) +DEF_MINMAX_VX (max, 128, double, >=) +DEF_MINMAX_VX (max, 256, double, >=) +DEF_MINMAX_VX (max, 512, double, >=) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c new file mode 100644 index 00000000000..775ddb1d25e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" +#include "math.h" + +DEF_CALL_VV (max, 1, float, fmaxf) +DEF_CALL_VV (max, 2, float, fmaxf) +DEF_CALL_VV (max, 4, float, fmaxf) +DEF_CALL_VV (max, 8, float, fmaxf) +DEF_CALL_VV (max, 16, float, fmaxf) +DEF_CALL_VV (max, 32, float, fmaxf) +DEF_CALL_VV (max, 64, float, fmaxf) +DEF_CALL_VV (max, 128, float, fmaxf) +DEF_CALL_VV (max, 256, float, fmaxf) +DEF_CALL_VV (max, 512, float, fmaxf) +DEF_CALL_VV (max, 1024, float, fmaxf) + +DEF_CALL_VV (max, 1, double, fmax) +DEF_CALL_VV (max, 2, double, fmax) +DEF_CALL_VV (max, 4, double, fmax) +DEF_CALL_VV (max, 8, double, fmax) +DEF_CALL_VV (max, 16, double, fmax) +DEF_CALL_VV (max, 32, double, fmax) +DEF_CALL_VV (max, 64, double, fmax) +DEF_CALL_VV (max, 128, double, fmax) +DEF_CALL_VV (max, 256, double, fmax) +DEF_CALL_VV (max, 512, double, fmax) + +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c new file mode 100644 index 00000000000..e082c47b044 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VV (min, 1, _Float16, <) +DEF_MINMAX_VV (min, 2, _Float16, <) +DEF_MINMAX_VV (min, 4, _Float16, <) +DEF_MINMAX_VV (min, 8, _Float16, <) +DEF_MINMAX_VV (min, 16, _Float16, <) +DEF_MINMAX_VV (min, 32, _Float16, <) +DEF_MINMAX_VV (min, 64, _Float16, <) +DEF_MINMAX_VV (min, 128, _Float16, <) +DEF_MINMAX_VV (min, 256, _Float16, <) +DEF_MINMAX_VV (min, 512, _Float16, <) +DEF_MINMAX_VV (min, 1024, _Float16, <) +DEF_MINMAX_VV (min, 2048, _Float16, <) + +DEF_MINMAX_VV (min, 1, float, <) +DEF_MINMAX_VV (min, 2, float, <) +DEF_MINMAX_VV (min, 4, float, <) +DEF_MINMAX_VV (min, 8, float, <) +DEF_MINMAX_VV (min, 16, float, <) +DEF_MINMAX_VV (min, 32, float, <) +DEF_MINMAX_VV (min, 64, float, <) +DEF_MINMAX_VV (min, 128, float, <) +DEF_MINMAX_VV (min, 256, float, <) +DEF_MINMAX_VV (min, 512, float, <) +DEF_MINMAX_VV (min, 1024, float, <) + +DEF_MINMAX_VV (min, 1, double, <) +DEF_MINMAX_VV (min, 2, double, <) +DEF_MINMAX_VV (min, 4, double, <) +DEF_MINMAX_VV (min, 8, double, <) +DEF_MINMAX_VV (min, 16, double, <) +DEF_MINMAX_VV (min, 32, double, <) +DEF_MINMAX_VV (min, 64, double, <) +DEF_MINMAX_VV (min, 128, double, <) +DEF_MINMAX_VV (min, 256, double, <) +DEF_MINMAX_VV (min, 512, double, <) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c new file mode 100644 index 00000000000..1b900522750 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VX (min, 1, _Float16, <) +DEF_MINMAX_VX (min, 2, _Float16, <) +DEF_MINMAX_VX (min, 4, _Float16, <) +DEF_MINMAX_VX (min, 8, _Float16, <) +DEF_MINMAX_VX (min, 16, _Float16, <) +DEF_MINMAX_VX (min, 32, _Float16, <) +DEF_MINMAX_VX (min, 64, _Float16, <) +DEF_MINMAX_VX (min, 128, _Float16, <) +DEF_MINMAX_VX (min, 256, _Float16, <) +DEF_MINMAX_VX (min, 512, _Float16, <) +DEF_MINMAX_VX (min, 1024, _Float16, <) +DEF_MINMAX_VX (min, 2048, _Float16, <) + +DEF_MINMAX_VX (min, 1, float, <) +DEF_MINMAX_VX (min, 2, float, <) +DEF_MINMAX_VX (min, 4, float, <) +DEF_MINMAX_VX (min, 8, float, <) +DEF_MINMAX_VX (min, 16, float, <) +DEF_MINMAX_VX (min, 32, float, <) +DEF_MINMAX_VX (min, 64, float, <) +DEF_MINMAX_VX (min, 128, float, <) +DEF_MINMAX_VX (min, 256, float, <) +DEF_MINMAX_VX (min, 512, float, <) +DEF_MINMAX_VX (min, 1024, float, <) + +DEF_MINMAX_VX (min, 1, double, <) +DEF_MINMAX_VX (min, 2, double, <) +DEF_MINMAX_VX (min, 4, double, <) +DEF_MINMAX_VX (min, 8, double, <) +DEF_MINMAX_VX (min, 16, double, <) +DEF_MINMAX_VX (min, 32, double, <) +DEF_MINMAX_VX (min, 64, double, <) +DEF_MINMAX_VX (min, 128, double, <) +DEF_MINMAX_VX (min, 256, double, <) +DEF_MINMAX_VX (min, 512, double, <) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c new file mode 100644 index 00000000000..ad05800572f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VV (min, 1, _Float16, <=) +DEF_MINMAX_VV (min, 2, _Float16, <=) +DEF_MINMAX_VV (min, 4, _Float16, <=) +DEF_MINMAX_VV (min, 8, _Float16, <=) +DEF_MINMAX_VV (min, 16, _Float16, <=) +DEF_MINMAX_VV (min, 32, _Float16, <=) +DEF_MINMAX_VV (min, 64, _Float16, <=) +DEF_MINMAX_VV (min, 128, _Float16, <=) +DEF_MINMAX_VV (min, 256, _Float16, <=) +DEF_MINMAX_VV (min, 512, _Float16, <=) +DEF_MINMAX_VV (min, 1024, _Float16, <=) +DEF_MINMAX_VV (min, 2048, _Float16, <=) + +DEF_MINMAX_VV (min, 1, float, <=) +DEF_MINMAX_VV (min, 2, float, <=) +DEF_MINMAX_VV (min, 4, float, <=) +DEF_MINMAX_VV (min, 8, float, <=) +DEF_MINMAX_VV (min, 16, float, <=) +DEF_MINMAX_VV (min, 32, float, <=) +DEF_MINMAX_VV (min, 64, float, <=) +DEF_MINMAX_VV (min, 128, float, <=) +DEF_MINMAX_VV (min, 256, float, <=) +DEF_MINMAX_VV (min, 512, float, <=) +DEF_MINMAX_VV (min, 1024, float, <=) + +DEF_MINMAX_VV (min, 1, double, <=) +DEF_MINMAX_VV (min, 2, double, <=) +DEF_MINMAX_VV (min, 4, double, <=) +DEF_MINMAX_VV (min, 8, double, <=) +DEF_MINMAX_VV (min, 16, double, <=) +DEF_MINMAX_VV (min, 32, double, <=) +DEF_MINMAX_VV (min, 64, double, <=) +DEF_MINMAX_VV (min, 128, double, <=) +DEF_MINMAX_VV (min, 256, double, <=) +DEF_MINMAX_VV (min, 512, double, <=) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c new file mode 100644 index 00000000000..5d4109aa3c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_MINMAX_VX (min, 1, _Float16, <=) +DEF_MINMAX_VX (min, 2, _Float16, <=) +DEF_MINMAX_VX (min, 4, _Float16, <=) +DEF_MINMAX_VX (min, 8, _Float16, <=) +DEF_MINMAX_VX (min, 16, _Float16, <=) +DEF_MINMAX_VX (min, 32, _Float16, <=) +DEF_MINMAX_VX (min, 64, _Float16, <=) +DEF_MINMAX_VX (min, 128, _Float16, <=) +DEF_MINMAX_VX (min, 256, _Float16, <=) +DEF_MINMAX_VX (min, 512, _Float16, <=) +DEF_MINMAX_VX (min, 1024, _Float16, <=) +DEF_MINMAX_VX (min, 2048, _Float16, <=) + +DEF_MINMAX_VX (min, 1, float, <=) +DEF_MINMAX_VX (min, 2, float, <=) +DEF_MINMAX_VX (min, 4, float, <=) +DEF_MINMAX_VX (min, 8, float, <=) +DEF_MINMAX_VX (min, 16, float, <=) +DEF_MINMAX_VX (min, 32, float, <=) +DEF_MINMAX_VX (min, 64, float, <=) +DEF_MINMAX_VX (min, 128, float, <=) +DEF_MINMAX_VX (min, 256, float, <=) +DEF_MINMAX_VX (min, 512, float, <=) +DEF_MINMAX_VX (min, 1024, float, <=) + +DEF_MINMAX_VX (min, 1, double, <=) +DEF_MINMAX_VX (min, 2, double, <=) +DEF_MINMAX_VX (min, 4, double, <=) +DEF_MINMAX_VX (min, 8, double, <=) +DEF_MINMAX_VX (min, 16, double, <=) +DEF_MINMAX_VX (min, 32, double, <=) +DEF_MINMAX_VX (min, 64, double, <=) +DEF_MINMAX_VX (min, 128, double, <=) +DEF_MINMAX_VX (min, 256, double, <=) +DEF_MINMAX_VX (min, 512, double, <=) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c new file mode 100644 index 00000000000..1e9ff7d5054 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" +#include "math.h" + +DEF_CALL_VV (min, 1, float, fminf) +DEF_CALL_VV (min, 2, float, fminf) +DEF_CALL_VV (min, 4, float, fminf) +DEF_CALL_VV (min, 8, float, fminf) +DEF_CALL_VV (min, 16, float, fminf) +DEF_CALL_VV (min, 32, float, fminf) +DEF_CALL_VV (min, 64, float, fminf) +DEF_CALL_VV (min, 128, float, fminf) +DEF_CALL_VV (min, 256, float, fminf) +DEF_CALL_VV (min, 512, float, fminf) +DEF_CALL_VV (min, 1024, float, fminf) + +DEF_CALL_VV (min, 1, double, fmin) +DEF_CALL_VV (min, 2, double, fmin) +DEF_CALL_VV (min, 4, double, fmin) +DEF_CALL_VV (min, 8, double, fmin) +DEF_CALL_VV (min, 16, double, fmin) +DEF_CALL_VV (min, 32, double, fmin) +DEF_CALL_VV (min, 64, double, fmin) +DEF_CALL_VV (min, 128, double, fmin) +DEF_CALL_VV (min, 256, double, fmin) +DEF_CALL_VV (min, 512, double, fmin) + +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */