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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q6-20020a170906940600b009a1c2fcdceasi1861818ejx.109.2023.08.31.20.34.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 20:34:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yHIRQg8z; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39FAD385840D for ; Fri, 1 Sep 2023 03:34:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39FAD385840D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693539277; bh=chTL46ASJE/S2PU+yMb7QaaewTWKUlXF3WFuSVxJDA0=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=yHIRQg8zyE85COdGp/aMWLUyPBSSuwdhGfzJHh8QVpoBYXZ8C4xBKF1kxBHO0Qbbe AnEfgEaulQP8Gqbtx9PNvnhJYn/FVDK4zxWzrNs6j2jZ7pW8blWZSNk79+0yk/pozv YDXGNmRT9fwWOl9shofocrh28y6VcmzYdPAHaRdE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id E801F3858D37 for ; Fri, 1 Sep 2023 03:33:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E801F3858D37 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="462489506" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="462489506" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 20:33:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="1070581729" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="1070581729" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 31 Aug 2023 20:33:34 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id DC4B51005701; Fri, 1 Sep 2023 11:33:33 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode Date: Fri, 1 Sep 2023 11:33:32 +0800 Message-Id: <20230901033332.1774189-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Cc: yanzhang.wang@intel.com, kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775804642650993127 X-GMAIL-MSGID: 1775804642650993127 From: Pan Li This patch would like to allow the VLS mode autovec for the floating-point binary operation ADD/SUB/MUL/DIV. Given below code example: test (float *out, float *in1, float *in2) { for (int i = 0; i < 128; i++) out[i] = in1[i] + in2[i]; } Before this patch: test: csrr a4,vlenb slli a4,a4,1 li a5,128 bleu a5,a4,.L38 mv a5,a4 .L38: vsetvli zero,a5,e32,m8,ta,ma vle32.v v16,0(a1) vsetvli a4,zero,e32,m8,ta,ma vmv.v.i v8,0 vsetvli zero,a5,e32,m8,tu,ma vle32.v v24,0(a2) vfadd.vv v8,v24,v16 vse32.v v8,0(a0) ret After this patch: test: li a5,128 vsetvli zero,a5,e32,m1,ta,ma vle32.v v1,0(a2) vle32.v v2,0(a1) vfadd.vv v1,v1,v2 vse32.v v1,0(a0) ret Please note this patch also fix the execution failure of below vect test cases. * vect-alias-check-10.c * vect-alias-check-11.c * vect-alias-check-12.c * vect-alias-check-14.c Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-vls.md (3): New pattern for vls floating-point autovec. * config/riscv/vector-iterators.md: New iterator for floating-point V and VLS. * config/riscv/vector.md: Add VLS to floating-point binop. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: * gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li > --- gcc/config/riscv/autovec-vls.md | 24 ++++++ gcc/config/riscv/vector-iterators.md | 80 +++++++++++++++++++ gcc/config/riscv/vector.md | 12 +-- .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++ .../rvv/autovec/vls/floating-point-add-1.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-add-2.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-add-3.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-div-1.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-div-2.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-div-3.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-mul-1.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-mul-2.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-mul-3.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-sub-1.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-sub-2.c | 43 ++++++++++ .../rvv/autovec/vls/floating-point-sub-3.c | 43 ++++++++++ 16 files changed, 634 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 503ad691b9a..4ca640c11e2 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -208,6 +208,30 @@ (define_insn_and_split "3" [(set_attr "type" "vector")] ) +;; ------------------------------------------------------------------------- +;; ---- [FP] Binary operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfadd.vv/vfsub.vv/vfmul.vv/vfdiv.vv +;; - vfadd.vf/vfsub.vf/vfmul.vf/vfdiv.vf +;; ------------------------------------------------------------------------- +(define_insn_and_split "3" + [(set (match_operand:VLSF 0 "register_operand") + (any_float_binop:VLSF + (match_operand:VLSF 1 "") + (match_operand:VLSF 2 "")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + riscv_vector::emit_vlmax_insn (code_for_pred (, mode), + riscv_vector::BINARY_OP_FRM_DYN, operands); + DONE; +} +[(set_attr "type" "vector")] +) + ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations ;; ------------------------------------------------------------------------------- diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 4023a038fe9..09fa787c0fc 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -445,6 +445,50 @@ (define_mode_iterator V_VLSI [ (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096") ]) +(define_mode_iterator V_VLSF [ + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") + (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") +]) + (define_mode_iterator VF_ZVFHMIN [ (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") @@ -2494,3 +2538,39 @@ (define_mode_iterator VLSI [ (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024") (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048") (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")]) + +(define_mode_iterator VLSF [ + (V1HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V2HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V4HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V8HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V16HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16") + (V32HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (V64HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (V128HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256") + (V256HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512") + (V512HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024") + (V1024HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048") + (V2048HF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096") + (V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32") + (V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64") + (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64") + (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") + (V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256") + (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512") + (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024") + (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048") + (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096") +]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 451138a1b45..6fe750ca8a4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6026,8 +6026,8 @@ (define_insn "@pred_series" ;; ------------------------------------------------------------------------------- (define_insn "@pred_" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6038,10 +6038,10 @@ (define_insn "@pred_" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (any_float_binop:VF - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (any_float_binop:V_VLSF + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 00a8a8d2849..476f966c427 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -95,6 +95,14 @@ typedef double v512df __attribute__ ((vector_size (4096))); a[i] = b[i] OP c[i]; \ } +#define DEF_OP_VX(PREFIX, NUM, TYPE, OP) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = b[i] OP c; \ + } + #define DEF_OP_VI_M16(PREFIX, NUM, TYPE, OP) \ void __attribute__ ((noinline, noclone)) \ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c new file mode 100644 index 00000000000..5c2da4df24e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VV (add, 1, _Float16, +) +DEF_OP_VV (add, 2, _Float16, +) +DEF_OP_VV (add, 4, _Float16, +) +DEF_OP_VV (add, 8, _Float16, +) +DEF_OP_VV (add, 16, _Float16, +) +DEF_OP_VV (add, 32, _Float16, +) +DEF_OP_VV (add, 64, _Float16, +) +DEF_OP_VV (add, 128, _Float16, +) +DEF_OP_VV (add, 256, _Float16, +) +DEF_OP_VV (add, 512, _Float16, +) +DEF_OP_VV (add, 1024, _Float16, +) +DEF_OP_VV (add, 2048, _Float16, +) + +DEF_OP_VV (add, 1, float, +) +DEF_OP_VV (add, 2, float, +) +DEF_OP_VV (add, 4, float, +) +DEF_OP_VV (add, 8, float, +) +DEF_OP_VV (add, 16, float, +) +DEF_OP_VV (add, 32, float, +) +DEF_OP_VV (add, 64, float, +) +DEF_OP_VV (add, 128, float, +) +DEF_OP_VV (add, 256, float, +) +DEF_OP_VV (add, 512, float, +) +DEF_OP_VV (add, 1024, float, +) + +DEF_OP_VV (add, 1, double, +) +DEF_OP_VV (add, 2, double, +) +DEF_OP_VV (add, 4, double, +) +DEF_OP_VV (add, 8, double, +) +DEF_OP_VV (add, 16, double, +) +DEF_OP_VV (add, 32, double, +) +DEF_OP_VV (add, 64, double, +) +DEF_OP_VV (add, 128, double, +) +DEF_OP_VV (add, 256, double, +) +DEF_OP_VV (add, 512, double, +) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c new file mode 100644 index 00000000000..73a355bc085 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VX (add, 1, _Float16, +) +DEF_OP_VX (add, 2, _Float16, +) +DEF_OP_VX (add, 4, _Float16, +) +DEF_OP_VX (add, 8, _Float16, +) +DEF_OP_VX (add, 16, _Float16, +) +DEF_OP_VX (add, 32, _Float16, +) +DEF_OP_VX (add, 64, _Float16, +) +DEF_OP_VX (add, 128, _Float16, +) +DEF_OP_VX (add, 256, _Float16, +) +DEF_OP_VX (add, 512, _Float16, +) +DEF_OP_VX (add, 1024, _Float16, +) +DEF_OP_VX (add, 2048, _Float16, +) + +DEF_OP_VX (add, 1, float, +) +DEF_OP_VX (add, 2, float, +) +DEF_OP_VX (add, 4, float, +) +DEF_OP_VX (add, 8, float, +) +DEF_OP_VX (add, 16, float, +) +DEF_OP_VX (add, 32, float, +) +DEF_OP_VX (add, 64, float, +) +DEF_OP_VX (add, 128, float, +) +DEF_OP_VX (add, 256, float, +) +DEF_OP_VX (add, 512, float, +) +DEF_OP_VX (add, 1024, float, +) + +DEF_OP_VX (add, 1, double, +) +DEF_OP_VX (add, 2, double, +) +DEF_OP_VX (add, 4, double, +) +DEF_OP_VX (add, 8, double, +) +DEF_OP_VX (add, 16, double, +) +DEF_OP_VX (add, 32, double, +) +DEF_OP_VX (add, 64, double, +) +DEF_OP_VX (add, 128, double, +) +DEF_OP_VX (add, 256, double, +) +DEF_OP_VX (add, 512, double, +) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c new file mode 100644 index 00000000000..42925e5143a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VI_15 (add, 1, _Float16, +) +DEF_OP_VI_15 (add, 2, _Float16, +) +DEF_OP_VI_15 (add, 4, _Float16, +) +DEF_OP_VI_15 (add, 8, _Float16, +) +DEF_OP_VI_15 (add, 16, _Float16, +) +DEF_OP_VI_15 (add, 32, _Float16, +) +DEF_OP_VI_15 (add, 64, _Float16, +) +DEF_OP_VI_15 (add, 128, _Float16, +) +DEF_OP_VI_15 (add, 256, _Float16, +) +DEF_OP_VI_15 (add, 512, _Float16, +) +DEF_OP_VI_15 (add, 1024, _Float16, +) +DEF_OP_VI_15 (add, 2048, _Float16, +) + +DEF_OP_VI_15 (add, 1, float, +) +DEF_OP_VI_15 (add, 2, float, +) +DEF_OP_VI_15 (add, 4, float, +) +DEF_OP_VI_15 (add, 8, float, +) +DEF_OP_VI_15 (add, 16, float, +) +DEF_OP_VI_15 (add, 32, float, +) +DEF_OP_VI_15 (add, 64, float, +) +DEF_OP_VI_15 (add, 128, float, +) +DEF_OP_VI_15 (add, 256, float, +) +DEF_OP_VI_15 (add, 512, float, +) +DEF_OP_VI_15 (add, 1024, float, +) + +DEF_OP_VI_15 (add, 1, double, +) +DEF_OP_VI_15 (add, 2, double, +) +DEF_OP_VI_15 (add, 4, double, +) +DEF_OP_VI_15 (add, 8, double, +) +DEF_OP_VI_15 (add, 16, double, +) +DEF_OP_VI_15 (add, 32, double, +) +DEF_OP_VI_15 (add, 64, double, +) +DEF_OP_VI_15 (add, 128, double, +) +DEF_OP_VI_15 (add, 256, double, +) +DEF_OP_VI_15 (add, 512, double, +) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c new file mode 100644 index 00000000000..93a9e39d00c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VV (div, 1, _Float16, /) +DEF_OP_VV (div, 2, _Float16, /) +DEF_OP_VV (div, 4, _Float16, /) +DEF_OP_VV (div, 8, _Float16, /) +DEF_OP_VV (div, 16, _Float16, /) +DEF_OP_VV (div, 32, _Float16, /) +DEF_OP_VV (div, 64, _Float16, /) +DEF_OP_VV (div, 128, _Float16, /) +DEF_OP_VV (div, 256, _Float16, /) +DEF_OP_VV (div, 512, _Float16, /) +DEF_OP_VV (div, 1024, _Float16, /) +DEF_OP_VV (div, 2048, _Float16, /) + +DEF_OP_VV (div, 1, float, /) +DEF_OP_VV (div, 2, float, /) +DEF_OP_VV (div, 4, float, /) +DEF_OP_VV (div, 8, float, /) +DEF_OP_VV (div, 16, float, /) +DEF_OP_VV (div, 32, float, /) +DEF_OP_VV (div, 64, float, /) +DEF_OP_VV (div, 128, float, /) +DEF_OP_VV (div, 256, float, /) +DEF_OP_VV (div, 512, float, /) +DEF_OP_VV (div, 1024, float, /) + +DEF_OP_VV (div, 1, double, /) +DEF_OP_VV (div, 2, double, /) +DEF_OP_VV (div, 4, double, /) +DEF_OP_VV (div, 8, double, /) +DEF_OP_VV (div, 16, double, /) +DEF_OP_VV (div, 32, double, /) +DEF_OP_VV (div, 64, double, /) +DEF_OP_VV (div, 128, double, /) +DEF_OP_VV (div, 256, double, /) +DEF_OP_VV (div, 512, double, /) + +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c new file mode 100644 index 00000000000..a5bc2a0e970 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VX (div, 1, _Float16, /) +DEF_OP_VX (div, 2, _Float16, /) +DEF_OP_VX (div, 4, _Float16, /) +DEF_OP_VX (div, 8, _Float16, /) +DEF_OP_VX (div, 16, _Float16, /) +DEF_OP_VX (div, 32, _Float16, /) +DEF_OP_VX (div, 64, _Float16, /) +DEF_OP_VX (div, 128, _Float16, /) +DEF_OP_VX (div, 256, _Float16, /) +DEF_OP_VX (div, 512, _Float16, /) +DEF_OP_VX (div, 1024, _Float16, /) +DEF_OP_VX (div, 2048, _Float16, /) + +DEF_OP_VX (div, 1, float, /) +DEF_OP_VX (div, 2, float, /) +DEF_OP_VX (div, 4, float, /) +DEF_OP_VX (div, 8, float, /) +DEF_OP_VX (div, 16, float, /) +DEF_OP_VX (div, 32, float, /) +DEF_OP_VX (div, 64, float, /) +DEF_OP_VX (div, 128, float, /) +DEF_OP_VX (div, 256, float, /) +DEF_OP_VX (div, 512, float, /) +DEF_OP_VX (div, 1024, float, /) + +DEF_OP_VX (div, 1, double, /) +DEF_OP_VX (div, 2, double, /) +DEF_OP_VX (div, 4, double, /) +DEF_OP_VX (div, 8, double, /) +DEF_OP_VX (div, 16, double, /) +DEF_OP_VX (div, 32, double, /) +DEF_OP_VX (div, 64, double, /) +DEF_OP_VX (div, 128, double, /) +DEF_OP_VX (div, 256, double, /) +DEF_OP_VX (div, 512, double, /) + +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c new file mode 100644 index 00000000000..f1fb7ed2c9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VI_15 (div, 1, _Float16, /) +DEF_OP_VI_15 (div, 2, _Float16, /) +DEF_OP_VI_15 (div, 4, _Float16, /) +DEF_OP_VI_15 (div, 8, _Float16, /) +DEF_OP_VI_15 (div, 16, _Float16, /) +DEF_OP_VI_15 (div, 32, _Float16, /) +DEF_OP_VI_15 (div, 64, _Float16, /) +DEF_OP_VI_15 (div, 128, _Float16, /) +DEF_OP_VI_15 (div, 256, _Float16, /) +DEF_OP_VI_15 (div, 512, _Float16, /) +DEF_OP_VI_15 (div, 1024, _Float16, /) +DEF_OP_VI_15 (div, 2048, _Float16, /) + +DEF_OP_VI_15 (div, 1, float, /) +DEF_OP_VI_15 (div, 2, float, /) +DEF_OP_VI_15 (div, 4, float, /) +DEF_OP_VI_15 (div, 8, float, /) +DEF_OP_VI_15 (div, 16, float, /) +DEF_OP_VI_15 (div, 32, float, /) +DEF_OP_VI_15 (div, 64, float, /) +DEF_OP_VI_15 (div, 128, float, /) +DEF_OP_VI_15 (div, 256, float, /) +DEF_OP_VI_15 (div, 512, float, /) +DEF_OP_VI_15 (div, 1024, float, /) + +DEF_OP_VI_15 (div, 1, double, /) +DEF_OP_VI_15 (div, 2, double, /) +DEF_OP_VI_15 (div, 4, double, /) +DEF_OP_VI_15 (div, 8, double, /) +DEF_OP_VI_15 (div, 16, double, /) +DEF_OP_VI_15 (div, 32, double, /) +DEF_OP_VI_15 (div, 64, double, /) +DEF_OP_VI_15 (div, 128, double, /) +DEF_OP_VI_15 (div, 256, double, /) +DEF_OP_VI_15 (div, 512, double, /) + +/* { dg-final { scan-assembler-times {vfdiv\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c new file mode 100644 index 00000000000..3beccb275ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VV (mul, 1, _Float16, *) +DEF_OP_VV (mul, 2, _Float16, *) +DEF_OP_VV (mul, 4, _Float16, *) +DEF_OP_VV (mul, 8, _Float16, *) +DEF_OP_VV (mul, 16, _Float16, *) +DEF_OP_VV (mul, 32, _Float16, *) +DEF_OP_VV (mul, 64, _Float16, *) +DEF_OP_VV (mul, 128, _Float16, *) +DEF_OP_VV (mul, 256, _Float16, *) +DEF_OP_VV (mul, 512, _Float16, *) +DEF_OP_VV (mul, 1024, _Float16, *) +DEF_OP_VV (mul, 2048, _Float16, *) + +DEF_OP_VV (mul, 1, float, *) +DEF_OP_VV (mul, 2, float, *) +DEF_OP_VV (mul, 4, float, *) +DEF_OP_VV (mul, 8, float, *) +DEF_OP_VV (mul, 16, float, *) +DEF_OP_VV (mul, 32, float, *) +DEF_OP_VV (mul, 64, float, *) +DEF_OP_VV (mul, 128, float, *) +DEF_OP_VV (mul, 256, float, *) +DEF_OP_VV (mul, 512, float, *) +DEF_OP_VV (mul, 1024, float, *) + +DEF_OP_VV (mul, 1, double, *) +DEF_OP_VV (mul, 2, double, *) +DEF_OP_VV (mul, 4, double, *) +DEF_OP_VV (mul, 8, double, *) +DEF_OP_VV (mul, 16, double, *) +DEF_OP_VV (mul, 32, double, *) +DEF_OP_VV (mul, 64, double, *) +DEF_OP_VV (mul, 128, double, *) +DEF_OP_VV (mul, 256, double, *) +DEF_OP_VV (mul, 512, double, *) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c new file mode 100644 index 00000000000..b9616386177 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VX (mul, 1, _Float16, *) +DEF_OP_VX (mul, 2, _Float16, *) +DEF_OP_VX (mul, 4, _Float16, *) +DEF_OP_VX (mul, 8, _Float16, *) +DEF_OP_VX (mul, 16, _Float16, *) +DEF_OP_VX (mul, 32, _Float16, *) +DEF_OP_VX (mul, 64, _Float16, *) +DEF_OP_VX (mul, 128, _Float16, *) +DEF_OP_VX (mul, 256, _Float16, *) +DEF_OP_VX (mul, 512, _Float16, *) +DEF_OP_VX (mul, 1024, _Float16, *) +DEF_OP_VX (mul, 2048, _Float16, *) + +DEF_OP_VX (mul, 1, float, *) +DEF_OP_VX (mul, 2, float, *) +DEF_OP_VX (mul, 4, float, *) +DEF_OP_VX (mul, 8, float, *) +DEF_OP_VX (mul, 16, float, *) +DEF_OP_VX (mul, 32, float, *) +DEF_OP_VX (mul, 64, float, *) +DEF_OP_VX (mul, 128, float, *) +DEF_OP_VX (mul, 256, float, *) +DEF_OP_VX (mul, 512, float, *) +DEF_OP_VX (mul, 1024, float, *) + +DEF_OP_VX (mul, 1, double, *) +DEF_OP_VX (mul, 2, double, *) +DEF_OP_VX (mul, 4, double, *) +DEF_OP_VX (mul, 8, double, *) +DEF_OP_VX (mul, 16, double, *) +DEF_OP_VX (mul, 32, double, *) +DEF_OP_VX (mul, 64, double, *) +DEF_OP_VX (mul, 128, double, *) +DEF_OP_VX (mul, 256, double, *) +DEF_OP_VX (mul, 512, double, *) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c new file mode 100644 index 00000000000..d8e4e26bc00 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VI_15 (mul, 1, _Float16, *) +DEF_OP_VI_15 (mul, 2, _Float16, *) +DEF_OP_VI_15 (mul, 4, _Float16, *) +DEF_OP_VI_15 (mul, 8, _Float16, *) +DEF_OP_VI_15 (mul, 16, _Float16, *) +DEF_OP_VI_15 (mul, 32, _Float16, *) +DEF_OP_VI_15 (mul, 64, _Float16, *) +DEF_OP_VI_15 (mul, 128, _Float16, *) +DEF_OP_VI_15 (mul, 256, _Float16, *) +DEF_OP_VI_15 (mul, 512, _Float16, *) +DEF_OP_VI_15 (mul, 1024, _Float16, *) +DEF_OP_VI_15 (mul, 2048, _Float16, *) + +DEF_OP_VI_15 (mul, 1, float, *) +DEF_OP_VI_15 (mul, 2, float, *) +DEF_OP_VI_15 (mul, 4, float, *) +DEF_OP_VI_15 (mul, 8, float, *) +DEF_OP_VI_15 (mul, 16, float, *) +DEF_OP_VI_15 (mul, 32, float, *) +DEF_OP_VI_15 (mul, 64, float, *) +DEF_OP_VI_15 (mul, 128, float, *) +DEF_OP_VI_15 (mul, 256, float, *) +DEF_OP_VI_15 (mul, 512, float, *) +DEF_OP_VI_15 (mul, 1024, float, *) + +DEF_OP_VI_15 (mul, 1, double, *) +DEF_OP_VI_15 (mul, 2, double, *) +DEF_OP_VI_15 (mul, 4, double, *) +DEF_OP_VI_15 (mul, 8, double, *) +DEF_OP_VI_15 (mul, 16, double, *) +DEF_OP_VI_15 (mul, 32, double, *) +DEF_OP_VI_15 (mul, 64, double, *) +DEF_OP_VI_15 (mul, 128, double, *) +DEF_OP_VI_15 (mul, 256, double, *) +DEF_OP_VI_15 (mul, 512, double, *) + +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c new file mode 100644 index 00000000000..75fe340935c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VV (sub, 1, _Float16, -) +DEF_OP_VV (sub, 2, _Float16, -) +DEF_OP_VV (sub, 4, _Float16, -) +DEF_OP_VV (sub, 8, _Float16, -) +DEF_OP_VV (sub, 16, _Float16, -) +DEF_OP_VV (sub, 32, _Float16, -) +DEF_OP_VV (sub, 64, _Float16, -) +DEF_OP_VV (sub, 128, _Float16, -) +DEF_OP_VV (sub, 256, _Float16, -) +DEF_OP_VV (sub, 512, _Float16, -) +DEF_OP_VV (sub, 1024, _Float16, -) +DEF_OP_VV (sub, 2048, _Float16, -) + +DEF_OP_VV (sub, 1, float, -) +DEF_OP_VV (sub, 2, float, -) +DEF_OP_VV (sub, 4, float, -) +DEF_OP_VV (sub, 8, float, -) +DEF_OP_VV (sub, 16, float, -) +DEF_OP_VV (sub, 32, float, -) +DEF_OP_VV (sub, 64, float, -) +DEF_OP_VV (sub, 128, float, -) +DEF_OP_VV (sub, 256, float, -) +DEF_OP_VV (sub, 512, float, -) +DEF_OP_VV (sub, 1024, float, -) + +DEF_OP_VV (sub, 1, double, -) +DEF_OP_VV (sub, 2, double, -) +DEF_OP_VV (sub, 4, double, -) +DEF_OP_VV (sub, 8, double, -) +DEF_OP_VV (sub, 16, double, -) +DEF_OP_VV (sub, 32, double, -) +DEF_OP_VV (sub, 64, double, -) +DEF_OP_VV (sub, 128, double, -) +DEF_OP_VV (sub, 256, double, -) +DEF_OP_VV (sub, 512, double, -) + +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c new file mode 100644 index 00000000000..96a6fe6df2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VX (sub, 1, _Float16, -) +DEF_OP_VX (sub, 2, _Float16, -) +DEF_OP_VX (sub, 4, _Float16, -) +DEF_OP_VX (sub, 8, _Float16, -) +DEF_OP_VX (sub, 16, _Float16, -) +DEF_OP_VX (sub, 32, _Float16, -) +DEF_OP_VX (sub, 64, _Float16, -) +DEF_OP_VX (sub, 128, _Float16, -) +DEF_OP_VX (sub, 256, _Float16, -) +DEF_OP_VX (sub, 512, _Float16, -) +DEF_OP_VX (sub, 1024, _Float16, -) +DEF_OP_VX (sub, 2048, _Float16, -) + +DEF_OP_VX (sub, 1, float, -) +DEF_OP_VX (sub, 2, float, -) +DEF_OP_VX (sub, 4, float, -) +DEF_OP_VX (sub, 8, float, -) +DEF_OP_VX (sub, 16, float, -) +DEF_OP_VX (sub, 32, float, -) +DEF_OP_VX (sub, 64, float, -) +DEF_OP_VX (sub, 128, float, -) +DEF_OP_VX (sub, 256, float, -) +DEF_OP_VX (sub, 512, float, -) +DEF_OP_VX (sub, 1024, float, -) + +DEF_OP_VX (sub, 1, double, -) +DEF_OP_VX (sub, 2, double, -) +DEF_OP_VX (sub, 4, double, -) +DEF_OP_VX (sub, 8, double, -) +DEF_OP_VX (sub, 16, double, -) +DEF_OP_VX (sub, 32, double, -) +DEF_OP_VX (sub, 64, double, -) +DEF_OP_VX (sub, 128, double, -) +DEF_OP_VX (sub, 256, double, -) +DEF_OP_VX (sub, 512, double, -) + +/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c new file mode 100644 index 00000000000..0094e2cbf4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ + +#include "def.h" + +DEF_OP_VI_15 (sub, 1, _Float16, -) +DEF_OP_VI_15 (sub, 2, _Float16, -) +DEF_OP_VI_15 (sub, 4, _Float16, -) +DEF_OP_VI_15 (sub, 8, _Float16, -) +DEF_OP_VI_15 (sub, 16, _Float16, -) +DEF_OP_VI_15 (sub, 32, _Float16, -) +DEF_OP_VI_15 (sub, 64, _Float16, -) +DEF_OP_VI_15 (sub, 128, _Float16, -) +DEF_OP_VI_15 (sub, 256, _Float16, -) +DEF_OP_VI_15 (sub, 512, _Float16, -) +DEF_OP_VI_15 (sub, 1024, _Float16, -) +DEF_OP_VI_15 (sub, 2048, _Float16, -) + +DEF_OP_VI_15 (sub, 1, float, -) +DEF_OP_VI_15 (sub, 2, float, -) +DEF_OP_VI_15 (sub, 4, float, -) +DEF_OP_VI_15 (sub, 8, float, -) +DEF_OP_VI_15 (sub, 16, float, -) +DEF_OP_VI_15 (sub, 32, float, -) +DEF_OP_VI_15 (sub, 64, float, -) +DEF_OP_VI_15 (sub, 128, float, -) +DEF_OP_VI_15 (sub, 256, float, -) +DEF_OP_VI_15 (sub, 512, float, -) +DEF_OP_VI_15 (sub, 1024, float, -) + +DEF_OP_VI_15 (sub, 1, double, -) +DEF_OP_VI_15 (sub, 2, double, -) +DEF_OP_VI_15 (sub, 4, double, -) +DEF_OP_VI_15 (sub, 8, double, -) +DEF_OP_VI_15 (sub, 16, double, -) +DEF_OP_VI_15 (sub, 32, double, -) +DEF_OP_VI_15 (sub, 64, double, -) +DEF_OP_VI_15 (sub, 128, double, -) +DEF_OP_VI_15 (sub, 256, double, -) +DEF_OP_VI_15 (sub, 512, double, -) + +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */