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Peter Anvin" Subject: [PATCH 1/4] x86: add X86_FEATURE_XENPV to disabled-features.h Date: Thu, 3 Nov 2022 12:36:33 +0100 Message-Id: <20221103113636.25543-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221103113636.25543-1-jgross@suse.com> References: <20221103113636.25543-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748476446762384945?= X-GMAIL-MSGID: =?utf-8?q?1748476446762384945?= Add X86_FEATURE_XENPV to the features handled specially in disabled-features.h. Signed-off-by: Juergen Gross --- arch/x86/include/asm/disabled-features.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 33d2cd04d254..c862552d7d6d 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -81,6 +81,12 @@ # define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) #endif +#ifdef CONFIG_XEN_PV +# define DISABLE_XENPV 0 +#else +# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31)) +#endif + #ifdef CONFIG_INTEL_TDX_GUEST # define DISABLE_TDX_GUEST 0 #else @@ -98,7 +104,7 @@ #define DISABLED_MASK5 0 #define DISABLED_MASK6 0 #define DISABLED_MASK7 (DISABLE_PTI) -#define DISABLED_MASK8 (DISABLE_TDX_GUEST) +#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST) #define DISABLED_MASK9 (DISABLE_SGX) #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET) From patchwork Thu Nov 3 11:36:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 14830 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp479235wru; Thu, 3 Nov 2022 04:55:06 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6R6QTikKuxOhu5Sd+wzpGpB5LIvbtboNr7Ix5GGOqFtfAo20y3ZDOhhBbaTj6oKVUCK+yU X-Received: by 2002:a63:5319:0:b0:46f:c6e0:661 with SMTP id h25-20020a635319000000b0046fc6e00661mr17045383pgb.571.1667476506005; Thu, 03 Nov 2022 04:55:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667476505; cv=none; d=google.com; s=arc-20160816; b=hLN5UzEnaUZ9N8Ykvz1BQvoDQTAy4RJd9d+1dPjGeMU/PviiWl+l75JdaNYLkMsmDa +DV6nsTsRs4vYuDEQBHol83F7xckl3RgpKD/I4QtyC17sIx1SpOTKqFTbGQIxOi5BGi2 9Id0Tdsdnm9456K5Lmy170ippP4K6LdyMgwU9KY4Cabommq5d1F4rnaQVXaO51ZFZ5+m jh8AKuwXFYJzZwWqq1uVf68cCTDfVNyJue9jqMwgWd/R+5AnLJ3qVj0yLXITwHXDqR3h bizt1T9Awe+t1Remb+RS1l5RZC8+WXX3EphOOjHihSGE9C6lvr549ByU7df0704EXwvh 9Kfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mK6Yb+HDZYey+MdThM5vOztF2LsAJko2NCXxRRCzJLc=; b=hQStN5SSd8x54Hy69g5TAMLvM7HYLgrcTrvS9yLmbGgkKMGBwMWiwqZv0LSJauAxzv rj72fiEa3G3csltLaPNE91L/P8KQ6STuU1x0vjEdiyqvWvdivoULfn1suBNClyKTtSkO LKaPgFC7dt9Oe73GUuAvFP6eVhP0eV+6qwX8f8nWhNpJnufybaUALnclx0mCROcIlU8K pbxGdGs+XbC7x+72vgCj/k0JpnmKd4RG06/NsElpYz89pHJb6E2aRZxHdW/Lz3QBAPNC gax1y6Go8eNmykmYVq6ZDYy2z2zBQlRxyjTs+6NAtV2OG9NSgP9wzlKtr67GxMS1+fZQ 4NRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=kXqfwiKM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH 2/4] x86: remove unneeded 64-bit dependency in arch_enter_from_user_mode() Date: Thu, 3 Nov 2022 12:36:34 +0100 Message-Id: <20221103113636.25543-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221103113636.25543-1-jgross@suse.com> References: <20221103113636.25543-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748475844865387573?= X-GMAIL-MSGID: =?utf-8?q?1748475844865387573?= The check for 64-bit mode when testing X86_FEATURE_XENPV isn't needed, as Xen PV guests are no longer supported in 32-bit mode. While at it switch from boot_cpu_has() to cpu_feature_enabled(). Signed-off-by: Juergen Gross --- arch/x86/include/asm/entry-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry-common.h index 674ed46d3ced..117903881fe4 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -24,8 +24,8 @@ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) /* * For !SMAP hardware we patch out CLAC on entry. */ - if (boot_cpu_has(X86_FEATURE_SMAP) || - (IS_ENABLED(CONFIG_64BIT) && boot_cpu_has(X86_FEATURE_XENPV))) + if (cpu_feature_enabled(X86_FEATURE_SMAP) || + cpu_feature_enabled(X86_FEATURE_XENPV)) mask |= X86_EFLAGS_AC; WARN_ON_ONCE(flags & mask); From patchwork Thu Nov 3 11:36:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 14832 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp482717wru; Thu, 3 Nov 2022 05:02:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7CQfL5+rAZsuUjJUO1E3eZ7+zbsY5MLAuPLRg5+hJMFfq5L3t0o2bHRDe+sgil3kKUX/03 X-Received: by 2002:aa7:8502:0:b0:56c:349e:c18b with SMTP id v2-20020aa78502000000b0056c349ec18bmr30012971pfn.1.1667476934601; Thu, 03 Nov 2022 05:02:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667476934; cv=none; d=google.com; s=arc-20160816; b=t9ipKNDY7iOqIHnnIRNe8KJMDvJv9D8aiLt51vDjGPUrreYV0rzUzbhcN7dBirl5ns lVIyd+dIhlYPPykH38IEJ6+gAS4M5HuYEsI1Ccpn2uWBZ9ZdyzVnrhzWFRUGvYrIF8ho me0WPoKLOUQ9qeVM5fN+DAftr6beqCX7MaEsTQI9k1WtZoa2Z8psGSn7cJIcPdXGVPKF y/ejssr9OplaoJ+QQ+2mQN+1uqWUzC89JncPUayr4pTNiUCTpa+Wl/MTVhJ9gYktFixX whBdC64mUIeZsFLyzPWRqoj742TU004dWa+aex5b/+vKyQdsxNFUvOor4XBZJwKynedW afcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZIOvMf0VCiOOdx+pSynOR3iuEcnpBNHWVTTFgfhwJA0=; b=GCzhx0AchGyCh6FI14Q1xzPIs4NJ9IZVNAehfkFD1nv3YHJK92qRnBWJ97rw5XZMe8 MI808EUBsk3OCGuvaxN1jyUzHxdfCai6eHi3Lwx9d9JKphBPjn7rqmTo4EcjwYkmnf3y HFvDN4/3tXxDULVV6VE2k1x5eLRNVJtNlOzmJIktH8LikDUkZrJORUsMTUoljtwjca5g 2jpMdCo9Vo3g4UZQryeE8BujupGihwjyBIZhzt2uCR1RYcjPx3tsp6swtshGDwC00KlT 76Pf+bcnSkrBODX0iZNWlC6gP906EjNCShL2882QFd9QbjPcg1X8XqGxwuKd4Z7VQQ2s vTsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=fO1ejgT0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH 3/4] x86: drop 32-bit Xen PV guest code in update_task_stack() Date: Thu, 3 Nov 2022 12:36:35 +0100 Message-Id: <20221103113636.25543-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221103113636.25543-1-jgross@suse.com> References: <20221103113636.25543-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748476294114609335?= X-GMAIL-MSGID: =?utf-8?q?1748476294114609335?= Testing for Xen PV guest mode in a 32-bit only code section can be dropped, as Xen PV guests are supported in 64-bit mode only. While at it switch from boot_cpu_has() to cpu_feature_enabled() in the 64-bit part of the code. Signed-off-by: Juergen Gross --- arch/x86/include/asm/switch_to.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index c08eb0fdd11f..5c91305d09d2 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -66,13 +66,10 @@ static inline void update_task_stack(struct task_struct *task) { /* sp0 always points to the entry trampoline stack, which is constant: */ #ifdef CONFIG_X86_32 - if (static_cpu_has(X86_FEATURE_XENPV)) - load_sp0(task->thread.sp0); - else - this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); + this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); #else /* Xen PV enters the kernel on the thread stack. */ - if (static_cpu_has(X86_FEATURE_XENPV)) + if (cpu_feature_enabled(X86_FEATURE_XENPV)) load_sp0(task_top_of_stack(task)); #endif } From patchwork Thu Nov 3 11:36:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 14828 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp475750wru; Thu, 3 Nov 2022 04:46:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5GPT1QnC75JvNA2xP4Ydn1yrjYoH+qRyNxUK+FD3PgM+icHEuWawxybXg2oh/jKWk4AyRm X-Received: by 2002:aa7:dcd5:0:b0:461:5fad:4215 with SMTP id w21-20020aa7dcd5000000b004615fad4215mr30885445edu.332.1667475964596; Thu, 03 Nov 2022 04:46:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667475964; cv=none; d=google.com; s=arc-20160816; b=a7JUJfzduAEOPqWUkflImkpd61CFD5m3g2DOkcnU7r/0n6e2kVc4alCMXANHRDM3p7 wum+FJvHKk2I4XDRvb4oEwEkc0G/sN4Se6qDzF0ZGhO8GB5bbnWTFUp0IKLXxkPWk6Y2 rOZ8v3XHBCXebQn3dVnIpVYYXyjSnujG6uuyCkY8AAvBmFO4el+XdQKjgfmjb4MOs6vv 5J7gjdDcrLacJ2LWrkP3EA7OEit4mAyXxWqds0NtkLi4jXc2ybChoe0HMhW4rE4C5lfo XcdE/bXa8AvP4FwM9WBuDnY4uCJChZ+HaZnI+AwNesYaj2ZjxDUThqY8W+Z8jsXWgk58 Xevg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JbTtzDPkc2Z0HXkinvq56o0oqCsbj4jxT6+YNZSa1dg=; b=UkD4yTg0M8M2UVLPic8bwozT1M66nYAllLumqRDuXE9L2OnjHvTexrIadgrttgtE4V iwOgPamgStLBt9UU7hrLAU0fHJ88wDa8IVjp2PMw2riTE1PcIxaX7JnJt1zFYP46k0EF 4ELPOrCwvfA59q3J63opRso2OSUMMvqE92yojIwa9zAYcNfuYhq82FyWhGrQvLHbUgWw SlP2zLuV10yP7+rvRIfiLIUtwthjuSe2motk1BfT4co4ImNheYwQHpFTgejhH7BmnXTw oYBT8jGUnK1Mcc3M0uEFXPjTt1GuoCcw1OK1ahCWHFI8wfywdqOcQFYKiO2ridXScKsv WFKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=sydXpXUw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Pu Wen , Andy Lutomirski , Peter Zijlstra Subject: [PATCH 4/4] x86: switch to cpu_feature_enabled() for X86_FEATURE_XENPV Date: Thu, 3 Nov 2022 12:36:36 +0100 Message-Id: <20221103113636.25543-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221103113636.25543-1-jgross@suse.com> References: <20221103113636.25543-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748475277387988416?= X-GMAIL-MSGID: =?utf-8?q?1748475277387988416?= Convert the remaining cases of static_cpu_has(X86_FEATURE_XENPV) and boot_cpu_has(X86_FEATURE_XENPV) to use cpu_feature_enabled(), allowing more efficient code in case the kernel is configured without CONFIG_XEN_PV. Signed-off-by: Juergen Gross --- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/bugs.c | 2 +- arch/x86/kernel/cpu/hygon.c | 2 +- arch/x86/kernel/process_64.c | 4 ++-- arch/x86/kernel/topology.c | 2 +- arch/x86/mm/cpu_entry_area.c | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 860b60273df3..697fe881e967 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -985,7 +985,7 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ - if (!cpu_has(c, X86_FEATURE_XENPV)) + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); /* diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index da7c361f47e0..7f78e1527c5e 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1302,7 +1302,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return SPECTRE_V2_CMD_AUTO; } - if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) { + if (cmd == SPECTRE_V2_CMD_IBRS && cpu_feature_enabled(X86_FEATURE_XENPV)) { pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", mitigation_options[i].option); return SPECTRE_V2_CMD_AUTO; diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 21fd425088fe..1c27645fd429 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -339,7 +339,7 @@ static void init_hygon(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_ARAT); /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */ - if (!cpu_has(c, X86_FEATURE_XENPV)) + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); check_null_seg_clears_base(c); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 6b3418bff326..e2f469175be8 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,7 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +190,7 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!static_cpu_has(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs(); diff --git a/arch/x86/kernel/topology.c b/arch/x86/kernel/topology.c index 8617d1ed9d31..1b83377274b8 100644 --- a/arch/x86/kernel/topology.c +++ b/arch/x86/kernel/topology.c @@ -106,7 +106,7 @@ int arch_register_cpu(int num) * Xen PV guests don't support CPU0 hotplug at all. */ if (c->x86_vendor != X86_VENDOR_INTEL || - boot_cpu_has(X86_FEATURE_XENPV)) + cpu_feature_enabled(X86_FEATURE_XENPV)) cpu0_hotpluggable = 0; /* diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index 6c2f1b76a0b6..c83799753d44 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -147,7 +147,7 @@ static void __init setup_cpu_entry_area(unsigned int cpu) * On Xen PV, the GDT must be read-only because the hypervisor * requires it. */ - pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? + pgprot_t gdt_prot = cpu_feature_enabled(X86_FEATURE_XENPV) ? PAGE_KERNEL_RO : PAGE_KERNEL; pgprot_t tss_prot = PAGE_KERNEL; #endif