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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ca3-20020a170906a3c300b0099ce780a194si630877ejb.667.2023.08.31.02.07.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 02:07:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4F1F23858017 for ; Thu, 31 Aug 2023 09:07:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 40765385841C for ; Thu, 31 Aug 2023 09:06:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 40765385841C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp67t1693472783tlp8geoh Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 31 Aug 2023 17:06:22 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: +ynUkgUhZJkHkpG2NzlEnZRM66YrlH/bu/lclwRjTuRoYWW7/17elf+9n8itd En8CzlYwePLalSMCQ8ffuN1bp7bapzdPhPF5rvEa4H9Eif7H8Ii5pCo4K7OruRbuGNws/D9 pQ5bQBRkYpO+gRCt3jZNJnWlYAHt8srkHA0+aLPrWT4yvx3yRPJVaCXe+I24cann4WmE6vD /YP0r6EBuAtmocVk9coSC3aoD2203YZ2ZTupSPsbCIUVMyfKC/06jDchzbe3QnuVp+MGhE6 l4NmL9MJqEpUmiTwQiDmhL10ONql1KpxohycPqwcK6qA3hBBYs0bXa3qjknqyknCWbc8+8q R354paCrzZ24c1fB9vG/g3JXkEAOLs/GZJI2RaYbMUZJvKHpOw7ZDiWj7KybhBWtxR09WVg uoUF3nNg9oY= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6675077783997502113 From: Lehua Ding To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Change vsetvl tail and mask policy to default policy Date: Thu, 31 Aug 2023 17:06:21 +0800 Message-Id: <20230831090621.2687116-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775734974676665753 X-GMAIL-MSGID: 1775734974676665753 This patch change the vsetvl policy to default policy (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead fixed policy. Any policy is now returned, allowing change to agnostic or undisturbed. In the future, users may be able to control the default policy, such as keeping agnostic by compiler options. gcc/ChangeLog: * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here. * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx): Change to default policy. * config/riscv/riscv-vector-builtins-bases.cc: Change to default policy. * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete. * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust. * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust. * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test. --- gcc/config/riscv/riscv-protos.h | 3 +++ gcc/config/riscv/riscv-v.cc | 4 +++- gcc/config/riscv/riscv-vector-builtins-bases.cc | 8 ++++---- gcc/config/riscv/riscv-vsetvl.h | 2 -- gcc/config/riscv/riscv.cc | 3 +-- .../riscv/rvv/base/binop_vx_constraint-171.c | 4 ++-- .../riscv/rvv/base/binop_vx_constraint-173.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 11 +++++++++++ 8 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 92e30a10f3c..e145ee6c69b 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -406,6 +406,9 @@ enum mask_policy MASK_ANY = 2, }; +/* Return true if VALUE is agnostic or any policy. */ +#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) + enum class reduction_type { UNORDERED, diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 427700192a3..6228ff3d92e 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1672,9 +1672,11 @@ static rtx gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl) { unsigned int sew = get_sew (vmode); + rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode); + rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode); return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode), gen_int_mode (get_vlmul (vmode), Pmode), - const0_rtx, const0_rtx); + tail_policy, mask_policy); } /* GET VL * 2 rtx. */ diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 54582ee130c..8e679f72392 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -139,11 +139,11 @@ public: /* LMUL. */ e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode)); - /* TA. */ - e.add_input_operand (Pmode, gen_int_mode (1, Pmode)); + /* TAIL_ANY. */ + e.add_input_operand (Pmode, gen_int_mode (get_prefer_tail_policy (), Pmode)); - /* MU. */ - e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); + /* MASK_ANY. */ + e.add_input_operand (Pmode, gen_int_mode (get_prefer_mask_policy (), Pmode)); return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); } }; diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h index 2a315e45f31..53549abfac5 100644 --- a/gcc/config/riscv/riscv-vsetvl.h +++ b/gcc/config/riscv/riscv-vsetvl.h @@ -21,8 +21,6 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_VSETVL_H #define GCC_RISCV_VSETVL_H -#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) - namespace riscv_vector { /* Classification of vsetvl instruction. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d84fa2311fa..8bca8075713 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5246,8 +5246,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) else if (code == CONST_INT) { /* Tail && Mask policy. */ - bool agnostic_p = UINTVAL (op) & 0x1; - asm_fprintf (file, "%s", agnostic_p ? "a" : "u"); + asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u"); } else output_operand_lossage ("invalid vector constant"); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c index dae5eff42ce..6e8669ae59e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c @@ -7,7 +7,7 @@ /* ** f1: ** ... -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] ** ... ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] ** ... @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int n) /* ** f2: ** ... -** vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au] +** vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au] ** ... ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] ** ... diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c index 0d5a2603856..af9c45e942b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c @@ -7,7 +7,7 @@ /* ** f1: ** ... -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] ** ... ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] ** ... @@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int vl) /* ** f2: ** ... -** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au] +** vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au] ** ... ** vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au] ** ... diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c new file mode 100644 index 00000000000..1703c739f5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include + +size_t foo () +{ + return __riscv_vsetvlmax_e8m1 (); +} + +/* { dg-final { scan-assembler-times {\tvsetvli\t[a-x0-9]+,zero,e8,m1,ta,ma} 1 } } */