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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l9-20020aa7d949000000b005232e129627si7017945eds.670.2023.08.29.19.22.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 19:22:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B81C93858004 for ; Wed, 30 Aug 2023 02:22:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 5118E3858D28 for ; Wed, 30 Aug 2023 02:22:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5118E3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp81t1693362134tza35yrd Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 30 Aug 2023 10:22:12 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJlREPdrSy/cuFVq/adp9ffRD/hh1084uOftEk4D0ZFtDqUvJVAsq 8+9FEOPpKoMPYpA9ME/VX+EWIlUtRv54/TaITZJLi6F3baZStI4f4ZinkcOK11jqBKWKYwy btqtLFKYbBBhv/ZuBozjS0YKS6POiQyyOa7s7T+jmPHCkCPX1BpF+J7QGF2rQJ2RNT0PP8u cIaYNZP9RPOdC4b+LQIvgi865TtuUMpYYUWaFXXm5L0JvLsiJJFdWMUQCfB/xTyT8uUS9Mq JgEurcZzOm3zEnnujIqoUuAyHyxoew/OGfShUn1HzseMsMWwFfvuqr92jvOAbB/dt6Nsq2L p5f9kr8YftxVDvb4xvhC9tMQjDVvlWiA6KseUeoK97brIxDCzyBzfQYSdPN/Ove7RIUUgwN X-QQ-GoodBg: 2 X-BIZMAIL-ID: 76548916835888533 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl Date: Wed, 30 Aug 2023 10:22:11 +0800 Message-Id: <20230830022211.2242563-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, Juzhe-Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775618932346110359 X-GMAIL-MSGID: 1775618932346110359 Fix ICE in "vect" testsuite: FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record, at df-scan.cc:2958) FAIL: gcc.dg/vect/pr64495.c (test for excess errors After this patch, all current found VSETVL PASS related bugs in "vect" are fixed. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): Fix bug. --- gcc/config/riscv/riscv-vsetvl.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 73d672b083b..1386d9250ca 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2300,18 +2300,26 @@ vector_insn_info::get_avl_or_vl_reg (void) const if (!vlmax_avl_p (get_avl ())) return get_avl (); - if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl ())) - return ::get_vl (get_insn ()->rtl ()); - if (get_avl_source ()) return get_avl_reg_rtx (); + rtx_insn *rinsn = get_insn ()->rtl (); + if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn)) + { + rtx vl = ::get_vl (rinsn); + /* For VLMAX, we should make sure we get the + REG to emit 'vsetvl VL,zero' since the 'VL' + should be the REG according to RVV ISA. */ + if (REG_P (vl)) + return vl; + } + /* A DIRTY (polluted EMPTY) block if: - get_insn is scalar move (no AVL or VL operand). - get_avl_source is null (no def in the current DIRTY block). Then we trace the previous insn which must be the insn already inserted in Phase 2 to get the VL operand for VLMAX. */ - rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ()); + rtx_insn *prev_rinsn = PREV_INSN (rinsn); gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn)); return ::get_vl (prev_rinsn); }