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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id rv14-20020a17090710ce00b0099bcde09ca3si4263148ejb.89.2023.08.29.16.03.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:03:22 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="ad4/Tpd6"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 314803857BA4 for ; Tue, 29 Aug 2023 23:03:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 8F4653858402 for ; Tue, 29 Aug 2023 23:02:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F4653858402 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bc8a2f71eeso31285705ad.0 for ; Tue, 29 Aug 2023 16:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1693350149; x=1693954949; darn=gcc.gnu.org; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=o78+yrT0Akm7M43HDhX8oPLJn47mNY5HN3LA4/bns9A=; b=ad4/Tpd6ui8LrD9YUvVv+uCgtlFdA4cOfezWYYTjvKbLSWPAPFFi7T24bCwfLaa2wz e5uL4yy5Ig92y69RBjc3QK5uhQIHBlh2b5tbPcskrusVOPyWuxXFuKEy2FmfDTWI6fUI FzWPHYtwNV6dvdDaPC/q2+1H92XUrf3LMsE30W2n0iYcnEBniUUm82DzgTVfVqpZAo3L ny/bHF/tPKqcfYL9oaXvHFHYKfjj+0Ebd8TFDKwrcm3d6kKtvr2HTYO6DFwXe4cdja0x d9XIXfulPlyuHALJgC67164GcLweBCDB1cMRaztodTG+kWCi4m2xJHafxAqMuzefPzle b1Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693350149; x=1693954949; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=o78+yrT0Akm7M43HDhX8oPLJn47mNY5HN3LA4/bns9A=; b=YeWrQeqNS5KlVf5kAmV7IFh9I+vPD4yjfJV2NhITwWTK+uAMDCj3SyunnhmM5EGSwm NUwbN+GLLFeboViBX0rEwOSgw5VZ0aR+XGctk2SR4x+HS5un8CnrQr1Okx2R7x0LwX76 Rls1PfYtYDTuC40L9AUHV80TcHSPSN5U5RA0RqIM40JgkBFLRgMF2LnnOC+TaiKsKcwE tJ5wE4APeNqrGnLDOxVokgwHV/XGwIFtfNSPwO1jQOlWxQhHMJcgrv4yFDmhfadRStTN UNglevvAw9ITB6S5phA9W+Mi77SUdxB6tctq61+x1+x3BYrlV3sAGdA3GlTWCqYpzyG+ ADdQ== X-Gm-Message-State: AOJu0Yx0NGVBTCZ2w0Ql4S+a2UaFh3QoY4fFEMEk9u08ZWl8vPFmDX5M N/LPkpTRVF4lco3r0Uq0YMZMxeaVuNpY04eaOHvSMA== X-Received: by 2002:a17:902:bd45:b0:1bc:2c79:c6b6 with SMTP id b5-20020a170902bd4500b001bc2c79c6b6mr405583plx.28.1693350148986; Tue, 29 Aug 2023 16:02:28 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id f15-20020a170902ff0f00b001b801044466sm9802519plj.114.2023.08.29.16.02.27 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Aug 2023 16:02:28 -0700 (PDT) Message-ID: Date: Tue, 29 Aug 2023 17:02:27 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US From: Jeff Law Subject: [committed] RISC-V: Use splitter to generate zicond in another case To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775606381299237868 X-GMAIL-MSGID: 1775606381299237868 So in analyzing Ventana's internal tree against the trunk it became apparent that the current zicond code is missing a case that helps coremark's bitwise CRC implementation. Here's a minimized testcase: long xor1(long crc, long poly) { if (crc & 1) crc ^= poly; return crc; } ie, it's just a conditional xor. We generate this: andi a5,a0,1 neg a5,a5 and a5,a5,a1 xor a0,a5,a0 ret But we should instead generate: andi a5,a0,1 czero.eqz a5,a1,a5 xor a0,a5,a0 ret Combine wants to generate: Trying 7, 8 -> 9: 7: r140:DI=r137:DI&0x1 8: r141:DI=-r140:DI REG_DEAD r140:DI 9: r142:DI=r141:DI&r144:DI REG_DEAD r144:DI REG_DEAD r141:DI Failed to match this instruction: (set (reg:DI 142) (and:DI (sign_extract:DI (reg/v:DI 137 [ crc ]) (const_int 1 [0x1]) (const_int 0 [0])) (reg:DI 144))) A splitter can rewrite the above into a suitable if-then-else construct and squeeze an instruction out of that pesky CRC loop. Sadly it doesn't really help anything else. The patch includes two variants. One that uses ZBS, the other uses an ANDI logical to produce the input condition. This was primarily Philipp's work under contract with Ventana. I just rewrite the split bits in an if-then-else form and adjusted the testsuite for zicond instead of xventanacondops. Pushed to the trunk, Jeff commit 94b950df6f8c46925799f642e5c44f42638f2b5e Author: Philipp Tomsich Date: Tue Aug 29 16:48:24 2023 -0600 RISC-V: Use splitter to generate zicond in another case So in analyzing Ventana's internal tree against the trunk it became apparent that the current zicond code is missing a case that helps coremark's bitwise CRC implementation. Here's a minimized testcase: long xor1(long crc, long poly) { if (crc & 1) crc ^= poly; return crc; } ie, it's just a conditional xor. We generate this: andi a5,a0,1 neg a5,a5 and a5,a5,a1 xor a0,a5,a0 ret But we should instead generate: andi a5,a0,1 czero.eqz a5,a1,a5 xor a0,a5,a0 ret Combine wants to generate: Trying 7, 8 -> 9: 7: r140:DI=r137:DI&0x1 8: r141:DI=-r140:DI REG_DEAD r140:DI 9: r142:DI=r141:DI&r144:DI REG_DEAD r144:DI REG_DEAD r141:DI Failed to match this instruction: (set (reg:DI 142) (and:DI (sign_extract:DI (reg/v:DI 137 [ crc ]) (const_int 1 [0x1]) (const_int 0 [0])) (reg:DI 144))) A splitter can rewrite the above into a suitable if-then-else construct and squeeze an instruction out of that pesky CRC loop. Sadly it doesn't really help anything else. The patch includes two variants. One that uses ZBS, the other uses an ANDI logical to produce the input condition. gcc/ * config/riscv/zicond.md: New splitters to rewrite single bit sign extension as the condition to a czero in the desired form. gcc/testsuite * gcc.target/riscv/zicond-xor-01.c: New test. Co-authored-by: Jeff Law diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 25f21d33487..4619220ef8a 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -62,3 +62,34 @@ (define_insn "*czero.nez..opt2" "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])" "czero.nez\t%0,%2,%1" ) + +;; Combine creates this form in some cases (particularly the coremark +;; CRC loop. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && TARGET_ZBS" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) + (const_int 0) + (match_dup 3)))]) + +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) + (const_int 0) + (match_dup 3)))] +{ + operands[2] = GEN_INT (1 << UINTVAL(operands[2])); +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c b/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c new file mode 100644 index 00000000000..8362ffaf5ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "czero.eqz\t" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */