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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ov9-20020a170906fc0900b00987383af65asi5153478ejb.582.2023.08.28.20.44.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 20:44:11 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20BCF38582BC for ; Tue, 29 Aug 2023 03:44:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 9893E3858C30 for ; Tue, 29 Aug 2023 03:43:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9893E3858C30 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1693280602tp7gj5w7 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 29 Aug 2023 11:43:21 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: 4MPk5pQyRCW8oC1U6o9qfgETJMr7beo01FgXXIa5x2XTeZf3fbVJhLbYRo6UT 988EfUt68EyRRVNhRES4XVZtWKpXL3kqPKSXIevAzdVPbXa4WzTlLwrTUYWC2OHhFCd6nZw i7Wu99foq5Axj3rJI60XHwjYRIW+KC5tN9onBD0r4E+Hkd4EtS73D70N6/eIvdCJ5nD7LII 0hUKo8os+FTe/U6abh75mx9u1VZLPOANbzn9fpNo9Xee39m1CnLPYJxuJHcMMFRLa4/EO6d npfugB8Jma46RwOnBnZzFCpG6NoeHmJERbQV3MQ+0a9zhR76IP/UHEM3Px6pIE5TU75xGzw oOL9COAoBOEcnuRQhuvn1GD5MUelh6DkH229NLGPDkpmssYbx2YrxfPk+udMQ4uSkW0HVDY XzBIU844Cws= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 12586561531574869027 From: Lehua Ding To: gcc-patches@gcc.gnu.org Subject: [PATCH V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} Date: Tue, 29 Aug 2023 11:43:21 +0800 Message-Id: <20230829034321.174885-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775533452713503291 X-GMAIL-MSGID: 1775533452713503291 V2 changes: Address the comments from Robin. Hi, This patch refactors the codes of expand_cond_len_{unop,binop,ternop}. Introduces a new unified function expand_cond_len_op to do the main thing. The expand_cond_len_{unop,binop,ternop} functions only care about how to pass the operands to the intrinsic patterns. Best, Lehua gcc/ChangeLog: * config/riscv/autovec.md: Adjust * config/riscv/riscv-protos.h (RVV_VUNDEF): Clean. (get_vlmax_rtx): Exported. * config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted. (emit_vlmax_masked_gather_mu_insn): Adjust. (get_vlmax_rtx): New func. (expand_load_store): Adjust. (expand_cond_len_unop): Call expand_cond_len_op. (expand_cond_len_op): New subroutine. (expand_cond_len_binop): Call expand_cond_len_op. (expand_cond_len_ternop): Call expand_cond_len_op. (expand_lanes_load_store): Adjust. --- gcc/config/riscv/autovec.md | 6 +- gcc/config/riscv/riscv-protos.h | 16 ++- gcc/config/riscv/riscv-v.cc | 166 ++++++++++---------------------- 3 files changed, 60 insertions(+), 128 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 20ab0693b98..7a6247d9d6b 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -971,9 +971,9 @@ rtx mask = gen_reg_rtx (mask_mode); riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero); - rtx ops[] = {operands[0], mask, operands[1], operands[1]}; - riscv_vector::emit_vlmax_masked_mu_insn (code_for_pred (NEG, mode), - riscv_vector::RVV_UNOP_MU, ops); + rtx ops[] = {operands[0], mask, operands[1], operands[1], + riscv_vector::get_vlmax_rtx (mode)}; + riscv_vector::expand_cond_len_unop (NEG, ops); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0e0470280f8..4137bb14b80 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -181,25 +181,20 @@ namespace riscv_vector { #define RVV_VUNDEF(MODE) \ gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ UNSPEC_VUNDEF) + +/* The value means the number of operands for insn_expander. */ enum insn_type { RVV_MISC_OP = 1, RVV_UNOP = 2, - RVV_UNOP_M = RVV_UNOP + 2, - RVV_UNOP_MU = RVV_UNOP + 2, - RVV_UNOP_TU = RVV_UNOP + 2, - RVV_UNOP_TUMU = RVV_UNOP + 2, + RVV_UNOP_MASK = RVV_UNOP + 2, RVV_BINOP = 3, - RVV_BINOP_MU = RVV_BINOP + 2, - RVV_BINOP_TU = RVV_BINOP + 2, - RVV_BINOP_TUMU = RVV_BINOP + 2, + RVV_BINOP_MASK = RVV_BINOP + 2, RVV_MERGE_OP = 4, RVV_CMP_OP = 4, RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */ RVV_TERNOP = 5, - RVV_TERNOP_MU = RVV_TERNOP + 1, - RVV_TERNOP_TU = RVV_TERNOP + 1, - RVV_TERNOP_TUMU = RVV_TERNOP + 1, + RVV_TERNOP_MASK = RVV_TERNOP + 1, RVV_WIDEN_TERNOP = 4, RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */ RVV_SLIDE_OP = 4, /* Dest, VUNDEF, source and offset. */ @@ -260,6 +255,7 @@ void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); void emit_scalar_move_insn (unsigned, rtx *, rtx = 0); void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); enum vlmul_type get_vlmul (machine_mode); +rtx get_vlmax_rtx (machine_mode); unsigned int get_ratio (machine_mode); unsigned int get_nf (machine_mode); machine_mode get_subpart_mode (machine_mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index b783fb8ab00..5ba2f59ef07 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -761,28 +761,6 @@ emit_vlmax_fp_ternary_insn (unsigned icode, int op_num, rtx *ops, rtx vl) e.emit_insn ((enum insn_code) icode, ops); } -/* This function emits a {NONVLMAX, TAIL_UNDISTURBED, MASK_ANY} vsetvli followed - * by the ternary operation which always has a real merge operand. */ -static void -emit_nonvlmax_fp_ternary_tu_insn (unsigned icode, int op_num, rtx *ops, rtx vl) -{ - machine_mode dest_mode = GET_MODE (ops[0]); - machine_mode mask_mode = get_mask_mode (dest_mode); - insn_expander e (/*OP_NUM*/ op_num, - /*HAS_DEST_P*/ true, - /*FULLY_UNMASKED_P*/ false, - /*USE_REAL_MERGE_P*/ true, - /*HAS_AVL_P*/ true, - /*VLMAX_P*/ false, - /*DEST_MODE*/ dest_mode, - /*MASK_MODE*/ mask_mode); - e.set_policy (TAIL_UNDISTURBED); - e.set_policy (MASK_ANY); - e.set_rounding_mode (FRM_DYN); - e.set_vl (vl); - e.emit_insn ((enum insn_code) icode, ops); -} - /* This function emits a {NONVLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the * actual operation. */ void @@ -1208,8 +1186,8 @@ emit_vlmax_masked_gather_mu_insn (rtx target, rtx op, rtx sel, rtx mask) } else icode = code_for_pred_gather (data_mode); - rtx ops[] = {target, mask, target, op, sel}; - emit_vlmax_masked_mu_insn (icode, RVV_BINOP_MU, ops); + rtx ops[RVV_BINOP_MASK] = {target, mask, target, op, sel}; + emit_vlmax_masked_mu_insn (icode, RVV_BINOP_MASK, ops); } /* According to RVV ISA spec (16.5.1. Synthesizing vdecompress): @@ -1858,6 +1836,14 @@ get_vlmul (machine_mode mode) return mode_vtype_infos.vlmul[mode]; } +/* Return the VLMAX rtx of vector mode MODE. */ +rtx +get_vlmax_rtx (machine_mode mode) +{ + gcc_assert (riscv_v_ext_vector_mode_p (mode)); + return gen_int_mode (GET_MODE_NUNITS (mode), Pmode); +} + /* Return the NF value of the corresponding mode. */ unsigned int get_nf (machine_mode mode) @@ -3415,7 +3401,7 @@ expand_load_store (rtx *ops, bool is_load) if (is_load) { rtx m_ops[] = {ops[0], mask, RVV_VUNDEF (mode), ops[1]}; - emit_vlmax_masked_insn (code_for_pred_mov (mode), RVV_UNOP_M, m_ops); + emit_vlmax_masked_insn (code_for_pred_mov (mode), RVV_UNOP_MASK, m_ops); } else { @@ -3432,7 +3418,7 @@ expand_load_store (rtx *ops, bool is_load) if (is_load) { rtx m_ops[] = {ops[0], mask, RVV_VUNDEF (mode), ops[1]}; - emit_nonvlmax_masked_insn (code_for_pred_mov (mode), RVV_UNOP_M, + emit_nonvlmax_masked_insn (code_for_pred_mov (mode), RVV_UNOP_MASK, m_ops, len); } else @@ -3451,32 +3437,26 @@ needs_fp_rounding (rtx_code code, machine_mode mode) return code != SMIN && code != SMAX && code != NEG && code != ABS; } -/* Expand unary ops COND_LEN_*. */ -void -expand_cond_len_unop (rtx_code code, rtx *ops) +/* Subroutine to expand COND_LEN_* patterns. */ +static void +expand_cond_len_op (rtx_code code, unsigned icode, int op_num, rtx *cond_ops, + rtx len) { - rtx dest = ops[0]; - rtx mask = ops[1]; - rtx src = ops[2]; - rtx merge = ops[3]; - rtx len = ops[4]; + rtx dest = cond_ops[0]; + rtx mask = cond_ops[1]; machine_mode mode = GET_MODE (dest); machine_mode mask_mode = GET_MODE (mask); - poly_int64 value; bool is_dummy_mask = rtx_equal_p (mask, CONSTM1_RTX (mask_mode)); bool is_vlmax_len = poly_int_rtx_p (len, &value) && known_eq (value, GET_MODE_NUNITS (mode)); - rtx cond_ops[] = {dest, mask, merge, src}; - insn_code icode = code_for_pred (code, mode); - if (is_dummy_mask) { /* Use TU, MASK ANY policy. */ if (needs_fp_rounding (code, mode)) - emit_nonvlmax_fp_tu_insn (icode, RVV_UNOP_TU, cond_ops, len); + emit_nonvlmax_fp_tu_insn (icode, op_num, cond_ops, len); else - emit_nonvlmax_tu_insn (icode, RVV_UNOP_TU, cond_ops, len); + emit_nonvlmax_tu_insn (icode, op_num, cond_ops, len); } else { @@ -3484,21 +3464,37 @@ expand_cond_len_unop (rtx_code code, rtx *ops) { /* Use TAIL ANY, MU policy. */ if (needs_fp_rounding (code, mode)) - emit_vlmax_masked_fp_mu_insn (icode, RVV_UNOP_MU, cond_ops); + emit_vlmax_masked_fp_mu_insn (icode, op_num, cond_ops); else - emit_vlmax_masked_mu_insn (icode, RVV_UNOP_MU, cond_ops); + emit_vlmax_masked_mu_insn (icode, op_num, cond_ops); } else { /* Use TU, MU policy. */ if (needs_fp_rounding (code, mode)) - emit_nonvlmax_fp_tumu_insn (icode, RVV_UNOP_TUMU, cond_ops, len); + emit_nonvlmax_fp_tumu_insn (icode, op_num, cond_ops, len); else - emit_nonvlmax_tumu_insn (icode, RVV_UNOP_TUMU, cond_ops, len); + emit_nonvlmax_tumu_insn (icode, op_num, cond_ops, len); } } } +/* Expand unary ops COND_LEN_*. */ +void +expand_cond_len_unop (rtx_code code, rtx *ops) +{ + rtx dest = ops[0]; + rtx mask = ops[1]; + rtx src = ops[2]; + rtx merge = ops[3]; + rtx len = ops[4]; + + machine_mode mode = GET_MODE (dest); + insn_code icode = code_for_pred (code, mode); + rtx cond_ops[RVV_UNOP_MASK] = {dest, mask, merge, src}; + expand_cond_len_op (code, icode, RVV_UNOP_MASK, cond_ops, len); +} + /* Expand binary ops COND_LEN_*. */ void expand_cond_len_binop (rtx_code code, rtx *ops) @@ -3509,43 +3505,11 @@ expand_cond_len_binop (rtx_code code, rtx *ops) rtx src2 = ops[3]; rtx merge = ops[4]; rtx len = ops[5]; - machine_mode mode = GET_MODE (dest); - machine_mode mask_mode = GET_MODE (mask); - poly_int64 value; - bool is_dummy_mask = rtx_equal_p (mask, CONSTM1_RTX (mask_mode)); - bool is_vlmax_len - = poly_int_rtx_p (len, &value) && known_eq (value, GET_MODE_NUNITS (mode)); - rtx cond_ops[] = {dest, mask, merge, src1, src2}; + machine_mode mode = GET_MODE (dest); insn_code icode = code_for_pred (code, mode); - - if (is_dummy_mask) - { - /* Use TU, MASK ANY policy. */ - if (needs_fp_rounding (code, mode)) - emit_nonvlmax_fp_tu_insn (icode, RVV_BINOP_TU, cond_ops, len); - else - emit_nonvlmax_tu_insn (icode, RVV_BINOP_TU, cond_ops, len); - } - else - { - if (is_vlmax_len) - { - /* Use TAIL ANY, MU policy. */ - if (needs_fp_rounding (code, mode)) - emit_vlmax_masked_fp_mu_insn (icode, RVV_BINOP_MU, cond_ops); - else - emit_vlmax_masked_mu_insn (icode, RVV_BINOP_MU, cond_ops); - } - else - { - /* Use TU, MU policy. */ - if (needs_fp_rounding (code, mode)) - emit_nonvlmax_fp_tumu_insn (icode, RVV_BINOP_TUMU, cond_ops, len); - else - emit_nonvlmax_tumu_insn (icode, RVV_BINOP_TUMU, cond_ops, len); - } - } + rtx cond_ops[RVV_BINOP_MASK] = {dest, mask, merge, src1, src2}; + expand_cond_len_op (code, icode, RVV_BINOP_MASK, cond_ops, len); } /* Prepare insn_code for gather_load/scatter_store according to @@ -3711,42 +3675,14 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) { rtx dest = ops[0]; rtx mask = ops[1]; + rtx src1 = ops[2]; + rtx src2 = ops[3]; + rtx src3 = ops[4]; + rtx merge = ops[5]; rtx len = ops[6]; - machine_mode mode = GET_MODE (dest); - machine_mode mask_mode = GET_MODE (mask); - - poly_int64 value; - bool is_dummy_mask = rtx_equal_p (mask, CONSTM1_RTX (mask_mode)); - bool is_vlmax_len - = poly_int_rtx_p (len, &value) && known_eq (value, GET_MODE_NUNITS (mode)); - if (is_dummy_mask) - { - /* Use TU, MASK ANY policy. */ - if (FLOAT_MODE_P (mode)) - emit_nonvlmax_fp_ternary_tu_insn (icode, RVV_TERNOP_TU, ops, len); - else - emit_nonvlmax_tu_insn (icode, RVV_TERNOP_TU, ops, len); - } - else - { - if (is_vlmax_len) - { - /* Use TAIL ANY, MU policy. */ - if (FLOAT_MODE_P (mode)) - emit_vlmax_masked_fp_mu_insn (icode, RVV_TERNOP_MU, ops); - else - emit_vlmax_masked_mu_insn (icode, RVV_TERNOP_MU, ops); - } - else - { - /* Use TU, MU policy. */ - if (FLOAT_MODE_P (mode)) - emit_nonvlmax_fp_tumu_insn (icode, RVV_TERNOP_TUMU, ops, len); - else - emit_nonvlmax_tumu_insn (icode, RVV_TERNOP_TUMU, ops, len); - } - } + rtx cond_ops[RVV_TERNOP_MASK] = {dest, mask, src1, src2, src3, merge}; + expand_cond_len_op (UNSPEC, icode, RVV_TERNOP_MASK, cond_ops, len); } /* Expand reduction operations. */ @@ -3852,7 +3788,7 @@ expand_lanes_load_store (rtx *ops, bool is_load) { rtx m_ops[] = {reg, mask, RVV_VUNDEF (mode), addr}; emit_vlmax_masked_insn (code_for_pred_unit_strided_load (mode), - RVV_UNOP_M, m_ops); + RVV_UNOP_MASK, m_ops); } else { @@ -3870,7 +3806,7 @@ expand_lanes_load_store (rtx *ops, bool is_load) { rtx m_ops[] = {reg, mask, RVV_VUNDEF (mode), addr}; emit_nonvlmax_masked_insn (code_for_pred_unit_strided_load (mode), - RVV_UNOP_M, m_ops, len); + RVV_UNOP_MASK, m_ops, len); } else emit_insn (gen_pred_unit_strided_store (mode, mask, addr, reg, len,