From patchwork Thu Nov 3 09:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 14774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp410430wru; Thu, 3 Nov 2022 02:17:36 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7pzAXtQgldTZK72VutLy3ceSHKp1c1BhGAonvokyF0mBMjBFBy94Wh+NFnQAV2dKiZKVbS X-Received: by 2002:a63:8aca:0:b0:461:25fe:e7c5 with SMTP id y193-20020a638aca000000b0046125fee7c5mr25548636pgd.395.1667467056476; Thu, 03 Nov 2022 02:17:36 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667467056; cv=pass; d=google.com; s=arc-20160816; b=dT8nkKz+mIHC4vqDlSLNA2nWLhQ0Iq9/9HZaX1UgPBtZyvOW1DgBRxL+rhPt7iOAsX bWpnEYYiXX/qG/LBM0Ngo4Q82vaJ+MrEV9Vqfqka/x57tUIQD1Lc3dPEu3bptCntP5KZ hategJ9ziR4ez9BE1H84zdKzrxwrosKfE1111j4e6HF9S+OnJSpnk3DpbwT1CDhAVjFR 595402V5MgFS8mmRCaJk8Q23fdcxaCqV0Ght5kHVp0HJOWpsiUQXmpaP46iCJifDKatC DMggDz78eD3PuUe0iqiFV4+6YKqXEvTpi9vhYDCBHh/0ynEB+B26x66AiU4Z/vLAk230 sqIA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ytuDHlCqrE1Thh8WIhqk1S74aVMRZtXhdiqCYvNKfFk=; b=sPFdpabT8QqYFoxOnjxBeHgIKU5TZmuVSC9Y42K/exxxfJvw1Wo3YOtkpJW70u2qX4 /TycWwM2tlSt6veQdWUJMeGlw35Ly6NeTaN3NbZqHpNcO2+4fdLds42L1/zRBL+BApKm cFgvQAdgGdxFLYQzKtAyR60LsjsAn/q2Qj7XH3vw/B/k2XnM/rl8tckWAjBKk8L+2oNR OCf7Isia3XgolBieR44WlflqRCWgZzw+4HZly23lNN3oqjuhcwsvFSni82vUmx5wWj70 ncR+AnIxHX/Es7v5b/l2q6OXIZi+kd6ADKHVD8INl2VHnXe0dB5SemuTEvFFQ2SDD/jP XS/Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=uBBshaXl; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 134-20020a63018c000000b0045a8b142a48si356778pgb.657.2022.11.03.02.17.23; Thu, 03 Nov 2022 02:17:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=uBBshaXl; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231532AbiKCJQa (ORCPT + 99 others); Thu, 3 Nov 2022 05:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231493AbiKCJQB (ORCPT ); Thu, 3 Nov 2022 05:16:01 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2062.outbound.protection.outlook.com [40.107.220.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1D1610555; Thu, 3 Nov 2022 02:15:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OzvSkD2qpi1Sog/8MYJ1fsQqYJbsaDtbd53+EghW5usIqFdnMK9u40k9q+69Y6C7XsM2Wh0omdtorO5hBt5keS3gmQqYioJ+TXAYZ1aJtjQzUez4D7fsXuTAZMyrPKV0O7EhZun1EwxtEMcjx4Q8UAcAmBcF5+rVyb1hD8q/EZ4kXxzMxX6Wtvt/Tx5u6cSM4gQzIjIUuMFxsMKM0WPqCIyTKQa5KA2vkjlrmAvWBTbX5+e5jyvq7MRU5BVw/p5E0jK2n4djEYACIjxMW546742KC53gPz2H6ODm2zgP0eh3hw0MG2nPLoIqTH1S/y4i6zDpka4JRPYhQx3B9ULxaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ytuDHlCqrE1Thh8WIhqk1S74aVMRZtXhdiqCYvNKfFk=; b=IwVzUNBcBN/m1WDbxQd72ncFlcnaamaNU8OI7rRctNnl/29JtnIKQkTHavCkSdSwQ5cGvtsXHKs8Oae1hYOLrGF5oAi23wi74I4EeAX40iO54Ou9BuIiZi+Em/WOEEKywyado3fgW3ux1U9KJ3ryoKbuS2sp2qQ+J8qpDc2gr4zS9lbNEihF0pEqfV5Ny2ejGj+HaUCWCHGXq6d65WuLDXpCvA/xkk3ivECTBk6nLVMkcxYpABMrHE9HJvZdAeXnOrw6rBUtn8zx/ojWiWfcIjOoJnGX+dBKH9Z4/mX9vQ34yYFZzv4hA9uGu8E+qzvJg+rTTiPxriUaXMaJYVD2EQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ytuDHlCqrE1Thh8WIhqk1S74aVMRZtXhdiqCYvNKfFk=; b=uBBshaXlOCZXjVy7SyUMrUXb/3zZPpOTn39P6IcV+QZE4asI4HOqk6A+rX1hdeRI9mPqFOvAevMZyFwaHBziW9oGI9LpHNg/kW9lOn/r758QFKXWT3fEKEp3T4sKrlYw6mVlokHIrZz50TCVUa44stLoB0HzU1FAlOmTYOLsPDg= Received: from BN8PR04CA0001.namprd04.prod.outlook.com (2603:10b6:408:70::14) by MN0PR12MB6319.namprd12.prod.outlook.com (2603:10b6:208:3c0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19; Thu, 3 Nov 2022 09:15:08 +0000 Received: from BN8NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:408:70:cafe::6d) by BN8PR04CA0001.outlook.office365.com (2603:10b6:408:70::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Thu, 3 Nov 2022 09:15:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT053.mail.protection.outlook.com (10.13.177.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Thu, 3 Nov 2022 09:15:08 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Thu, 3 Nov 2022 04:15:06 -0500 From: Appana Durga Kedareswara rao To: , , , , , , , , , , CC: , , Krzysztof Kozlowski Subject: [PATCH v6 1/4] dt-bindings: misc: tmr-manager: Add device-tree binding for TMR Manager Date: Thu, 3 Nov 2022 14:44:57 +0530 Message-ID: <20221103091500.3022212-2-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> References: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT053:EE_|MN0PR12MB6319:EE_ X-MS-Office365-Filtering-Correlation-Id: f4454dc9-5144-49bd-8af8-08dabd7be734 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xOMLabIQWoxZejZPvwr6WhAQhQTjEPNpTMbuOeKfL3QhdKe/6lpnpY9LAneJ4CWFvVYGZvxM7Re0we7bgw+15j4hPWm6stfSz0b7HpH+g1Tkw980zia15sJfAHLXECP6WUM+wmTcqKw5fkpM4LlsVXb/7M3iUjV3QVPlIkMo9+88gZBo7vglUMTDXTzxuhZL3iDftEAayHErL/ZAG/Gkm6b0UC/MPKN8p7vveM8nkucpPsWSqp8uxlphNC6T1dFKPJhTfn2AZLXexLPA0aPK0fT2UpTI/zEiPMzBRuIBoaWxKS12HLVnyaHL7k1YEi7dhgN60T8oPc1/uNWicUbawMNWtBQ+lMAKuRDzUJ7KXMBBsH9IZvqLtpCdVGNTMx13Y47cACwOaDAFN1VoRCzUc+qMhpyccpd2KOmUXByvVlbbUMVUinZZ3bk5GUvOsrKV1mBZFx85W5LArFOAmfDHU5OAXmMLGW178JFedpR/9RGr7NebWbN0YGzrS4Zz+xM+wOyNLshKIyoLwQ7wbH0cuFfM56BHG3qH7OSBFDr0NIXMnA7xJ+gGXi7Dztw2GYzHx6XtMtzl1ea3AVxkAFUqgF3CweLne7dTO7kLk33cHp5mL4FeZ8CTKDDFGFuTWjNubaxAi+V3CN0bCiL3n+Kn2EJLosBZESe8aw7jxCGSu8poIfm9bpd/9vm74pAP8Qr3fhedHkxuRrsrNlB1q/0mJmkMmqZnHFYzsI5mcvw75akrYZ1emDIdycD1z/8KaKLX6mg+D8beSVAIG70/egaIl81RRtHozCABseESgmd2hw6Uc3omZyVSSbyR5Z1wRK9Z8noeCL7ipT3Ai+ZUuhLUTEzFd1axyZkMVPgnsNnUoQfff+JXvChcj9qzzf/wNzsQUTBJrI13B2RRy7OpGYb/7A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(426003)(36756003)(86362001)(103116003)(921005)(81166007)(82740400003)(356005)(6666004)(1076003)(186003)(16526019)(336012)(40480700001)(40460700003)(2906002)(47076005)(2616005)(110136005)(26005)(478600001)(83380400001)(36860700001)(54906003)(41300700001)(70586007)(82310400005)(966005)(5660300002)(4326008)(316002)(8936002)(70206006)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 09:15:08.3485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4454dc9-5144-49bd-8af8-08dabd7be734 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6319 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748465936306887628?= X-GMAIL-MSGID: =?utf-8?q?1748465936306887628?= Triple Modular Redundancy(TMR) subsystem contains three microblaze cores, subsystem is fault-tolerant and continues to operate nominally after encountering an error. Together with the capability to detect and recover from errors, the implementation ensures the reliability of the entire subsystem. TMR Manager is responsible for performing recovery of the subsystem detects the fault via a break signal it invokes microblaze software break handler which calls the tmr manager driver api to update the error count and status. Signed-off-by: Appana Durga Kedareswara rao Reviewed-by: Krzysztof Kozlowski --- Changes for v6: --> None. Changes for v5: --> None. Changes for v4: --> None. Changes for v3: --> Added Krzysztof Reviewed by. Changes for v2: --> Added minimum and maximum values for xlnx,magic1 property as suggested by Michal. --> Fixed 80 char limit in description as suggested by Michal. .../bindings/misc/xlnx,tmr-manager.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml new file mode 100644 index 000000000000..27de12147a52 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Manager IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Manager is responsible for handling the + TMR subsystem state, including fault detection and error recovery. The core + is triplicated in each of the sub-blocks in the TMR subsystem, and provides + majority voting of its internal state. + +properties: + compatible: + enum: + - xlnx,tmr-manager-1.0 + + reg: + maxItems: 1 + + xlnx,magic1: + minimum: 0 + maximum: 255 + description: + Magic byte 1, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic1 + +additionalProperties: false + +examples: + - | + tmr-manager@44a10000 { + compatible = "xlnx,tmr-manager-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic1 = <0x46>; + }; From patchwork Thu Nov 3 09:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 14775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp410491wru; Thu, 3 Nov 2022 02:17:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4imfAL+UoXOyFpGHPGrwYcP4Hokva6Cl7hK/hxW/e5uSud6Kcoujqzn0Yjfo1m/OUziatp X-Received: by 2002:a17:907:728f:b0:7ad:dcbb:3e7f with SMTP id dt15-20020a170907728f00b007addcbb3e7fmr17004229ejc.535.1667467070320; Thu, 03 Nov 2022 02:17:50 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667467070; cv=pass; d=google.com; s=arc-20160816; b=a0GF0WgXlprJu6q/jV0x0EFSLw1jOYBZKj6c01zdJNKJU9Pqkyvb3Dso63qeqrx+T+ q6gAq1MLt9lXw42IryK28MSFhZUDyAIduWDIrc+BaTQcuudDWL3IB2EANODmV2xmES6a RM8n5S25dqI8HRKu1kFmdXIKHjYY8PYpHbb7Qjk7hylFFgTQ5wc32df4qNBf3y/fuxeM zotAP+KZknTCP2fGYJAaQUHD2GoP01y/vfXWHfz5VzMoW0ziruefzWKjLg+F0GGhVBWj 5k1iDFPVa2Rew+ljPm3KOfBx2cuxaob+LKmzf6srzE3ye313zHSiQgcLwfACBQx1OJyY mjJw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ja4XXTauCBesW80bAsQSj0tNwF8nHtyD1Zo6x92Lfkg=; b=ZAR4ABIbSkHebYwl1hBmBK8vrXqjBkIyA0z8LZYTyR2f89i+OpZjnGB+3cr5nKLMMI gguoqr2feiKWfs5PV310FnRocB1utlkBlzTnIegtj/YW0txi02MqKTBsPnKd9uMi/ZWK euJa0XIQtBk6vB1aiQ7/gzvMBEHPsBT5iFQBeORulc7foVncK2SEW009eTtWz/qAhTKL q5PWFH7dQ/YP3BEAYR33GDNGfOf/MTQa9ZWJxmjoB3pkd+u8QNSzryJLVdNY+af8EUX7 oGReUoqEuO4cuDn9nM3dCbCMC2YWQ9MQkPkaKRNm17hMYFD9qwU0TRIKtypCCODaIZZd AYUQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=vctzCqqA; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n17-20020aa7c691000000b0046107f951f9si529991edq.237.2022.11.03.02.17.26; Thu, 03 Nov 2022 02:17:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=vctzCqqA; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231540AbiKCJQm (ORCPT + 99 others); Thu, 3 Nov 2022 05:16:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231144AbiKCJQF (ORCPT ); Thu, 3 Nov 2022 05:16:05 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2061.outbound.protection.outlook.com [40.107.243.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 650DC1055C; Thu, 3 Nov 2022 02:15:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CKluBpEiUcENWrFzkMdTu7ldAkItudP7qa4WrXPDshsWjeTCL4T1eCRA9nuK+04Ub3W/ZVz8Y85JmTSNlxMH+UzjI+GOowOxdV5XfxVMvfb3lF+/XUySFcCoZhmW58QveXSVD9gyBFOnlIpbfbMU0xS3nT5EyEeeXg/mNcfwEPtL4eYOirkHdhjDckM0/nAdAaZjnf58nw9Yg928kUAPBHBdOhhudG8XBjw2/cGC6FgXNmzLDutVvYD+71KwPXkjUP33ozOFYbuecd+gR1bgh0+oCnhyCGx6nk0tB5JNq6F4E6bDC9aHdF8KAF4VTQkUaeNje5qDgPZUjtVk7/4mCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ja4XXTauCBesW80bAsQSj0tNwF8nHtyD1Zo6x92Lfkg=; b=aLyICLIB33AFRoVdRqYOK4EDbth1Bg9v30Mkpc9fRwk9ijIT0bIVnN/xqd+S9KfXCdWIuHtfgsD7e8XcD3su0ypYbB2/JV5Sb5DEJvvzS6TNvufL+vgF7SMQbeClbXg6czxQcNA6SLRK0gzlgeNw3OaByedB6MmXzSDNFyUSkOjnlLS37ogZbHGjKeezaVZLoydQHXJy7NhCRnNMBTUUCOudR41nQUwZslXEBdeimRWw77PTK/5Nct/YNJv9GX7BuEAHZ3WezaOUa6qV+UYnP08hVVYfLkNQWiG9k7u9pW3/Ek+eouI9v24tm42Rsg3u8Gc5rNczpNiOCXt/UTjK1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ja4XXTauCBesW80bAsQSj0tNwF8nHtyD1Zo6x92Lfkg=; b=vctzCqqAp3IH8DzIpMGHsSEBzKVT2GP5ZMDxBIBOCJdH2yu92VWDRrilSJQLVIzIIjF4PIunYvfTs2YDhaNJVX8e34rNBetpA0lIJHOpyhBhNPoVRD3Hh6xIlf3VRKD13nIIQIbx+bWBkyHYQWN86/4FE17+cpRnjFVZAYY1ow0= Received: from BN9PR03CA0077.namprd03.prod.outlook.com (2603:10b6:408:fc::22) by BL1PR12MB5379.namprd12.prod.outlook.com (2603:10b6:208:317::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22; Thu, 3 Nov 2022 09:15:12 +0000 Received: from BN8NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:408:fc:cafe::97) by BN9PR03CA0077.outlook.office365.com (2603:10b6:408:fc::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Thu, 3 Nov 2022 09:15:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Thu, 3 Nov 2022 09:15:11 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Thu, 3 Nov 2022 04:15:10 -0500 From: Appana Durga Kedareswara rao To: , , , , , , , , , , CC: , , kernel test robot Subject: [PATCH v6 2/4] drivers: misc: Add Support for TMR Manager Date: Thu, 3 Nov 2022 14:44:58 +0530 Message-ID: <20221103091500.3022212-3-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> References: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|BL1PR12MB5379:EE_ X-MS-Office365-Filtering-Correlation-Id: 55aadd53-aad3-4585-2abd-08dabd7be961 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hMbiBFpP2Cug0bXXsekZE0E5YzGTiBx2duudtLYqltuWcTIfIJ6H8/TCk0Agca8El5lzDk9fTCzX0pIeiImt9fGKZz3PLBUeIBYuSOtVJmLN0AwMD/GweT+4OMLoNBRgMrdQ2HtlI+RAomwV/Cjt/CJFbgMdvCL3Va/p4eqgWZ+RnA6QrvVtV+wXKPr9kkr++BnbCBTLBJ5gRrOzwhAHxJzfMdcw4rQiCDXrfrPK5/ppWEvp5yyWptEDkb57QlkKpGZwto5LZ1fpR8bHQCijxo3CdEPyuPIaXoFM2h61/BGvqORmrvXKI1PvXiFq9GDHdYupdze4Lj+xn8QGpMEO3ZQiUBNgG3VplcpzsoFsfoJSusDXmsKnoErAFchQNgXPHVFA4h7Gm8cn488lDOUx14g1Fwyj6DaFMYWfKbeGANoEueG6O8Zl7x98WmaJILFP3MS/ILZDJMPpNQdg9zNxeC8QMnnYph40ubc0ZVg5mLkc6RW/V17r73cegG9XRb+p8H8EI8p83gZ9YMJsaD4ZKkoZEvJLwBxRJZo8VU0t0qK6vAt5S2Mqz2k9aOxFatLVdIUlW2aEDl8hOgYx509MjKpfvKSNkpT9mxq+d310XPeFEzdsLQJspXHRwXtnu4wgQWxUT2HtWpT5b0Ftwk6gNwX21ymQjIKoxusBOtxp3dSrmuLQmtpWoiSCUa7m2STNE8SVKUdpA9gKIe8KitvkpOK0l93K4kTeqjLDK3nZ8Qu/WB3iCnGEUyGvPT4RrgffNYKcnmSw7jrqRG+X/q5N1TxUlOpwCCOMVJ4bxsnp4XV6X7MVf9FLUyKoIshdmx0RmZg4VW5aDPo0nsg6RLr1Y8Jgd8WDPqtHHiRKZEfh87E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199015)(36840700001)(40470700004)(46966006)(82740400003)(40460700003)(36860700001)(316002)(54906003)(8676002)(110136005)(86362001)(103116003)(4326008)(16526019)(81166007)(921005)(356005)(1076003)(26005)(83380400001)(8936002)(186003)(426003)(478600001)(966005)(6666004)(2616005)(336012)(70206006)(41300700001)(70586007)(82310400005)(30864003)(2906002)(47076005)(5660300002)(40480700001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 09:15:11.9964 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55aadd53-aad3-4585-2abd-08dabd7be961 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5379 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748465950413794178?= X-GMAIL-MSGID: =?utf-8?q?1748465950413794178?= Triple Modular Redundancy(TMR) subsystem contains three microblaze cores, subsystem is fault-tolerant and continues to operate nominally after encountering an error. Together with the capability to detect and recover from errors, the implementation ensures the reliability of the entire subsystem. TMR Manager is responsible for performing recovery of the subsystem detects the fault via a break signal it invokes microblaze software break handler which calls the tmr manager driver api to update the error count and status, added support for fault detection feature via sysfs interface. Usage: To know the break handler count(Error count): cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt Signed-off-by: Appana Durga Kedareswara rao Reported-by: kernel test robot --- Changes for v6: --> None. Changes for v5: --> Fixed Unexpected indentation htmldoc warning in sysfs-driver-xilinx-tmr-manager. --> Removed sysfs references from the Kconfig description. Changes for v4: --> None. Changes for v3: --> Added Krzysztof Reviewed by. Changes for v2: --> Added minimum and maximum values for xlnx,magic1 property as suggested by Michal. --> Fixed 80 char limit in description as suggested by Michal. .../testing/sysfs-driver-xilinx-tmr-manager | 16 ++ MAINTAINERS | 7 + drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_manager.c | 220 ++++++++++++++++++ 5 files changed, 254 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager create mode 100644 drivers/misc/xilinx_tmr_manager.c diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager new file mode 100644 index 000000000000..57b9b68a73ee --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager @@ -0,0 +1,16 @@ +What: /sys/devices/platform/amba_pl//errcnt +Date: Nov 2022 +Contact: appana.durga.kedareswara.rao@amd.com +Description: This control file provides the fault detection count. + This file cannot be written. + Example: + # cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt + 1 + +What: /sys/devices/platform/amba_pl//dis_block_break +Date: Nov 2022 +Contact: appana.durga.kedareswara.rao@amd.com +Description: Write any value to it, This control file enables the break signal. + This file is write only. + Example: + # echo > /sys/devices/platform/amba_pl/44a10000.tmr_manager/dis_block_break diff --git a/MAINTAINERS b/MAINTAINERS index 9774e7b07faf..58e165c44019 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13418,6 +13418,13 @@ W: http://www.monstr.eu/fdt/ T: git git://git.monstr.eu/linux-2.6-microblaze.git F: arch/microblaze/ +MICROBLAZE TMR MANAGER +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager +F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml +F: drivers/misc/xilinx_tmr_manager.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 358ad56f6524..a61445008f9e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -496,6 +496,16 @@ config VCPU_STALL_DETECTOR If you do not intend to run this kernel as a guest, say N. +config TMR_MANAGER + tristate "Select TMR Manager" + depends on MICROBLAZE && MB_MANAGER + help + This option enables the driver developed for TMR Manager. + The Triple Modular Redundancy(TMR) manager provides support for + fault detection. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index ac9b3e757ba1..b93b782a52f4 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -62,3 +62,4 @@ obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) += open-dice.o obj-$(CONFIG_GP_PCI1XXXX) += mchp_pci1xxxx/ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o +obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o diff --git a/drivers/misc/xilinx_tmr_manager.c b/drivers/misc/xilinx_tmr_manager.c new file mode 100644 index 000000000000..535f723c1a5a --- /dev/null +++ b/drivers/misc/xilinx_tmr_manager.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx TMR Subsystem. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Manager,The Triple Modular Redundancy(TMR) + * Manager is responsible for handling the TMR subsystem state, including + * fault detection and error recovery. The core is triplicated in each of + * the sub-blocks in the TMR subsystem, and provides majority voting of + * its internal state provides soft error detection, correction and + * recovery. + */ + +#include +#include +#include + +/* TMR Manager Register offsets */ +#define XTMR_MANAGER_CR_OFFSET 0x0 +#define XTMR_MANAGER_FFR_OFFSET 0x4 +#define XTMR_MANAGER_CMR0_OFFSET 0x8 +#define XTMR_MANAGER_CMR1_OFFSET 0xC +#define XTMR_MANAGER_BDIR_OFFSET 0x10 +#define XTMR_MANAGER_SEMIMR_OFFSET 0x1C + +/* Register Bitmasks/shifts */ +#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0) +#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8) +#define XTMR_MANAGER_CR_RIR_MASK BIT(16) +#define XTMR_MANAGER_FFR_LM12_MASK BIT(0) +#define XTMR_MANAGER_FFR_LM13_MASK BIT(1) +#define XTMR_MANAGER_FFR_LM23_MASK BIT(2) + +#define XTMR_MANAGER_CR_MAGIC2_SHIFT 4 +#define XTMR_MANAGER_CR_RIR_SHIFT 16 +#define XTMR_MANAGER_CR_BB_SHIFT 18 + +#define XTMR_MANAGER_MAGIC1_MAX_VAL 255 + +/** + * struct xtmr_manager_dev - Driver data for TMR Manager + * @regs: device physical base address + * @cr_val: control register value + * @magic1: Magic 1 hardware configuration value + * @err_cnt: error statistics count + * @phys_baseaddr: Physical base address + */ +struct xtmr_manager_dev { + void __iomem *regs; + u32 cr_val; + u32 magic1; + u32 err_cnt; + resource_size_t phys_baseaddr; +}; + +/* IO accessors */ +static inline void xtmr_manager_write(struct xtmr_manager_dev *xtmr_manager, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_manager->regs + addr); +} + +static inline u32 xtmr_manager_read(struct xtmr_manager_dev *xtmr_manager, + u32 addr) +{ + return ioread32(xtmr_manager->regs + addr); +} + +static void xmb_manager_reset_handler(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the FFR Register contents as a part of recovery process. */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_FFR_OFFSET, 0); +} + +static void xmb_manager_update_errcnt(struct xtmr_manager_dev *xtmr_manager) +{ + xtmr_manager->err_cnt++; +} + +static ssize_t errcnt_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%x\n", xtmr_manager->err_cnt); +} +static DEVICE_ATTR_RO(errcnt); + +static ssize_t dis_block_break_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + int ret; + long value; + + ret = kstrtoul(buf, 16, &value); + if (ret) + return ret; + + /* unblock the break signal*/ + xtmr_manager->cr_val &= ~(1 << XTMR_MANAGER_CR_BB_SHIFT); + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + return size; +} +static DEVICE_ATTR_WO(dis_block_break); + +static struct attribute *xtmr_manager_dev_attrs[] = { + &dev_attr_dis_block_break.attr, + &dev_attr_errcnt.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_manager_dev); + +static void xtmr_manager_init(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the SEM interrupt mask register to disable the interrupt */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_SEMIMR_OFFSET, 0); + + /* Allow recovery reset by default */ + xtmr_manager->cr_val = (1 << XTMR_MANAGER_CR_RIR_SHIFT) | + xtmr_manager->magic1; + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + /* + * Configure Break Delay Initialization Register to zero so that + * break occurs immediately + */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_BDIR_OFFSET, 0); + + /* + * To come out of break handler need to block the break signal + * in the tmr manager, update the xtmr_manager cr_val for the same + */ + xtmr_manager->cr_val |= (1 << XTMR_MANAGER_CR_BB_SHIFT); + + /* + * When the break vector gets asserted because of error injection, + * the break signal must be blocked before exiting from the + * break handler, Below api updates the TMR manager address and + * control register and error counter callback arguments, + * which will be used by the break handler to block the + * break and call the callback function. + */ + xmb_manager_register(xtmr_manager->phys_baseaddr, xtmr_manager->cr_val, + (void *)xmb_manager_update_errcnt, + xtmr_manager, (void *)xmb_manager_reset_handler); +} + +/** + * xtmr_manager_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_manager_probe(struct platform_device *pdev) +{ + struct xtmr_manager_dev *xtmr_manager; + struct resource *res; + int err; + + xtmr_manager = devm_kzalloc(&pdev->dev, sizeof(*xtmr_manager), + GFP_KERNEL); + if (!xtmr_manager) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xtmr_manager->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xtmr_manager->regs)) + return PTR_ERR(xtmr_manager->regs); + + xtmr_manager->phys_baseaddr = res->start; + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic1", + &xtmr_manager->magic1); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic1 property"); + return err; + } + + if (xtmr_manager->magic1 > XTMR_MANAGER_MAGIC1_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic1 property value"); + return -EINVAL; + } + + /* Initialize TMR Manager */ + xtmr_manager_init(xtmr_manager); + + platform_set_drvdata(pdev, xtmr_manager); + + return 0; +} + +static const struct of_device_id xtmr_manager_of_match[] = { + { + .compatible = "xlnx,tmr-manager-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_manager_of_match); + +static struct platform_driver xtmr_manager_driver = { + .driver = { + .name = "xilinx-tmr_manager", + .of_match_table = xtmr_manager_of_match, + .dev_groups = xtmr_manager_dev_groups, + }, + .probe = xtmr_manager_probe, +}; +module_platform_driver(xtmr_manager_driver); + +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Manager Driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Nov 3 09:14:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 14776 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp410659wru; Thu, 3 Nov 2022 02:18:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5+pOlR2KN/Gwiah/3xmjcjY+Gqhw3o8J3NJJWQ068FgWKs+6QwPWAZOKwlVdG992Zht7Wo X-Received: by 2002:a17:90b:4f8f:b0:20d:be54:f34f with SMTP id qe15-20020a17090b4f8f00b0020dbe54f34fmr47898429pjb.245.1667467096639; Thu, 03 Nov 2022 02:18:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667467096; cv=pass; d=google.com; s=arc-20160816; b=U9983iAVzDDDc+WIqYdHUl2Y4Nqmf17dcEkyDCWxDo5XP/wy8HvN59n5R7wbQEXtc4 lSRNBvRg1+7GjGLTLXES46lLEBkk3fMcliWaakNMzM+z0lC6xdnShe4yvjUqZNiwR60+ ho9TPDfhtg/LyT+AbV2qLFeFkqy9qVPatBOf0BGxy/nBn98RSCn2Xir5OK05KlZmC56S a9UIZJ3wmZSIAjBH/KnnIDlJ7oh7Jr3zWnyur7xw7CvJnPhkDw6O55vXAcv5B6A2HRPM qJIknyD2RyEqQK9JInlkhxAahfm6bxue56QF5hcqJ0zns1iYvjldym4bDxigCCwciecZ hiCg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hHtMISjAUh88XQJ+Sbf7Q/fUipkib6inFp5wFiXb/KY=; b=TZoPK/FCJrxqm971cL4bzV5ZBMo/UB0Y23BRoiyXWnXyA7jEw396ZN7qTXvZ8b0m4f i0xNUt1wTRYLLAFLLbqPF7+ljQ1V3qvvVHg9pNcvi99htavVVkK+mViE+UdCEizC0toP a1neOoQ3cRoFu7BAXJ6J+0+hJO3CrOXV3j5LRUZP3jzn0eewPV0XldT51KVSAldWTiAV QAqBRL1Jrem6Hh6V2BA7MaLzNFJj69LsXXfALjMaFuZn3EqTcXMDN/HdCK6UTL6JF9OH /OoRLqtVUptGNBrzkodYcbVjANARdwy20SXLwN6K/8MKjWIzg/kYFGxiI0mhRxbebkS4 smLw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=c3co4+HV; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i5-20020a63e445000000b0046eecbac482si437467pgk.415.2022.11.03.02.18.00; Thu, 03 Nov 2022 02:18:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=c3co4+HV; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231539AbiKCJRX (ORCPT + 99 others); Thu, 3 Nov 2022 05:17:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231561AbiKCJQo (ORCPT ); Thu, 3 Nov 2022 05:16:44 -0400 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2060.outbound.protection.outlook.com [40.107.101.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E437DE8F; Thu, 3 Nov 2022 02:16:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EDAdunosqZD6+QyOzMSg6bHuJ5du+nuTljXW+yNhtXfpM7Jr2h0oWYcjALhRmCmBtYogd4xM1FOKrFiOBkT8FH1v+6G7rkJkqJBlyBuUtsGD0dBBfCBE6zlqvErx+kp/ocUf9BKUDCo2NWEOqBaIyMk0/Q72mvk4mwY1RW0PrrZLoDdr2e+msToh0jd23DogCGjeeVJF2RvjjVXA2Mt3fvA7VKp4EdgbPWQPzl4PzhsUW6Wbk3/v13JjijarQOxP50Pj7Hre6ZKnhiANqy26GonDr9xqEUaqjCdv0N99kqOphjuMiK62i5uGmfaL9maajy8IOXrnZ9FdkInFa7609A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hHtMISjAUh88XQJ+Sbf7Q/fUipkib6inFp5wFiXb/KY=; b=i/MGhRJV+LpcbCW+hWDCcP3A7Z5vhmYr8CIoO+JrbfXwRJCXtIZbCdoA7uV8Buibtp8QghvRHB5KXd5pB0j4XY7geH7fKoLXC8LoyJBOJCExjHRz25QKwK+u3W64WID5Pupx5hfcrHMh1y9nlTeBLKU2m8brD0EII+9Lrz7X0SSrNGB1TrhUoP/LwCmFaKMK2xbVmeannJe2rVSQzCRrRubE702vKovhIvGJgV7TUH3GCjPD7MuxIZImEmrY93/DBVGUgmdsqJ/RCiKDBty3Fj8d3GXs29tHtcX9LGPfP0/kkzDPWgZRkZ2Rg6CD+LlbSUrcBsfSSJtgWJRq1TMiOg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hHtMISjAUh88XQJ+Sbf7Q/fUipkib6inFp5wFiXb/KY=; b=c3co4+HVBKYPQDYTaudNi2d1Rd+HppuE9q86GmqK8+91SHZCYVAXa85nSwpsz3QF9r/6itAx01JW39C0DmeEtFb2xbV0evK4V9Sj5ob+tezM5oBvZ1kJBEnCk841uhAS/quFlPl3V8iRDw5kZ48dPihlNm3RFfy7ne7zXzCJTK0= Received: from BN8PR07CA0019.namprd07.prod.outlook.com (2603:10b6:408:ac::32) by MN2PR12MB4078.namprd12.prod.outlook.com (2603:10b6:208:1de::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22; Thu, 3 Nov 2022 09:16:04 +0000 Received: from BN8NAM11FT108.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ac:cafe::21) by BN8PR07CA0019.outlook.office365.com (2603:10b6:408:ac::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Thu, 3 Nov 2022 09:16:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT108.mail.protection.outlook.com (10.13.176.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Thu, 3 Nov 2022 09:16:04 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Thu, 3 Nov 2022 04:15:59 -0500 From: Appana Durga Kedareswara rao To: , , , , , , , , , , CC: , , Krzysztof Kozlowski Subject: [PATCH v6 3/4] dt-bindings: misc: tmr-inject: Add device-tree binding for TMR Inject Date: Thu, 3 Nov 2022 14:44:59 +0530 Message-ID: <20221103091500.3022212-4-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> References: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT108:EE_|MN2PR12MB4078:EE_ X-MS-Office365-Filtering-Correlation-Id: b24357ea-8797-4e7a-7c64-08dabd7c086d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UaXucxfu/3hoiPXnhjhHacusGikcWk1/Go5fwhr7A+pJj/5VbIxhjFA7tthovul8y7Z4giW19L1SHzT6/tZZctHtREF0cKlR68Un7kMcKd422kzNOSrIvkCFwN35awk0IIMJl3g9PzctyrPPiL23TCZCxO7Bnb9VVbmXCMMpLtGLIZnFAgBFlv7H/psqOMfMi3c+wISFERQ9jo0mOfltj8fO9dF3ZdEzTTokFNsQfqQsTZWaiGTK7R1Ucjpvdyae3JCIajNQz7PKD/lEUECpM9hj+Yl6GpR2Ei3XFCT0q5Fg/G3eG5h2zzU3xaevxWO/6et7Wl8ofCnXQEatlciXiPLcjyoSF8SepvBaNOlwjTGwKMY0UjQwQRktfUFy3BZ4qsKIpf3FiPWyoriQIJHHOqCid3Bf4c8kcJU52QYxfvHFqLTrmBWDgO2VTKZxRUfVroh6xM29k+MU317b0AhUG/S5/Li1QrXztcxtPeNss5zYJ2RsFJuy5NAvm98xresVwEBzdt7eivGaRHYmZcx6uKSRh7lwUtGOPNPXcfTytIdplYK8FeUs5UnT+s6LanLtjwV2kfFaoZy+f7AKeMF7KB9dQy0TfU4VhFfrUnNA8+YBlyPE+MIShwykw9Fr+csCATpvVmiLGkWuNru9u6Xlldl8m1nHx9NJY29suYPkIO9Vezm9DbaVyTRVOLb+6yNRhgijZwavwXfKwg6vQrUOiq01qSroHEijcer2eyRyYMBjBV+dmPophOO8cQnrgtRhMisJ8pFf3ZCsSCgCuyH/JLZ/lXKb2OY8obRsui6WPFo6ZQBvaUbW9wguXIfbVlkqWfOJ1pI3SC3+TM32OlMGmeDhHDYonbxlea2OKlMo+6GrPJzk15gytULDHn8ayWqVwl0pUN4/U1E+ZBRy3MFGLQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(40480700001)(26005)(8936002)(86362001)(186003)(1076003)(16526019)(40460700003)(2616005)(5660300002)(478600001)(336012)(426003)(47076005)(966005)(4326008)(70206006)(70586007)(8676002)(82740400003)(110136005)(81166007)(356005)(83380400001)(36756003)(41300700001)(103116003)(316002)(921005)(54906003)(36860700001)(82310400005)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 09:16:04.0865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b24357ea-8797-4e7a-7c64-08dabd7c086d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4078 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748465978723591526?= X-GMAIL-MSGID: =?utf-8?q?1748465978723591526?= The Triple Modular Redundancy(TMR) Inject core provides functional fault injection by changing selected MicroBlaze instructions, which provides the possibility to verify that the TMR subsystem error detection and fault recovery logic is working properly. Signed-off-by: Appana Durga Kedareswara rao Reviewed-by: Krzysztof Kozlowski --- Changes for v6: --> None. Changes for v5: --> None. Changes for v4: --> None. Changes for v3: --> Added Krzysztof Reviewed by. Changes for v2: --> Added minimum and maximum values for xlnx,magic1 property as suggested by Michal. --> Fixed 80 char limit in description as suggested by Michal. .../bindings/misc/xlnx,tmr-inject.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml new file mode 100644 index 000000000000..1b6020e4ec27 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Inject IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Inject core provides functional fault + injection by changing selected MicroBlaze instructions, which provides the + possibility to verify that the TMR subsystem error detection and fault + recovery logic is working properly. + +properties: + compatible: + enum: + - xlnx,tmr-inject-1.0 + + reg: + maxItems: 1 + + xlnx,magic: + minimum: 0 + maximum: 255 + description: | + Magic number, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic + +additionalProperties: false + +examples: + - | + fault-inject@44a30000 { + compatible = "xlnx,tmr-inject-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic = <0x46>; + }; From patchwork Thu Nov 3 09:15:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 14777 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp410955wru; Thu, 3 Nov 2022 02:19:03 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5B+PJnqpb2SPRLfxOiZsiTkQfZYy4YngM3iU2RxBypip99OKV16wb+UjzANG95jQ7dlyOP X-Received: by 2002:a17:90a:6909:b0:212:f535:a34b with SMTP id r9-20020a17090a690900b00212f535a34bmr31162395pjj.6.1667467143133; Thu, 03 Nov 2022 02:19:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667467143; cv=pass; d=google.com; s=arc-20160816; b=c7wvFUQbdxUjsTno77mJFWkQrFEKsD11nBtwXvXwncrFf3UbEhVQaW/iJhJzwlz8XH CLxAHbl6eu1X9hgJODtrMKfkjFQJP/t8NkCj/q1K9Ulju4SkieSu6uRvA/tvfnTkFs1O I1qg3iEeS2qS3QiFomnOAZNLymcydKOu2esl5rtoy8m4nRlz01dBJ/M02SxKM+S52irn 4A5Fkn8pvNzIxzCyrY0kTmCAj2tA8evzLCM5dUNsee6gCDU6UlH2CaPw6qRH1znxoWQq k64Umqkj4haAw0PSCrsGHblnchvLkqZ8aAosIH2j2dRdieJ9r1BqzmOBb+8YFzqc3IW9 wMqQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g2OhAGFBdzIH8VoLtRojpAe6IU8trDb5pJh9MxplWN8=; b=TupjT4sFr6Gf84/ks4VM6+aWGJpvkq5sxxBIs9Bo6i+toy4sgPT+KeiW9FtL36U6/v 8zBxLSmZR7LrUvlK1DY2LX4hWcrSG7tyEByYA1a1NpEedoOQB1d4K93y3BqPairJoDvE xKKRtN+NWwCgXcrFiSUI0mNIqWR9xmpL2ILuL8lwmFDZ/ltOublno3fnnyZEqAG7Wy3P CDPgPNrLLRgfI/FAqaT52PqR5hR34azJevraEoYCMqtr7PVW5c3YQU9uCw7fG17MsaTc waX2lOkl4Yh9REzqrSaixDjCaJn8uVe2CTV07xcK7l66+27qKt3KBNurrL1NZHpjKJdx AYtw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ReOTzKFH; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t17-20020a17090aba9100b00213587b200esi510193pjr.189.2022.11.03.02.18.49; Thu, 03 Nov 2022 02:19:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ReOTzKFH; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231561AbiKCJR3 (ORCPT + 99 others); Thu, 3 Nov 2022 05:17:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231258AbiKCJQq (ORCPT ); Thu, 3 Nov 2022 05:16:46 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2060a.outbound.protection.outlook.com [IPv6:2a01:111:f400:7e88::60a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D41B2DF46; Thu, 3 Nov 2022 02:16:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BwleYPoYBw8dr4GLPqvIAScN36T3ZnG+zuk7Tapq1Qe7HgorY55UXb1c7WUf11pB+PQInvVxuIWMAmoD3pcVIq6gqaZyaqLO3u0BOte1H3ovsktYarFg9E2GnigM4+UmCLah496tJ0LT64r5kPpItcJbYpczX3mF/SEKomZoTzf5HC0uGz0GbiYWbBnxkMha3sgYAmzMfpvjLCdeVX3U9F11BywmNVNwBf/sNNUyI8hLxKPTi3U1WvLH/O5hgIK9f8jC3jsD1aDQf1x1Y2L1IezCLO2YywBzH9jGytbL0n/kgnaE1/u3kbG2GboYTvnjwfQOJSZExmMNWLABKN7jFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g2OhAGFBdzIH8VoLtRojpAe6IU8trDb5pJh9MxplWN8=; b=hU2Gg3jED4VDTe/Vltpsl9gTM7yt5nl/5cH8XES7XCOscVzXFNx6a6ebNG7AQP3t/KgiGb/+58MROrEfBYhnIBYDnUM/kdLcyH4AFHJlFAY1zCTbpEVHqR/p92/XL9deiW4sBgnLM2q2hmJrOFgPwsFFtE1KKl4gBEQKu+uL8KkygcQxJaHkVq9/9vCpaGBTrnvmbnAS7tRpMISp13togosMIMJl2XbUTDW0AKmyevr4XjN92f4rbPkd8Aai2Zv15H4L3NghjKaG7OPRerucAEjlFg6nGBPmikggdSGMCx4KusuPbhsqEpRO9QscnCscL2INTHs11dQFnkU//FvlGg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=g2OhAGFBdzIH8VoLtRojpAe6IU8trDb5pJh9MxplWN8=; b=ReOTzKFHUXuNTXKlIv5tR6aG9vvflx0xHk7t88bgYx7Kpa0wS5gY4yaklQPDejG9/zSZEKcr5EiJ0HUGkuyhpTBz7s4/xVvA85nQXe8rV4CFz6Eb8kOFLZRemdv4lRNLkbNuzT3z2GwymGJelG9JFtB/3uvp/uIFOdB3ypozzPc= Received: from BN8PR07CA0030.namprd07.prod.outlook.com (2603:10b6:408:ac::43) by PH0PR12MB7093.namprd12.prod.outlook.com (2603:10b6:510:21d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22; Thu, 3 Nov 2022 09:16:05 +0000 Received: from BN8NAM11FT108.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ac:cafe::4f) by BN8PR07CA0030.outlook.office365.com (2603:10b6:408:ac::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22 via Frontend Transport; Thu, 3 Nov 2022 09:16:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT108.mail.protection.outlook.com (10.13.176.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Thu, 3 Nov 2022 09:16:05 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Thu, 3 Nov 2022 04:16:02 -0500 From: Appana Durga Kedareswara rao To: , , , , , , , , , , CC: , , kernel test robot Subject: [PATCH v6 4/4] drivers: misc: Add Support for TMR Inject IP Date: Thu, 3 Nov 2022 14:45:00 +0530 Message-ID: <20221103091500.3022212-5-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> References: <20221103091500.3022212-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT108:EE_|PH0PR12MB7093:EE_ X-MS-Office365-Filtering-Correlation-Id: a00ac219-b17c-4d14-96fd-08dabd7c092e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fHtE3f/xAhJCOKi3HxYJmnGTEEoGNGYhV7WwWdPPSmosNAJ0SQn2q0HrgUOBSmQaDmRr4O1q+CG8abuYv3NnIZ+A/oI96rJIfm9U8VWsT1uwj1yIg60xDcVBxcuRqm5V/suerdc4Umn1H+Xcn8jBCTlha7nzVv7cmkQc55bp8dUvH0XHC8XWkx/dQ3+SSrY6p0QdAI93vJPdQTRFJ+iPblL39nFkqa9gwlt8eApGdzrnXzuUrLRUFNrLM3HNJEwesAUTa+zyyPX6fiJ0XsREPDG1VgqwePed1r8s4eCi0JvvKQIzcZiIuGvUkYM9TegkjMGMgdp3R4Ku+2PrlIpW3S2LZVESHAwWWV1xjsVfBqjbcwa6OCXErQT8rwp5cpxVjVSXB8qGbwnXeKTmS5GVkG61SCVlIFx+xsHg1wylisUZBJCNpu4TjuoXuNrih3iCQ55tNfOgimQONRf8tI0zthbXDF/SDf/JwSC1PrsVvfRg4CVvVsHXaRZWX7SicDI8gpQYBVa5lWVcqB2IK/TpjrrZASd94ZOAV3QQbijhYJqZjc8EM4CaozjK0ES+MTay43p4rAhWl9ptNTxVfevAU2+s/y3xddbL1FPpGaJjo+uYRtYL3pUXRJPpN1bxIDKrQDv9CK66DfiXutpC3yFiI30Wc5jrwg+Jmn/OjANvHJPpmn14JUMl1s3cWHtZCkWKl5e534kGR3GwhWHVNR+L88+J5/UR0hN+0CRc/653iXNlcGnwlgjp+A95bWpLH2Y9APRoUiy2VyDnc1m9UEI0VSxzYBHsnPFWeXu+QIBwII3LmaxebIjjazY0pSEvrS5x X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199015)(36840700001)(46966006)(40470700004)(82740400003)(36756003)(478600001)(82310400005)(36860700001)(2906002)(40460700003)(4326008)(70206006)(70586007)(356005)(5660300002)(86362001)(8936002)(41300700001)(54906003)(316002)(110136005)(40480700001)(81166007)(921005)(103116003)(8676002)(83380400001)(186003)(336012)(16526019)(426003)(2616005)(1076003)(26005)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 09:16:05.3520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a00ac219-b17c-4d14-96fd-08dabd7c092e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7093 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748466027029456688?= X-GMAIL-MSGID: =?utf-8?q?1748466027029456688?= The Triple Modular Redundancy(TMR) provides functional fault injection by changing selected MicroBlaze instructions, which provides the possibility to verify that the TMR subsystem error detection and fault recovery logic is working properly. Usage: echo 1 > /sys/kernel/debug/xtmr_inject/inject_fault/inject_fault Signed-off-by: Appana Durga Kedareswara rao Reported-by: kernel test robot --- Changes for v6: --> Fixed -Wmissing-prototypes warning reported by kernel test robot. Changes for v5: --> None. Changes for v4: --> Update depends on with FAULT_INJECTION_DEBUG_FS instead of FAULT_INJECTION. Changes for v3: --> Updated the driver to use fault-injection api as suggested by Greg. --> Updated the Kconfig to compile the driver as a module. Changes for v2: --> Fixed Month in the sysfs description. --> Fixed line over 80 char in driver. --> Replaced kstrtol with kstrtoul as suggested by Michal. --> Added error check for xlnx,magic value. MAINTAINERS | 6 ++ drivers/misc/Kconfig | 10 ++ drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_inject.c | 171 +++++++++++++++++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 drivers/misc/xilinx_tmr_inject.c diff --git a/MAINTAINERS b/MAINTAINERS index 58e165c44019..c8c5f18ee001 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13425,6 +13425,12 @@ F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml F: drivers/misc/xilinx_tmr_manager.c +MICROBLAZE TMR INJECT +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml +F: drivers/misc/xilinx_tmr_inject.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a61445008f9e..35a5d333fc37 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -506,6 +506,16 @@ config TMR_MANAGER Say N here unless you know what you are doing. +config TMR_INJECT + tristate "Select TMR Inject" + depends on TMR_MANAGER && FAULT_INJECTION_DEBUG_FS + help + This option enables the driver developed for TMR Inject. + The Triple Modular Redundancy(TMR) Inject provides + fault injection. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b93b782a52f4..b2d8dd39f4d5 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -63,3 +63,4 @@ obj-$(CONFIG_OPEN_DICE) += open-dice.o obj-$(CONFIG_GP_PCI1XXXX) += mchp_pci1xxxx/ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o +obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o diff --git a/drivers/misc/xilinx_tmr_inject.c b/drivers/misc/xilinx_tmr_inject.c new file mode 100644 index 000000000000..d1564519a283 --- /dev/null +++ b/drivers/misc/xilinx_tmr_inject.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Xilinx TMR Inject IP. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Inject IP,The Triple Modular Redundancy(TMR) + * Inject provides fault injection. + */ + +#include +#include +#include +#include + +/* TMR Inject Register offsets */ +#define XTMR_INJECT_CR_OFFSET 0x0 +#define XTMR_INJECT_AIR_OFFSET 0x4 +#define XTMR_INJECT_IIR_OFFSET 0xC +#define XTMR_INJECT_EAIR_OFFSET 0x10 +#define XTMR_INJECT_ERR_OFFSET 0x204 + +/* Register Bitmasks/shifts */ +#define XTMR_INJECT_CR_CPUID_SHIFT 8 +#define XTMR_INJECT_CR_IE_SHIFT 10 +#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16) + +#define XTMR_INJECT_MAGIC_MAX_VAL 255 + +/** + * struct xtmr_inject_dev - Driver data for TMR Inject + * @regs: device physical base address + * @magic: Magic hardware configuration value + */ +struct xtmr_inject_dev { + void __iomem *regs; + u32 magic; +}; + +static DECLARE_FAULT_ATTR(inject_fault); +static char *inject_request; +module_param(inject_request, charp, 0); +MODULE_PARM_DESC(inject_request, "default fault injection attributes"); +static struct dentry *dbgfs_root; + +/* IO accessors */ +static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_inject->regs + addr); +} + +static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject, + u32 addr) +{ + return ioread32(xtmr_inject->regs + addr); +} + +static int xtmr_inject_set(void *data, u64 val) +{ + if (val != 1) + return -EINVAL; + + xmb_inject_err(); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(xtmr_inject_fops, NULL, xtmr_inject_set, "%llu\n"); + +static void xtmr_init_debugfs(struct xtmr_inject_dev *xtmr_inject) +{ + struct dentry *dir; + + dbgfs_root = debugfs_create_dir("xtmr_inject", NULL); + dir = fault_create_debugfs_attr("inject_fault", dbgfs_root, + &inject_fault); + debugfs_create_file("inject_fault", 0200, dir, NULL, + &xtmr_inject_fops); +} + +static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject) +{ + u32 cr_val; + + if (inject_request) + setup_fault_attr(&inject_fault, inject_request); + /* Allow fault injection */ + cr_val = xtmr_inject->magic | + (1 << XTMR_INJECT_CR_IE_SHIFT) | + (1 << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + cr_val); + /* Initialize the address inject and instruction inject registers */ + xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET, + XMB_INJECT_ERR_OFFSET); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET, + XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK); +} + +/** + * xtmr_inject_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_inject_probe(struct platform_device *pdev) +{ + struct xtmr_inject_dev *xtmr_inject; + int err; + + xtmr_inject = devm_kzalloc(&pdev->dev, sizeof(*xtmr_inject), + GFP_KERNEL); + if (!xtmr_inject) + return -ENOMEM; + + xtmr_inject->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(xtmr_inject->regs)) + return PTR_ERR(xtmr_inject->regs); + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic", + &xtmr_inject->magic); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic property"); + return err; + } + + if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic property value"); + return -EINVAL; + } + + /* Initialize TMR Inject */ + xtmr_inject_init(xtmr_inject); + + xtmr_init_debugfs(xtmr_inject); + + platform_set_drvdata(pdev, xtmr_inject); + + return 0; +} + +static int xtmr_inject_remove(struct platform_device *pdev) +{ + debugfs_remove_recursive(dbgfs_root); + dbgfs_root = NULL; + return 0; +} + +static const struct of_device_id xtmr_inject_of_match[] = { + { + .compatible = "xlnx,tmr-inject-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_inject_of_match); + +static struct platform_driver xtmr_inject_driver = { + .driver = { + .name = "xilinx-tmr_inject", + .of_match_table = xtmr_inject_of_match, + }, + .probe = xtmr_inject_probe, + .remove = xtmr_inject_remove, +}; +module_platform_driver(xtmr_inject_driver); +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Inject Driver"); +MODULE_LICENSE("GPL");