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[8.43.85.97]) by mx.google.com with ESMTPS id l15-20020a170906938f00b00991f1e4b03dsi7937097ejx.406.2023.08.23.07.54.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 07:54:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=k6860Q04; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7A8E3385DC11 for ; Wed, 23 Aug 2023 14:54:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A8E3385DC11 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692802444; bh=NMI881AhrquyewRGqJ9Z63JQ55dfWIRYUqpcCO61z9Y=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=k6860Q042yqthszeSl/roZ//zgFJD7pVWcghNuMfUKyLPraP+78UfIKNf75grEeWI ocZzhorzt/ytCk3ZoUpQRWbThCUvCMVmZPAZFB7CiZoIV3N2VjBjiiI1NdKZ1qvDwa mkoc9rQV/B1z1s5rTl1K48bvRNoMchwceHc+5q6A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by sourceware.org (Postfix) with ESMTPS id DF7233858401 for ; Wed, 23 Aug 2023 14:53:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF7233858401 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-5256d74dab9so7104678a12.1 for ; Wed, 23 Aug 2023 07:53:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692802396; x=1693407196; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=NMI881AhrquyewRGqJ9Z63JQ55dfWIRYUqpcCO61z9Y=; b=fT6T4nTesFUPtJHPWfU+pV5QPDLKN0sfX+CvM6AtNTSoaNc9zhNfWC7M6KHm9/XfiI kQenok5bXKZ81IDwhzJO3q8/kMT5I50+PtSg/NrOa3v2e5dyL+GW45S0HKe719r9W/FH NFnfK7ycPoXG4Nh2B81suMAPiqG5gkm75fYgI9U0P5HxTdUUc9ve4eCGBl1FB/Xfrqbf kWRBpbppZs7SYTsnWjzanDE6bxHFf/WP7EGPgIou69GMoejY5cc/pScEhfBGpjynBC08 0PzqJlKgFIlixlJQRQ34Kx/wTHbxymsgNU539F88EmyOkQsE/CUVmW+CNQSj71SNx9SA Lxxg== X-Gm-Message-State: AOJu0Yx3XN9HADdeYSqwz462hHL3cFTvy4qweSO3R75tB3+72cIQxcsk kUU95IhOQuuYODnwqyjcindlaf6RLHb5FUctKy3TaqWAQnmqQg== X-Received: by 2002:aa7:c98c:0:b0:528:925f:413e with SMTP id c12-20020aa7c98c000000b00528925f413emr9886087edt.12.1692802396187; Wed, 23 Aug 2023 07:53:16 -0700 (PDT) MIME-Version: 1.0 Date: Wed, 23 Aug 2023 16:53:05 +0200 Message-ID: Subject: [committed] i386: Fix register spill failure with concat RTX [PR111010] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775032016998352381 X-GMAIL-MSGID: 1775032016998352381 Disable (=&r,m,m) alternative for 32-bit targets. The combination of two memory operands (possibly with complex addressing mode), early clobbered output, frame pointer and PIC registers uses too many registers on a register constrained 32-bit target. Also merge two similar patterns using DWIH mode iterator. PR target/111010 gcc/ChangeLog: * config/i386/i386.md (*concat3_3): Merge pattern from *concatditi3_3 and *concatsidi3_3 using DWIH mode iterator. Disable (=&r,m,m) alternative for 32-bit targets. (*concat3_4): Disable (=&r,m,m) alternative for 32-bit targets. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Also regtested by Rainer on i386-pc-solaris2.11 where the patch fixes the failure. (I didn't find a nice testcase, the test is very sensitive to perturbations in the code.) Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 108f4af8552..50794ed7bed 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12435,17 +12435,16 @@ (define_insn_and_split "*concat3_2" DONE; }) -(define_insn_and_split "*concatditi3_3" - [(set (match_operand:TI 0 "nonimmediate_operand" "=ro,r,r,&r,x") - (any_or_plus:TI - (ashift:TI - (zero_extend:TI - (match_operand:DI 1 "nonimmediate_operand" "r,m,r,m,x")) +(define_insn_and_split "*concat3_3" + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,r,&r,x") + (any_or_plus: + (ashift: + (zero_extend: + (match_operand:DWIH 1 "nonimmediate_operand" "r,m,r,m,x")) (match_operand:QI 2 "const_int_operand")) - (zero_extend:TI - (match_operand:DI 3 "nonimmediate_operand" "r,r,m,m,0"))))] - "TARGET_64BIT - && INTVAL (operands[2]) == 64" + (zero_extend: + (match_operand:DWIH 3 "nonimmediate_operand" "r,r,m,m,0"))))] + "INTVAL (operands[2]) == * BITS_PER_UNIT" "#" "&& reload_completed" [(const_int 0)] @@ -12456,28 +12455,10 @@ (define_insn_and_split "*concatditi3_3" emit_insn (gen_vec_concatv2di (tmp, operands[3], operands[1])); } else - split_double_concat (TImode, operands[0], operands[3], operands[1]); - DONE; -}) - -(define_insn_and_split "*concatsidi3_3" - [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,r,r,&r") - (any_or_plus:DI - (ashift:DI - (zero_extend:DI - (match_operand:SI 1 "nonimmediate_operand" "r,m,r,m")) - (match_operand:QI 2 "const_int_operand")) - (zero_extend:DI - (match_operand:SI 3 "nonimmediate_operand" "r,r,m,m"))))] - "!TARGET_64BIT - && INTVAL (operands[2]) == 32" - "#" - "&& reload_completed" - [(const_int 0)] -{ - split_double_concat (DImode, operands[0], operands[3], operands[1]); + split_double_concat (mode, operands[0], operands[3], operands[1]); DONE; -}) +} + [(set_attr "isa" "*,*,*,x64,x64")]) (define_insn_and_split "*concat3_4" [(set (match_operand: 0 "nonimmediate_operand" "=ro,r,r,&r") @@ -12495,7 +12476,8 @@ (define_insn_and_split "*concat3_4" { split_double_concat (mode, operands[0], operands[1], operands[2]); DONE; -}) +} + [(set_attr "isa" "*,*,*,x64")]) (define_insn_and_split "*concat3_5" [(set (match_operand:DWI 0 "nonimmediate_operand" "=r,o,o")