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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id a7-20020a1709065f8700b009a16d2fa98esi7620243eju.619.2023.08.23.04.04.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 04:04:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 994493853D1D for ; Wed, 23 Aug 2023 11:03:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id DBC713858C01 for ; Wed, 23 Aug 2023 11:03:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DBC713858C01 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1692788599t3s038g7 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 23 Aug 2023 19:03:17 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: rZJGTgY0+YPZEqgx6E3Pxy/zzQUJuatqg7JdOA7f2J4J1Mnlb7pPe/tdcpHUF FLfNPpwN+1X3v7ak4/hcVSGdk1m2EjfJzmds0Oa2yXJo1XPKsAqhBXLDgp7DDZ7qc0ZxlJx WrhqRT7gBaFFvdbYMGwEu/TL0ShSTZQywoRgYAnt4Tmu2dznB3Fhwqta723kOPzQJ+DwpnY JSd3iloxOCNkILHWyAx6evHCNNQ1f8Of0N5+RR/Gjm8FK6wU8nGKqn+e7uou+DnlKkU8vyH ZDThC693SyQThfgNubh8DqA16tczeiUow776TdQYkXD7EmpBXNOaa3Wd/aR6S/sjeBMeuZV qFz2EDYzGrUr/jq84cyIOj2wNEqC/UxUvSuCIvJNwxVjSxr2+9WlOhBTUEWJnZbgTqxM5du 4dUgxb76E0Q= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8539034374400435857 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Subject: [PATCH] RISC-V: Add conditional sign/zero extension and truncation autovec patterns Date: Wed, 23 Aug 2023 19:03:17 +0800 Message-Id: <20230823110317.4053846-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1775017546382502499 X-GMAIL-MSGID: 1775017546382502499 Hi, This patch adds conditional sign/zero extension and truncation autovec patterns by combining EXTENSION/TRUNCATION and VCOND_MASK patterns. For quad truncation, two vncvt instructions are generated. This patch combine the second vncvt and vmerge to form a masked vncvt, while the first vncvt remains unchanged. Of course, it is possible to convert the first vncvt to the mask type as well, but I don't think it is necessary. It is a similar story with 8x truncation. --- Best, Lehua gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_): Add combine pattern. (*cond_): Ditto. (*cond_): Ditto. (*cond_trunc): Ditto. * config/riscv/autovec.md (2): Change define_expand to define_insn_and_split. (2): Ditto. * config/riscv/riscv-protos.h (emit_vlmax_masked_insn): Exported. * config/riscv/riscv-v.cc (emit_vlmax_cmp_mu_insn): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: New test. --- gcc/config/riscv/autovec-opt.md | 69 +++++++++++++++++++ gcc/config/riscv/autovec.md | 39 ++++------- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 2 +- .../riscv/rvv/autovec/binop/narrow-3.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-1.h | 48 +++++++++++++ .../rvv/autovec/cond/cond_convert_int2int-2.h | 46 +++++++++++++ .../cond/cond_convert_int2int-rv32-1.c | 13 ++++ .../cond/cond_convert_int2int-rv32-2.c | 13 ++++ .../cond/cond_convert_int2int-rv64-1.c | 13 ++++ .../cond/cond_convert_int2int-rv64-2.c | 13 ++++ .../autovec/cond/cond_convert_int2int_run-1.c | 31 +++++++++ .../autovec/cond/cond_convert_int2int_run-2.c | 30 ++++++++ 13 files changed, 294 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 8247eb87ddb..f3ef3a839df 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -723,3 +723,72 @@ riscv_vector::RVV_BINOP, operands); DONE; }) + +;; Combine sign_extend/zero_extend(vf2) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VWEXTI 0 "register_operand") + (if_then_else:VWEXTI + (match_operand: 1 "register_operand") + (any_extend:VWEXTI (match_operand: 3 "register_operand")) + (match_operand:VWEXTI 2 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf2 (, mode); + riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M, operands); + DONE; +}) + +;; Combine sign_extend/zero_extend(vf4) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VQEXTI 0 "register_operand") + (if_then_else:VQEXTI + (match_operand: 1 "register_operand") + (any_extend:VQEXTI (match_operand: 3 "register_operand")) + (match_operand:VQEXTI 2 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf4 (, mode); + riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M, operands); + DONE; +}) + +;; Combine sign_extend/zero_extend(vf8) and vcond_mask +(define_insn_and_split "*cond_" + [(set (match_operand:VOEXTI 0 "register_operand") + (if_then_else:VOEXTI + (match_operand: 1 "register_operand") + (any_extend:VOEXTI (match_operand: 3 "register_operand")) + (match_operand:VOEXTI 2 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_vf8 (, mode); + riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M, operands); + DONE; +}) + +;; Combine trunc(vf2) + vcond_mask +(define_insn_and_split "*cond_trunc" + [(set (match_operand: 0 "register_operand") + (if_then_else: + (match_operand: 1 "register_operand") + (truncate: + (match_operand:VWEXTI 3 "register_operand")) + (match_operand: 2 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + insn_code icode = code_for_pred_trunc (mode); + riscv_vector::emit_vlmax_masked_insn (icode, riscv_vector::RVV_UNOP_M, operands); + DONE; +}) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index e1addc07036..4936333f303 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -644,22 +644,28 @@ [(set_attr "type" "vext") (set_attr "mode" "")]) -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VQEXTI 0 "register_operand") (any_extend:VQEXTI (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_vf4 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); DONE; }) -(define_expand "2" +(define_insn_and_split "2" [(set (match_operand:VOEXTI 0 "register_operand") (any_extend:VOEXTI (match_operand: 1 "register_operand")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] { insn_code icode = code_for_pred_vf8 (, mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); @@ -698,13 +704,8 @@ "TARGET_VECTOR" { rtx half = gen_reg_rtx (mode); - rtx opshalf[] = {half, operands[1]}; - insn_code icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, opshalf); - - rtx ops[] = {operands[0], half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops); + emit_insn (gen_trunc2 (half, operands[1])); + emit_insn (gen_trunc2 (operands[0], half)); DONE; }) @@ -718,19 +719,9 @@ (match_operand:VOEXTI 1 "register_operand")))] "TARGET_VECTOR" { - rtx half = gen_reg_rtx (mode); - rtx opshalf[] = {half, operands[1]}; - insn_code icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, opshalf); - - rtx quarter = gen_reg_rtx (mode); - rtx opsquarter[] = {quarter, half}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, opsquarter); - - rtx ops[] = {operands[0], quarter}; - icode = code_for_pred_trunc (mode); - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops); + rtx half = gen_reg_rtx (mode); + emit_insn (gen_trunc2 (half, operands[1])); + emit_insn (gen_trunc2 (operands[0], half)); DONE; }) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 2c4405c9860..558330718a1 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -254,6 +254,7 @@ void emit_nonvlmax_slide_tu_insn (unsigned, rtx *, rtx); void emit_vlmax_merge_insn (unsigned, int, rtx *); void emit_vlmax_cmp_insn (unsigned, rtx *); void emit_vlmax_cmp_mu_insn (unsigned, rtx *); +void emit_vlmax_masked_insn (unsigned, int, rtx *); void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); void emit_scalar_move_insn (unsigned, rtx *, rtx = 0); void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 14eda581d00..a2cf006804b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -905,7 +905,7 @@ emit_vlmax_cmp_mu_insn (unsigned icode, rtx *ops) } /* This function emits a masked instruction. */ -static void +void emit_vlmax_masked_insn (unsigned icode, int op_num, rtx *ops) { machine_mode dest_mode = GET_MODE (ops[0]); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c index 3b288466394..315d2de0a8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c @@ -27,5 +27,5 @@ TEST_ALL () -/* { dg-final { scan-assembler-times {\tvnsra\.wx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvnsra\.wx} 8 } } */ /* { dg-final { scan-assembler-times {\tvnsrl\.wx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h new file mode 100644 index 00000000000..3aa518210c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h @@ -0,0 +1,48 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, \ + NEW_TYPE *__restrict b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + NEW_TYPE bi = b[i]; \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : bi; \ + } \ + } + +/* wider-width Integer Type => Integer Type */ +#define TEST_ALL_X2X_WIDER(T) \ + T (uint8_t, uint16_t) \ + T (uint8_t, uint32_t) \ + T (uint8_t, uint64_t) \ + T (int8_t, int16_t) \ + T (int8_t, int32_t) \ + T (int8_t, int64_t) \ + T (uint16_t, uint32_t) \ + T (uint16_t, uint64_t) \ + T (int16_t, int32_t) \ + T (int16_t, int64_t) \ + T (uint32_t, uint64_t) \ + T (int32_t, int64_t) + +/* narrower-width Integer Type => Integer Type */ +#define TEST_ALL_X2X_NARROWER(T) \ + T (uint16_t, uint8_t) \ + T (int16_t, int8_t) \ + T (uint32_t, uint8_t) \ + T (int32_t, int8_t) \ + T (uint64_t, uint8_t) \ + T (int64_t, int8_t) \ + T (uint32_t, uint16_t) \ + T (int32_t, int16_t) \ + T (uint64_t, uint16_t) \ + T (int64_t, int16_t) \ + T (uint64_t, uint32_t) \ + T (int64_t, int32_t) + +TEST_ALL_X2X_WIDER (DEF_LOOP) +TEST_ALL_X2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h new file mode 100644 index 00000000000..2a5296cc3a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h @@ -0,0 +1,46 @@ +#include + +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ + void __attribute__ ((noipa)) \ + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ + OLD_TYPE *__restrict a, NEW_TYPE b, \ + OLD_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \ + } \ + } + +/* wider-width Integer Type => Integer Type */ +#define TEST_ALL_X2X_WIDER(T) \ + T (uint8_t, uint16_t) \ + T (uint8_t, uint32_t) \ + T (uint8_t, uint64_t) \ + T (int8_t, int16_t) \ + T (int8_t, int32_t) \ + T (int8_t, int64_t) \ + T (uint16_t, uint32_t) \ + T (uint16_t, uint64_t) \ + T (int16_t, int32_t) \ + T (int16_t, int64_t) \ + T (uint32_t, uint64_t) \ + T (int32_t, int64_t) + +/* narrower-width Integer Type => Integer Type */ +#define TEST_ALL_X2X_NARROWER(T) \ + T (uint16_t, uint8_t) \ + T (int16_t, int8_t) \ + T (uint32_t, uint8_t) \ + T (int32_t, int8_t) \ + T (uint64_t, uint8_t) \ + T (int64_t, int8_t) \ + T (uint32_t, uint16_t) \ + T (int32_t, int16_t) \ + T (uint64_t, uint16_t) \ + T (int64_t, int16_t) \ + T (uint64_t, uint32_t) \ + T (int64_t, int32_t) + +TEST_ALL_X2X_WIDER (DEF_LOOP) +TEST_ALL_X2X_NARROWER (DEF_LOOP) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c new file mode 100644 index 00000000000..549ad743e94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c new file mode 100644 index 00000000000..e1d8decc61d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c new file mode 100644 index 00000000000..a62c0ae37bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c new file mode 100644 index 00000000000..6af741b88d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */ +/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c new file mode 100644 index 00000000000..04f24168a38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-1.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b[N]; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2X_WIDER (TEST_LOOP) + TEST_ALL_X2X_NARROWER (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c new file mode 100644 index 00000000000..7a6897bf029 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ + +#include "cond_convert_int2int-2.h" + +#define N 99 + +#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \ + { \ + NEW_TYPE r[N], b = 189; \ + OLD_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL_X2X_WIDER (TEST_LOOP) + TEST_ALL_X2X_NARROWER (TEST_LOOP) + return 0; +}