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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Jonathan Corbet" Subject: [PATCH net-next v4] octeon_ep: support Octeon device CNF95N Date: Wed, 2 Nov 2022 23:05:57 -0700 Message-ID: <20221103060600.1858-1-vburru@marvell.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pwUKfBp_NGNOlz2YE4KrArP1yccwGy2H X-Proofpoint-GUID: pwUKfBp_NGNOlz2YE4KrArP1yccwGy2H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-02_15,2022-11-02_01,2022-06-22_01 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748454800949858470?= X-GMAIL-MSGID: =?utf-8?q?1748454800949858470?= Add support for Octeon device CNF95N. CNF95N is a Octeon Fusion family product with same PCI NIC characteristics as CN93 which is currently supported by the driver. update supported device list in Documentation. Signed-off-by: Veerasenareddy Burru --- V3 -> V4: - fix the lines exceeding 80 columns V2 -> V3: - fixed the prefix in subject: "net-next PATCH" to "PATCH net-next". V1 -> V2: - update supported device list in Documentation. .../ethernet/marvell/octeon_ep.rst | 1 + .../ethernet/marvell/octeon_ep/octep_main.c | 20 ++++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_main.h | 2 ++ 3 files changed, 20 insertions(+), 3 deletions(-) base-commit: d3a4706339da26633316357efe7ab9a92ff29b2a diff --git a/Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst b/Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst index bc562c49011b..cad96c8d1f97 100644 --- a/Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst +++ b/Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst @@ -23,6 +23,7 @@ Supported Devices ================= Currently, this driver support following devices: * Network controller: Cavium, Inc. Device b200 + * Network controller: Cavium, Inc. Device b400 Interface Control ================= diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.c b/drivers/net/ethernet/marvell/octeon_ep/octep_main.c index 9089adcb75f9..1cbfa800a8af 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.c @@ -23,6 +23,7 @@ struct workqueue_struct *octep_wq; /* Supported Devices */ static const struct pci_device_id octep_pci_id_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN93_PF)}, + {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF95N_PF)}, {0, }, }; MODULE_DEVICE_TABLE(pci, octep_pci_id_tbl); @@ -907,6 +908,18 @@ static void octep_ctrl_mbox_task(struct work_struct *work) } } +static const char *octep_devid_to_str(struct octep_device *oct) +{ + switch (oct->chip_id) { + case OCTEP_PCI_DEVICE_ID_CN93_PF: + return "CN93XX"; + case OCTEP_PCI_DEVICE_ID_CNF95N_PF: + return "CNF95N"; + default: + return "Unsupported"; + } +} + /** * octep_device_setup() - Setup Octeon Device. * @@ -939,9 +952,10 @@ int octep_device_setup(struct octep_device *oct) switch (oct->chip_id) { case OCTEP_PCI_DEVICE_ID_CN93_PF: - dev_info(&pdev->dev, - "Setting up OCTEON CN93XX PF PASS%d.%d\n", - OCTEP_MAJOR_REV(oct), OCTEP_MINOR_REV(oct)); + case OCTEP_PCI_DEVICE_ID_CNF95N_PF: + dev_info(&pdev->dev, "Setting up OCTEON %s PF PASS%d.%d\n", + octep_devid_to_str(oct), OCTEP_MAJOR_REV(oct), + OCTEP_MINOR_REV(oct)); octep_device_setup_cn93_pf(oct); break; default: diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h index 025626a61383..123ffc13754d 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h @@ -21,6 +21,8 @@ #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 +#define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF + #define OCTEP_MAX_QUEUES 63 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES