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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id r5-20020aa7cb85000000b0052348d74865sm1119527edt.61.2023.08.18.06.57.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Aug 2023 06:57:16 -0700 (PDT) Message-ID: <6c8b8a16-bbf9-b697-0f4c-26a838fb5665@gmail.com> Date: Fri, 18 Aug 2023 15:57:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: [PATCH] RISC-V: Enable pressure-aware scheduling by default. To: gcc-patches , palmer , Kito Cheng , jeffreyalaw , "juzhe.zhong@rivai.ai" , vineetg@rivosinc.com Cc: rdapp.gcc@gmail.com Content-Language: en-US X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774575525899966026 X-GMAIL-MSGID: 1774575525899966026 Hi, this patch enables pressure-aware scheduling for riscv. There have been various requests for it so I figured I'd just go ahead and send the patch. There is some slight regression in code quality for a number of vector tests where we spill more due to different instructions order. The ones I looked at were a mix of bad luck and/or brittle tests. Comparing the size of the generated assembly or the number of vsetvls for SPECint also didn't show any immediate benefit but that's obviously not a very fine-grained analysis. As cost and scheduling models mature I expect the situation to improve and for now I think it's generally favorable to enable pressure-aware scheduling so we can work with it rather than trying to find every possible problem in advance. Any other opinions on that? Regards Robin This patch enables register -fsched-pressure by default and sets the algorithm to "model". As with other backends, this helps reduce unnecessary spills. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add -fsched-pressure. * config/riscv/riscv.cc (riscv_option_override): Set sched pressure algorithm. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/narrow_constraint-1.c: Add -fno-sched-pressure. * gcc.target/riscv/rvv/base/narrow_constraint-17.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-18.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-19.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-20.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-21.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-22.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-23.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-24.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-25.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-26.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-27.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-28.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-29.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-30.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-31.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-4.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-5.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto. --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv.cc | 5 +++++ .../gcc.target/riscv/rvv/base/narrow_constraint-1.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-17.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-18.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-19.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-20.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-21.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-22.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-23.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-24.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-25.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-26.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-27.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-28.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-29.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-30.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-31.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-4.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-5.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-8.c | 2 +- .../gcc.target/riscv/rvv/base/narrow_constraint-9.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c | 2 +- 27 files changed, 32 insertions(+), 25 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4737dcd44a1..59848b21162 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -2017,9 +2017,11 @@ static const struct default_options riscv_option_optimization_table[] = { { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 }, #if TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1 { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 }, { OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1}, + /* Enable -fsched-pressure by default when optimizing. */ #endif { OPT_LEVELS_NONE, 0, NULL, 0 } }; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 49062bef9fc..96c5362d2fd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -65,6 +65,7 @@ along with GCC; see the file COPYING3. If not see #include "cfgloop.h" #include "cfgrtl.h" #include "sel-sched.h" +#include "sched-int.h" #include "fold-const.h" #include "gimple-iterator.h" #include "gimple-expr.h" @@ -7095,6 +7096,10 @@ riscv_option_override (void) sorry ( "Current RISC-V GCC cannot support VLEN greater than 4096bit for 'V' Extension"); + SET_OPTION_IF_UNSET (&global_options, &global_options_set, + param_sched_pressure_algorithm, + SCHED_PRESSURE_MODEL); + /* Convert -march to a chunks count. */ riscv_vector_chunks = riscv_convert_vector_bits (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c index 0cdf60cde06..02d155dc5bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c index 97df21dd743..35ef18817fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c index 56c95d9c884..1c17b763fab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c index d50e497d6c9..923bc27b36b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c index 4e77c51d058..6dd1b84678b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c index 4f7efd508b1..ecf6d267fdb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c index 92084be99b2..20186079593 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c index f9817caca1e..847d27cc760 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c index 62d1f6dddd5..603bfa20f82 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c index 250c3fdb89a..4f295ecaaaf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c index 72e2d210c05..1a652399f87 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c index 0842700475c..4d70a4c39fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c index 9c1eddfac7e..c625d96a94c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c index 6988c24bd92..109ebc84112 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c index fe181de4d56..b993e480765 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c index ae5b4ed6913..d0bf4a80c9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c index 28971a0aad8..273f15a21ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c index 26675bcc87c..d75dc778638 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c index 0dac85a3203..c96ab598883 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c index 448ca859dbb..53130d32606 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c index cf6470cea0d..fba44d999b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c index 4e2a717197b..5aabdef4aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c index 026b40944c5..6db0f0b1c51 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c index ca57ecad7cf..5e5e07b37c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c index a01b3918404..119e41e23b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */ #include "riscv_vector.h"