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[8.43.85.97]) by mx.google.com with ESMTPS id m5-20020a056402050500b005237b8b2adcsi12694301edv.201.2023.08.17.05.30.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Aug 2023 05:30:00 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 768F8385DC0F for ; Thu, 17 Aug 2023 12:29:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 1514E3858C50 for ; Thu, 17 Aug 2023 12:29:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1514E3858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1692275365top7oiio Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.8]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 17 Aug 2023 20:29:24 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: znfcQSa1hKZ7ghH3xezqRY4wsX4mgtaoWMPbecervR+qNej2Xf6iU4vE1q+nq 7FX9yS/6lgYKRTyBQVNcE8K/dzZw2unPe9QzXxwIHxYBvtm/mhsepEF1mtuE8ZBn9zpjYBU JT8XGvDmwbzjLaMV7ICJDny7YyUQUYduMXGUZ8zRAfjnTL5juDmFdJm6THMGX5X5Ct9zugq mOkpQlXNKnYKMg56ZYli4wmy4VIZp7Q4LBq6jzQDQZq7cupv7QoFzfnkdWsupvNKJ188rEI 1nyGlZufoJb5ZQLEeaxFDz/0WGbgCr12/HUzVpr5WrVu+0FbsIDAl25kERkefaOqea6ojyq MAKOI+lluu0eZ8wSXBLI2ZMri5br1NjDewyCCNYWEhk4L3punseknXoxeMqzLdNk4lVRq+f X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5039637598142673896 From: Lehua Ding To: gcc-patches@gcc.gnu.org, rdapp.gcc@gmail.com Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Subject: [PATCH V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl Date: Thu, 17 Aug 2023 20:29:23 +0800 Message-Id: <20230817122923.3114045-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774462229366229227 X-GMAIL-MSGID: 1774479371100593126 Hi, This little patch fix the fail testcase (gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c) after apply this patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627121.html). The specific reason is that the vsetvl pass has bug and this patch forbidden the fuse of this case. This patch needs to be committed before that patch to work. Best, Lehua gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion): Forbidden. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c: Address failure due to uninitialized vtype register. --- gcc/config/riscv/riscv-vsetvl.cc | 17 +++++++++++++++++ .../autovec/gather-scatter/strided_load_run-1.c | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 79cbac01047..2d8fa754ea0 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -3330,6 +3330,23 @@ pass_vsetvl::backward_demand_fusion (void) else if (block_info.reaching_out.dirty_p ()) { /* DIRTY -> DIRTY or VALID -> DIRTY. */ + + /* Forbidden this case fuse because it change the value of a5. + bb 1: vsetvl zero, no_zero_avl + ... + use a5 + ... + bb 2: vsetvl a5, zero + => + bb 1: vsetvl a5, zero + ... + use a5 + ... + bb 2: + */ + if (block_info.reaching_out.demand_p (DEMAND_NONZERO_AVL) + && vlmax_avl_p (prop.get_avl ())) + continue; vector_insn_info new_info; if (block_info.reaching_out.compatible_p (prop)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c index 7ffa93bf13f..7eeb22aade2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c @@ -7,6 +7,12 @@ int main (void) { + /* FIXME: The purpose of this assembly is to ensure that the vtype register is + initialized befor instructions such as vmv1r.v are executed. Otherwise you + will get illegal instruction errors when running with spike+pk. This is an + interim solution for reduce unnecessary failures and a unified solution + will come later. */ + asm volatile("vsetivli x0, 0, e8, m1, ta, ma"); #define RUN_LOOP(DATA_TYPE, BITS) \ DATA_TYPE dest_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)]; \ DATA_TYPE dest2_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)]; \