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[8.43.85.97]) by mx.google.com with ESMTPS id ov30-20020a170906fc1e00b0099ce38d877fsi12476773ejb.30.2023.08.16.19.19.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 19:19:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=GtlvvNyk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1E8B5385C426 for ; Thu, 17 Aug 2023 02:19:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1E8B5385C426 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692238751; bh=c0Tj9xwsQ+3qMu1Qn4birPNRxDZEl0EsG7DADo/BUVs=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=GtlvvNyk55mS3s3nHLWgb1LQJG0UjnVgosCNNKfoZEYD1T/NEa7iDnSwF6GrEJ0dK VLjQ/5/U8S07oQuFTljdIFCNyK/gf9au849vTFH8aNwyRaLoLTun8NTwzbftHP2Y6X sBJ4Ni/B8ua2GW4IiqWqSIEC6F5NZ7md5b/iMcNM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id D76313857016 for ; Thu, 17 Aug 2023 02:18:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D76313857016 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="362844653" X-IronPort-AV: E=Sophos;i="6.01,178,1684825200"; d="scan'208";a="362844653" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2023 19:18:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="1065068986" X-IronPort-AV: E=Sophos;i="6.01,178,1684825200"; d="scan'208";a="1065068986" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 16 Aug 2023 19:18:18 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 0759D1005695; Thu, 17 Aug 2023 10:18:18 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API Date: Thu, 17 Aug 2023 10:18:15 +0800 Message-Id: <20230817021815.3062069-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774440950475602320 X-GMAIL-MSGID: 1774440950475602320 From: Pan Li This patch would like to support the rounding mode API for the VFNCVT.F.{X|XU|F}.W as the below samples. * __riscv_vfncvt_f_x_w_f32m1_rm * __riscv_vfncvt_f_x_w_f32m1_rm_m * __riscv_vfncvt_f_xu_w_f32m1_rm * __riscv_vfncvt_f_xu_w_f32m1_rm_m * __riscv_vfncvt_f_f_w_f32m1_rm * __riscv_vfncvt_f_f_w_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfncvt_f): Add frm_op_type template arg. (vfncvt_f_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfncvt_f_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test. Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 10 ++- .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 3 + .../riscv/rvv/base/float-point-ncvt-f.c | 69 +++++++++++++++++++ 4 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index acadec2afca..ad04647f9ba 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1786,9 +1786,15 @@ public: } }; +template class vfncvt_f : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_f_w) @@ -2512,7 +2518,8 @@ static CONSTEXPR const vfncvt_x vfncvt_xu_obj; static CONSTEXPR const vfncvt_x vfncvt_xu_frm_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; -static CONSTEXPR const vfncvt_f vfncvt_f_obj; +static CONSTEXPR const vfncvt_f vfncvt_f_obj; +static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj; static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj; static CONSTEXPR const reducop vredsum_obj; static CONSTEXPR const reducop vredmaxu_obj; @@ -2769,6 +2776,7 @@ BASE (vfncvt_xu_frm) BASE (vfncvt_rtz_x) BASE (vfncvt_rtz_xu) BASE (vfncvt_f) +BASE (vfncvt_f_frm) BASE (vfncvt_rod_f) BASE (vredsum) BASE (vredmaxu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 9bd09a41960..c8c649c4bb0 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -226,6 +226,7 @@ extern const function_base *const vfncvt_xu_frm; extern const function_base *const vfncvt_rtz_x; extern const function_base *const vfncvt_rtz_xu; extern const function_base *const vfncvt_f; +extern const function_base *const vfncvt_f_frm; extern const function_base *const vfncvt_rod_f; extern const function_base *const vredsum; extern const function_base *const vredmaxu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 1e0e989fc2a..cfbc125dcd8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -474,6 +474,9 @@ DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops) DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops) DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, i_to_nf_x_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, u_to_nf_xu_w_ops) +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, f_to_nf_f_w_ops) /* 14. Vector Reduction Operations. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c new file mode 100644 index 00000000000..d6d4be5e98e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfncvt_f_x_w_f32m1_rm (vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_x_w_f32m1_rm_m (vbool32_t mask, vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_xu_w_f32m1_rm (vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_xu_w_f32m1_rm_m (vbool32_t mask, vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_f_w_f32m1_rm (vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfncvt_f_f_w_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_x_w_f32m1 (vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_x_w_f32m1_m (vbool32_t mask, vint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_xu_w_f32m1 (vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_xu_w_f32m1_m (vbool32_t mask, vuint64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfncvt_f_f_w_f32m1 (vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfncvt_f_f_w_f32m1_m (vbool32_t mask, vfloat64m2_t op1, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfncvt\.f\.[xuf]+\.w\s+v[0-9]+,\s*v[0-9]+} 12 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 6 } } */