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[8.43.85.97]) by mx.google.com with ESMTPS id m8-20020a50ef08000000b005231f38ea66si11014031eds.680.2023.08.16.05.55.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 05:55:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="d/UWOdc6"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B7E1B3857351 for ; Wed, 16 Aug 2023 12:55:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B7E1B3857351 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692190512; bh=BGmGv8RGo2Hffb2FNWAsUEG6oZEdE1RaIlnSABm4VKA=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=d/UWOdc6jbglTsxCRGXAmDqrZpeTfephvaAZ9qfVnOgfWCaxpyirevYQbdt+MKLfg mWdNvHjMRswJE1mcvJbbGHoFaGRyqUtxH5NOgiGIHJw0ZCry0FzJmDdgC7/HtuCQBm t82wAXLkcOXP4uTkKl3mfr9LohqFDb7kXBt20Po4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 4678D3858C52 for ; Wed, 16 Aug 2023 12:54:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4678D3858C52 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="352113692" X-IronPort-AV: E=Sophos;i="6.01,177,1684825200"; d="scan'208";a="352113692" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2023 05:54:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="1064814229" X-IronPort-AV: E=Sophos;i="6.01,177,1684825200"; d="scan'208";a="1064814229" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 16 Aug 2023 05:54:21 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5036C1005132; Wed, 16 Aug 2023 20:54:20 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFNCVT.X.F.W rounding mode intrinsic API Date: Wed, 16 Aug 2023 20:54:18 +0800 Message-Id: <20230816125418.534962-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774390360506724844 X-GMAIL-MSGID: 1774390360506724844 From: Pan Li This patch would like to support the rounding mode API for the VFNCVT.X.F.W as the below samples. * __riscv_vfncvt_x_f_w_i16mf2_rm * __riscv_vfncvt_x_f_w_i16mf2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfncvt_x): Add frm_op_type template arg. (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfncvt_x_frm): New intrinsic function def. * config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_frm_def): New shape function for frm. (SHAPE): New declaration. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-ncvt-x.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 9 ++++- .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/riscv-vector-builtins-shapes.cc | 39 +++++++++++++++++++ .../riscv/riscv-vector-builtins-shapes.h | 1 + .../riscv/rvv/base/float-point-ncvt-x.c | 29 ++++++++++++++ 6 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 050ecbe780c..2f40eeaeda5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1759,10 +1759,15 @@ public: }; /* Implements vfncvt.x. */ -template +template class vfncvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn ( @@ -2502,6 +2507,7 @@ static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj; static CONSTEXPR const vfwcvt_f vfwcvt_f_obj; static CONSTEXPR const vfncvt_x vfncvt_x_obj; +static CONSTEXPR const vfncvt_x vfncvt_x_frm_obj; static CONSTEXPR const vfncvt_x vfncvt_xu_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj; static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj; @@ -2756,6 +2762,7 @@ BASE (vfwcvt_rtz_x) BASE (vfwcvt_rtz_xu) BASE (vfwcvt_f) BASE (vfncvt_x) +BASE (vfncvt_x_frm) BASE (vfncvt_xu) BASE (vfncvt_rtz_x) BASE (vfncvt_rtz_xu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 6565740c597..edff0de2715 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -220,6 +220,7 @@ extern const function_base *const vfwcvt_rtz_x; extern const function_base *const vfwcvt_rtz_xu; extern const function_base *const vfwcvt_f; extern const function_base *const vfncvt_x; +extern const function_base *const vfncvt_x_frm; extern const function_base *const vfncvt_xu; extern const function_base *const vfncvt_rtz_x; extern const function_base *const vfncvt_rtz_xu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 22c039c8cbb..5e37bae318a 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -472,6 +472,8 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, u_to_nf_xu_w_ops) DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, f_to_nf_f_w_ops) DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops) +DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops) + /* 14. Vector Reduction Operations. */ // 14.1. Vector Single-Width Integer Reduction Instructions diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 1d14fa21e81..80329113af3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -333,6 +333,44 @@ struct widen_alu_frm_def : public build_frm_base } }; +/* narrow_alu_frm_def class. */ +struct narrow_alu_frm_def : public build_frm_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + char base_name[BASE_NAME_MAX_LEN] = {}; + + normalize_base_name (base_name, instance.base_name, sizeof (base_name)); + + b.append_base_name (base_name); + + if (!overloaded_p) + { + /* vop --> vop_. */ + b.append_name (operand_suffixes[instance.op_info->op]); + /* vop_ --> vop__. */ + vector_type_index ret_type_idx + = instance.op_info->ret.get_function_type_index (instance.type.index); + b.append_name (type_suffixes[ret_type_idx].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_rm" suffix + for vop_rm C++ overloaded API. */ + if (!overloaded_p) + b.append_name ("_rm"); + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + + b.append_name (predication_suffixes[instance.pred]); + + return b.finish_name (); + } +}; + /* widen_alu_def class. Handle vwadd/vwsub. Unlike vadd.vx/vadd.vv/vwmul.vv/vwmul.vx, vwadd.vv/vwadd.vx/vwadd.wv/vwadd.wx has 'OP' suffix in overloaded API. */ @@ -856,6 +894,7 @@ SHAPE(widen_alu_frm, widen_alu_frm) SHAPE(no_mask_policy, no_mask_policy) SHAPE(return_mask, return_mask) SHAPE(narrow_alu, narrow_alu) +SHAPE(narrow_alu_frm, narrow_alu_frm) SHAPE(move, move) SHAPE(mask_alu, mask_alu) SHAPE(reduc_alu, reduc_alu) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index 841b930b547..b53ab451902 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -35,6 +35,7 @@ extern const function_shape *const widen_alu_frm; extern const function_shape *const no_mask_policy; extern const function_shape *const return_mask; extern const function_shape *const narrow_alu; +extern const function_shape *const narrow_alu_frm; extern const function_shape *const move; extern const function_shape *const mask_alu; extern const function_shape *const reduc_alu; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c new file mode 100644 index 00000000000..1630b7e7ccf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vint16mf2_t +test_riscv_vfncvt_x_f_w_i16mf2_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_rm (op1, 0, vl); +} + +vint16mf2_t +test_vfncvt_x_f_w_i16mf2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_rm_m (mask, op1, 1, vl); +} + +vint16mf2_t +test_riscv_vfncvt_x_f_w_i16mf2 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2 (op1, vl); +} + +vint16mf2_t +test_vfncvt_x_f_w_i16mf2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfncvt_x_f_w_i16mf2_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfncvt\.x\.f\.w\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */