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[8.43.85.97]) by mx.google.com with ESMTPS id z13-20020a170906714d00b0098e42bef73asi9800999ejj.98.2023.08.15.23.51.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 23:51:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=J6txypvl; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1C41F385624F for ; Wed, 16 Aug 2023 06:51:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1C41F385624F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692168707; bh=O9tyneMUYDm7SbhqD0qH8qolHI/Bq4SXPGsb7KEUXpU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=J6txypvlKE9lrfNo6VZA8DG5o1Jd3M24JWFau6O/VZp5zxy6ihShE83fwbrjjJiSC QV7Mz9ZXezpy8HDxkbhd7RuaDkBlQmDgYod/mLOZMZH1d+haoftuuckNH45y3cvZXl zb8Tgk1HNw1d+YPaI57o0wUrsn0r/UnfNz2+N52o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 3DC6A3858002 for ; Wed, 16 Aug 2023 06:51:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3DC6A3858002 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="375227946" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="375227946" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2023 23:51:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="980625378" X-IronPort-AV: E=Sophos;i="6.01,176,1684825200"; d="scan'208";a="980625378" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga006.fm.intel.com with ESMTP; 15 Aug 2023 23:50:57 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id D6F701005124; Wed, 16 Aug 2023 14:50:56 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API Date: Wed, 16 Aug 2023 14:50:55 +0800 Message-Id: <20230816065055.653158-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815064807.1314281-1-pan2.li@intel.com> References: <20230815064807.1314281-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774276720917975761 X-GMAIL-MSGID: 1774367495372558246 From: Pan Li This patch would like to support the rounding mode API for the VFCVT.F.X.V and VFCVT.F.XU.V as the below samples. * __riscv_vfcvt_f_x_v_f32m1_rm * __riscv_vfcvt_f_x_v_f32m1_rm_m * __riscv_vfcvt_f_xu_v_f32m1_rm * __riscv_vfcvt_f_xu_v_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfcvt_f_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test. Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 8 +++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-cvt-f.c | 50 +++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 421f4096db8..c78fa8e5b62 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1694,9 +1694,15 @@ public: } }; +template class vfcvt_f : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_x_v) @@ -2482,6 +2488,7 @@ static CONSTEXPR const vfcvt_x vfcvt_xu_frm_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj; static CONSTEXPR const vfcvt_f vfcvt_f_obj; +static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_obj; static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj; @@ -2733,6 +2740,7 @@ BASE (vfcvt_xu_frm) BASE (vfcvt_rtz_x) BASE (vfcvt_rtz_xu) BASE (vfcvt_f) +BASE (vfcvt_f_frm) BASE (vfwcvt_x) BASE (vfwcvt_xu) BASE (vfwcvt_rtz_x) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 98b61655692..08452587180 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -211,6 +211,7 @@ extern const function_base *const vfcvt_xu_frm; extern const function_base *const vfcvt_rtz_x; extern const function_base *const vfcvt_rtz_xu; extern const function_base *const vfcvt_f; +extern const function_base *const vfcvt_f_frm; extern const function_base *const vfwcvt_x; extern const function_base *const vfwcvt_xu; extern const function_base *const vfwcvt_rtz_x; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 613bbe7a855..8dbcd946d11 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -447,6 +447,8 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops) DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops) DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops) +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, i_to_f_x_v_ops) +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, u_to_f_xu_v_ops) // 13.18. Widening Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c new file mode 100644 index 00000000000..424a38ede13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1_rm (vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1_rm_m (vbool32_t mask, vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_rm_m (mask, op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1_rm (vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1_rm_m (vbool32_t mask, vuint32m1_t op1, + size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_rm_m (mask, op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1 (vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfcvt_f_x_v_f32m1_m (vbool32_t mask, vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1 (vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfcvt_f_x_vu_f32m1_m (vbool32_t mask, vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfcvt\.f\.x[u]?\.v\s+v[0-9]+,\s*v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */