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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id a3-20020aa7cf03000000b005236b763941si9363647edy.524.2023.08.14.23.48.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Aug 2023 23:48:59 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="v/J89hVk"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B06F5385770F for ; Tue, 15 Aug 2023 06:48:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B06F5385770F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692082137; bh=2axXJFijFU9IBouGVVtt7Za0sQ0ruKOu/x9yFGFeQE0=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=v/J89hVkW1VPJ5vzb4kYLOMEqRNp4ZMSEWGIZWjJexVu69hxuzDNIXH2k8XG8Tz2Y QAFbr/nLMgeaUt4Q/DWWOLxJKWuQaVxyktjhxVAlg5Wya3PZt/T+kTNpHzJjpnA/w+ lfq9Q0/GKgUVeIxr9CE+LnItZN9la/kIUwbpbGQg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id B72673858422 for ; Tue, 15 Aug 2023 06:48:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B72673858422 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="357178916" X-IronPort-AV: E=Sophos;i="6.01,174,1684825200"; d="scan'208";a="357178916" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 23:48:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="877259965" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 14 Aug 2023 23:48:12 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 361C0100782A; Tue, 15 Aug 2023 14:48:08 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API Date: Tue, 15 Aug 2023 14:48:07 +0800 Message-Id: <20230815064807.1314281-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774276720917975761 X-GMAIL-MSGID: 1774276720917975761 From: Pan Li This patch would like to support the rounding mode API for the VFCVT.F.X.V and VFCVT.F.XU.V as the below samples. * __riscv_vfcvt_f_x_v_f32m1_rm * __riscv_vfcvt_f_x_v_f32m1_rm_m * __riscv_vfcvt_f_xu_v_f32m1_rm * __riscv_vfcvt_f_xu_v_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfcvt_f_frm): New class for frm. (vfcvt_f_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfcvt_f_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 22 ++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-cvt-f.c | 50 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 8eb89a05580..3c2bc13b586 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -675,6 +675,26 @@ public: } }; +/* Implements below instructions for frm + - vfcvt_f +*/ +class vfcvt_f_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_x_v) + return e.use_exact_insn (code_for_pred (FLOAT, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_xu_v) + return e.use_exact_insn ( + code_for_pred (UNSIGNED_FLOAT, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2486,6 +2506,7 @@ static CONSTEXPR const vfcvt_x_frm vfcvt_xu_frm_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj; static CONSTEXPR const vfcvt_f vfcvt_f_obj; +static CONSTEXPR const vfcvt_f_frm vfcvt_f_frm_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_obj; static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj; static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj; @@ -2737,6 +2758,7 @@ BASE (vfcvt_xu_frm) BASE (vfcvt_rtz_x) BASE (vfcvt_rtz_xu) BASE (vfcvt_f) +BASE (vfcvt_f_frm) BASE (vfwcvt_x) BASE (vfwcvt_xu) BASE (vfwcvt_rtz_x) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 98b61655692..08452587180 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -211,6 +211,7 @@ extern const function_base *const vfcvt_xu_frm; extern const function_base *const vfcvt_rtz_x; extern const function_base *const vfcvt_rtz_xu; extern const function_base *const vfcvt_f; +extern const function_base *const vfcvt_f_frm; extern const function_base *const vfwcvt_x; extern const function_base *const vfwcvt_xu; extern const function_base *const vfwcvt_rtz_x; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 613bbe7a855..8dbcd946d11 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -447,6 +447,8 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops) DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops) DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops) +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, i_to_f_x_v_ops) +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, u_to_f_xu_v_ops) // 13.18. Widening Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c new file mode 100644 index 00000000000..424a38ede13 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1_rm (vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1_rm_m (vbool32_t mask, vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_rm_m (mask, op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1_rm (vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1_rm_m (vbool32_t mask, vuint32m1_t op1, + size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_rm_m (mask, op1, 0, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_x_v_f32m1 (vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfcvt_f_x_v_f32m1_m (vbool32_t mask, vint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_m (mask, op1, vl); +} + +vfloat32m1_t +test_riscv_vfcvt_f_xu_v_f32m1 (vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfcvt_f_x_vu_f32m1_m (vbool32_t mask, vuint32m1_t op1, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfcvt\.f\.x[u]?\.v\s+v[0-9]+,\s*v[0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */