From patchwork Tue Aug 15 00:47:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135642 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp317534vqo; Tue, 15 Aug 2023 02:55:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHQYJdlFtp4+Bbv/h9RAP9f5HmMQYOARI9gSxjTislxLP7CmngHH9wpqQ07ccJqyMx+XcSy X-Received: by 2002:a17:903:2450:b0:1b5:5059:e733 with SMTP id l16-20020a170903245000b001b55059e733mr11022539pls.17.1692093304099; Tue, 15 Aug 2023 02:55:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692093304; cv=none; d=google.com; s=arc-20160816; b=dSfZQjqc+wTr3S00eF1F3XOuwHruifwLHm5JxXnd6NWTul8SvNW+9x317CUSE2zEwX OwH3pCPrRIjNgsmTMMsqKQQloTnfMsLx/YyiM0NFIGCoNA8X6aa6hfICZhGONHKg8GQy t+Zl8WdiARXxUqmMF/278KHVXMyozAnpwS9eVjTA3LRNPTv1UmHWzFFLEOk95uwPQ0c0 vl8aMRld31wzM6kXdwHsew9S7rGnfmXJ5ZrMSWFflw+aqh/80shEZNIo/UF6Dvextq7T V3A8keRI+HT4eHjrhspaHaB3WOAWPJAna3Yb+2feBWxNxAcnCeCPg1hZQrvc21E32jHI tdWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kWFy23FiS5IEyPcQQ+qx1pOmeByt0rL2tbVxQX6kpKo=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=A+H11XVvOoCxJo2cDB0Rh33SI4FqyNpv4lAmTSrAGBYR4HtZxCB/QWRQFSpIq8lrSq Qf5V2ssCj+crkfDGXSX4da8j6ePRg0roTtg/0Of42RsEbUMv4Mpi4SVjXyIw8iXTVpyZ RvPpVpfG5qUDi1jc/BA2t5iloTUvOef6id+ftyWMbbG/piEMR2bzp+dbuQ1u7CTAD4OG 37P1Sni3eW/mvn9GgqUGJL1r1+yQ420TVHJIQ5g0k2CNlz187tU5Yc2tJbjv3C76r9aI JK8EGqqN8KPCfXgRjtfXSxX+OhFMxPH+bBlT/stpan8kF5oszSsnn5ZB1oLtQ5MlxnmR /Pjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ArMfxvd8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Mon, 14 Aug 2023 17:48:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5F8E364006 for ; Tue, 15 Aug 2023 00:48:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C703C433C9; Tue, 15 Aug 2023 00:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060498; bh=pgFliqh5FCiPwev8SHNbWyt1mtItXDmKgFcmPAR7eAI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ArMfxvd8GgUdg9gKY7FVVUcLWCSiKmKUDUbi+UAGlo4ygnK0IxpvcOECu7gxym9b+ 6XhETF2Rtb8o+c8/Q2S8XTUUNI15wG2klfjCtsR1Mmkm1Xi+DQ2gNYcN2N/T31Xtm1 AgsBEAX8lxJjcmzsVneffl3TGWlOQNimVicJzFsZGRBr/DF9TI8fVZiMjUGwjVwa9C nxeQ4P+tA0myGZBOwFI4D0Huaykq4WTzQ+sx7hA1RiUtasRRDseNyqZJsmIWvBbyc+ LPQ0fazBO9uHvG6/n+RxG+QZwGI8wcx520FlACcltd/KNaplqsj0yMkyMCKzbKksVk KhCJY1XMVb6KA== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 01/20] ARC: uaccess: remove arc specific out-of-line handles for -Os Date: Mon, 14 Aug 2023 17:47:54 -0700 Message-Id: <20230815004813.555115-2-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774288428138499816 X-GMAIL-MSGID: 1774288428138499816 Everything is now out-of-line in lib/usercopy.c Signed-off-by: Vineet Gupta --- arch/arc/include/asm/uaccess.h | 11 ++--------- arch/arc/mm/extable.c | 11 ----------- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h index 99712471c96a..d2da159bb80a 100644 --- a/arch/arc/include/asm/uaccess.h +++ b/arch/arc/include/asm/uaccess.h @@ -584,7 +584,7 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) return res; } -static inline unsigned long __arc_clear_user(void __user *to, unsigned long n) +static inline unsigned long __clear_user(void __user *to, unsigned long n) { long res = n; unsigned char *d_char = to; @@ -626,17 +626,10 @@ static inline unsigned long __arc_clear_user(void __user *to, unsigned long n) return res; } -#ifndef CONFIG_CC_OPTIMIZE_FOR_SIZE - #define INLINE_COPY_TO_USER #define INLINE_COPY_FROM_USER -#define __clear_user(d, n) __arc_clear_user(d, n) -#else -extern unsigned long arc_clear_user_noinline(void __user *to, - unsigned long n); -#define __clear_user(d, n) arc_clear_user_noinline(d, n) -#endif +#define __clear_user __clear_user #include diff --git a/arch/arc/mm/extable.c b/arch/arc/mm/extable.c index 4e14c4244ea2..88fa3a4d4906 100644 --- a/arch/arc/mm/extable.c +++ b/arch/arc/mm/extable.c @@ -22,14 +22,3 @@ int fixup_exception(struct pt_regs *regs) return 0; } - -#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE - -unsigned long arc_clear_user_noinline(void __user *to, - unsigned long n) -{ - return __arc_clear_user(to, n); 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Mon, 14 Aug 2023 17:48:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C946D640F6 for ; Tue, 15 Aug 2023 00:48:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6F3CC433CB; Tue, 15 Aug 2023 00:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060499; bh=YH1Bc28nzEk45ZXRwo0o5JTtxWlnUgrQ7Atrmj3ROek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sYn9I40SFgdPcfvO+C1hyvCYNpDILybAVYz26koAmqj/kKoLVs8PazZpg2vzGnFyG D+QnTkdkKTqjl9/c7LFQqsMCSe31rR9RqvluNm04G7sFNwExJ2BEX9D1xdgFxQj3q7 g9ZiBKNtZCtVvRQcUrlUSbYqCGuO0eWBy24njidcrnEZNKQPsKSol0n+efHEJaJ3xL VYDMzZZCeJo6RBOUl2KkCZDpA0Aq5h/r6XDbJpWyJ/ugdrSD8DphbH+xRlcT0+N76q 6yZq5j9IYGgWwnnvotQuESl5w9b97H8QiQ9Rk07XnY9l9Kc64Twm3/nI9PyNnfzSgr pD+WPdvs/ATOw== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 02/20] ARC: uaccess: use optimized generic __strnlen_user/__strncpy_from_user Date: Mon, 14 Aug 2023 17:47:55 -0700 Message-Id: <20230815004813.555115-3-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774658648194463848 X-GMAIL-MSGID: 1774658648194463848 The existing ARC variants have 2 issues - Use ZOL which may not be present in forthcoming architecture - Byte loop based vs. generic version which is word loop based Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 96cf8720bb93..47b4acc7d0c9 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -26,6 +26,8 @@ config ARC select GENERIC_PENDING_IRQ if SMP select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD + select GENERIC_STRNCPY_FROM_USER if MMU + select GENERIC_STRNLEN_USER if MMU select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 From patchwork Tue Aug 15 00:47:56 2023 Content-Type: text/plain; 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Mon, 14 Aug 2023 17:48:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3587664872 for ; Tue, 15 Aug 2023 00:48:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E27CC433CC; Tue, 15 Aug 2023 00:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060499; bh=u1nWpIWuw7k0zAnF/NQi2BJwAjoLPN0MnaMyy2rE3OY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m+4vGTbgbE+G2m55otkANO02MVzGEQh6P3wkbDIeKAc61Ge4ipns3aCly/jAe4662 /x/bB18nxReFR6fch5pOQItf2Y0nH3kizE7YbHIYeyeZj4DTTd2ShXjwa3AkqS3wGy 2sHLa6fcriwlG6N2VFhCXyebVd+8TkYnpxkGM4l3Fjjm+jTAj1ivbji7qF6QU57Y+H hG0hNX6AqE5MNSqZILVB9hPj+39Q9WdBjKrIuY/mTMOWlE6XVYhZr/ZX4hEUN27wAk LxZJFrr86j3mZs5YqGYm1/7UrLxm7YQ0rec3LWTNNswfIYf0Yih20vPN/W3EY2wttt 2faWVWD8mbw8A== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 03/20] ARC: uaccess: elide unaliged handling if hardware supports Date: Mon, 14 Aug 2023 17:47:56 -0700 Message-Id: <20230815004813.555115-4-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774277351066450227 X-GMAIL-MSGID: 1774277351066450227 Signed-off-by: Vineet Gupta --- arch/arc/include/asm/uaccess.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h index d2da159bb80a..1e8809ea000a 100644 --- a/arch/arc/include/asm/uaccess.h +++ b/arch/arc/include/asm/uaccess.h @@ -146,8 +146,9 @@ raw_copy_from_user(void *to, const void __user *from, unsigned long n) if (n == 0) return 0; - /* unaligned */ - if (((unsigned long)to & 0x3) || ((unsigned long)from & 0x3)) { + /* fallback for unaligned access when hardware doesn't support */ + if (!IS_ENABLED(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS) && + (((unsigned long)to & 0x3) || ((unsigned long)from & 0x3))) { unsigned char tmp; @@ -373,8 +374,9 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) if (n == 0) return 0; - /* unaligned */ - if (((unsigned long)to & 0x3) || ((unsigned long)from & 0x3)) { + /* fallback for unaligned access when hardware doesn't support */ + if (!IS_ENABLED(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS) && + (((unsigned long)to & 0x3) || ((unsigned long)from & 0x3))) { unsigned char tmp; From patchwork Tue Aug 15 00:47:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135680 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp559697vqo; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w15-20020aa7da4f000000b005257e415dd6si390039eds.482.2023.08.15.09.52.40; Tue, 15 Aug 2023 09:53:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kO8RZEOg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233678AbjHOAsa (ORCPT + 99 others); Mon, 14 Aug 2023 20:48:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233514AbjHOAsV (ORCPT ); Mon, 14 Aug 2023 20:48:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C2B31710 for ; Mon, 14 Aug 2023 17:48:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 366E764A88 for ; Tue, 15 Aug 2023 00:48:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6D2AC433CA; Tue, 15 Aug 2023 00:48:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060500; bh=zkG7tKNl0pma2wQFLKTamwokqNgfsNplt2WvHHW0PGA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kO8RZEOgp4rtCJQvp9wDXzhuhF7W3vI/goCzoA04uvMkG+BW64KEvcpWXKMlnfY72 jkhHSjgPy9uYEOCcFrDtkCbCn2Z6aSS0ghRRTfSrPAGN4GF0ilZ5K+kUmmJR5+etfZ Ius1ROSzMsZwSVd3AZVpmi+7vQl3Ejjtb7z3B/vgP3/t+UVWcMd7E1y1sB1Cd/UlNZ UQaeO7GTK9aqkt32A5/Xei8MX0D5AK0LJkypV+gUXCwv74P+opA8zGqmt3fID7t/xf yWVUgdv2UjxM03uEtOaS3JcAfIj40GKCirBj6lIOv7AYRYJeXz2dAhC1LeKXQ/ZmH3 YI4mQFHuPInIQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 04/20] ARCv2: memset: don't prefetch for len == 0 which happens a alot Date: Mon, 14 Aug 2023 17:47:57 -0700 Message-Id: <20230815004813.555115-5-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774314727858158653 X-GMAIL-MSGID: 1774314727858158653 This avoids potential "bleeding" when size == 0 as cache line would be dirtied (and possibly fetched from other cores) and due to the same reaons more optimal too. Signed-off-by: Vineet Gupta --- arch/arc/lib/memset-archs.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arc/lib/memset-archs.S b/arch/arc/lib/memset-archs.S index d2e09fece5bc..d0a5cec4cdca 100644 --- a/arch/arc/lib/memset-archs.S +++ b/arch/arc/lib/memset-archs.S @@ -36,12 +36,13 @@ #endif ENTRY_CFI(memset) - PREFETCHW_INSTR r0, 0 ; Prefetch the first write location mov.f 0, r2 ;;; if size is zero jz.d [blink] mov r3, r0 ; don't clobber ret val + PREFETCHW_INSTR r0, 0 ; Prefetch the first write location + ;;; if length < 8 brls.d.nt r2, 8, .Lsmallchunk mov.f lp_count,r2 From patchwork Tue Aug 15 00:47:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135656 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp408373vqo; Tue, 15 Aug 2023 06:00:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGzFE0CuXQPqccsnoUWzbunUZCiHGR0LcWfZjmXA8t+R4w8uTwTvY+pt2lOkjdaQrUtutoQ X-Received: by 2002:a17:90a:6c42:b0:268:6339:318 with SMTP id x60-20020a17090a6c4200b0026863390318mr10584527pjj.30.1692104419259; Tue, 15 Aug 2023 06:00:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692104419; cv=none; d=google.com; s=arc-20160816; b=XDGm787P8+sWL20kVTvaXCcUnmZpaitOmY8LE5/vA6X8LFofJjzleYwqbXUrnehA+x 5LMbPhjxPWHRIwHPfwcLNnayzLDmphpa0Theq+B/qgTQRNX6Y1c9cLY9OEbcquuivye3 If0MqOc60dXVK5ThWaGnLLkDOWlcKBEt6EXXoop/p11hNZIX1btUEbvJeilPDgi4zg1F sYIOtBtd1t+eLZfsvmBoWMwOOnafGIxF2lnD4bomMzra+lRfI1URh1wQEUV52bjlmx55 /X38WX/SYRbW/wGpXechn2BPnVr5ynTe0XCXAGS2yfXuDbPQaPTnFh/ou0bHEguzLJdK lCRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mRJtK+9mTpJKX0vj5aHNB7yWug1Hucg6mvcLhr+ZOPo=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=EPVenSOnuEv/ZAstMBGV/SP7jBJghvIKTUYSpLNtmYIiw5fxvp7YrbPoNpJBbgjueb /rhKvQnR8NlS+M3Rd0elZxoD+D9jrutFaCoEPPVkL76KRmSBCkq4U6ANWCoxGOpVijba e2e3W9Pw/+gB8tw/h3RN8CShl4j97gCVT5Q6E0nHz1wx96XOWca8zgfgHAtVKs0kjHJa QKogotf3+dQRY7UPoDkm+O2lkSqapGBERufN7xKfcoGnE0oIdpbn8jfc14/oUW0fZRKx z7/A6FtX/jwAXynQc3rvrzp5jlFi555TiIbdizLVvIdCytOwjsZg36IkHSeZXhBdj0ev 4F9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=PKlrCQUi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q24-20020a17090aa01800b00268030516b6si9198870pjp.101.2023.08.15.06.00.00; Tue, 15 Aug 2023 06:00:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=PKlrCQUi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233765AbjHOAsi (ORCPT + 99 others); Mon, 14 Aug 2023 20:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233539AbjHOAsY (ORCPT ); Mon, 14 Aug 2023 20:48:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73AB71710 for ; Mon, 14 Aug 2023 17:48:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EAD463FE9 for ; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 342FFC433C7; Tue, 15 Aug 2023 00:48:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060500; bh=+ggOxNlO23GQYPQs86USV0qxaHwyNkCE70FT4o/Cdb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PKlrCQUi2gLF06LPw1KAAhsC7djngjGIZumeC4G0AwhKlZg203W0347Gn35YnCCQR qXwHdo28JesYiJr5sCG3gbqSJjGDMzzZcnDwlsPdRcg5Dkp55cTz8IQD0oM1OC7sEJ z8wJ6ejLtv3g+wXxA1enTbngLf2nHMPGmpb1tVQO3KvSps1t4da7ID0SkeC154IAyP a/DnOVco/FdawyA8DEjkMUcQ/WIbBi3L176Up7c7BsUiEyZqve5dOaLNzReyRfb6AE eBSwqvotPTwYxjKk9pB3gy4BvuCW3UrrDSUlEtV5ke2ZM2geBlcEENovrkGx9lxAmF mz2RbJTVXcb3w== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 05/20] ARC: boot log: eliminate struct cpuinfo_arc #1: mm Date: Mon, 14 Aug 2023 17:47:58 -0700 Message-Id: <20230815004813.555115-6-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774300083327313936 X-GMAIL-MSGID: 1774300083327313936 This is first step in eliminating struct cpuinfo_arc[NR_CPUS] Back when we had just ARCompact ISA, the idea was to read/bit-fiddle the BCRs once and and cache decoded information in a global struct ready to use. With ARCv2 it was modified to contained abstract / ISA agnostic information. However with ARCv3 there 's too much disparity to abstract in common structures. So drop the entire decode once and store paradigm. Afterall there's only 2 users of this machinery anyways: boot printing and cat /proc/cpuinfo. None is performance critical to warrant locking away resident memory per cpu. This patch is first step in that direction - decouples struct cpuinfo_arc_mmu from global struct cpuinfo_arc - mmu code still has a trimmed down static version of struct cpuinfo_arc_mmu to cache information needed in performance critical code such as tlb flush routines - folds read_decode_mmu_bcr() into arc_mmu_mumbojumbo() - setup_processor() directly calls arc_mmu_init() and not via arc_cpu_init() Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 27 +++++++--- arch/arc/include/asm/setup.h | 1 - arch/arc/kernel/setup.c | 4 +- arch/arc/mm/tlb.c | 92 +++++++++++++--------------------- 4 files changed, 57 insertions(+), 67 deletions(-) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 2162023195c5..af00cbe9b850 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -185,6 +185,27 @@ struct bcr_uarch_build_arcv2 { #endif }; +struct bcr_mmu_3 { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, + u_itlb:4, u_dtlb:4; +#else + unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4, + ways:4, ver:8; +#endif +}; + +struct bcr_mmu_4 { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif +}; + struct bcr_mpy { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; @@ -307,11 +328,6 @@ struct bcr_generic { * Generic structures to hold build configuration used at runtime */ -struct cpuinfo_arc_mmu { - unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; - unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; -}; - struct cpuinfo_arc_cache { unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; }; @@ -326,7 +342,6 @@ struct cpuinfo_arc_ccm { struct cpuinfo_arc { struct cpuinfo_arc_cache icache, dcache, slc; - struct cpuinfo_arc_mmu mmu; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; struct bcr_isa_arcv2 isa; diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 374138832c5a..76443f198778 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -36,7 +36,6 @@ long __init arc_get_mem_sz(void); extern void arc_mmu_init(void); extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); -extern void read_decode_mmu_bcr(void); extern void arc_cache_init(void); extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 41f07b3e594e..094461540f8a 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -186,7 +186,6 @@ static void read_arc_build_cfg_regs(void) /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ read_decode_ccm_bcr(cpu); - read_decode_mmu_bcr(); read_decode_cache_bcr(); if (is_isa_arcompact()) { @@ -256,7 +255,7 @@ static void read_arc_build_cfg_regs(void) cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); /* there's no direct way to distinguish 750 vs. 770 */ - if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) + if (unlikely(cpu->core.family < 0x34)) cpu->name = "ARC750"; } else { cpu->isa = isa; @@ -463,6 +462,7 @@ void setup_processor(void) arc_init_IRQ(); pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); + pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str))); arc_mmu_init(); arc_cache_init(); diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 2a3105a682c3..17e32c707367 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -18,7 +18,9 @@ /* A copy of the ASID from the PID reg is kept in asid_cache */ DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE; -static int __read_mostly pae_exists; +static struct cpuinfo_arc_mmu { + unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; +} mmuinfo; /* * Utility Routine to erase a J-TLB entry @@ -131,7 +133,7 @@ static void tlb_entry_insert(unsigned int pd0, phys_addr_t pd1) noinline void local_flush_tlb_all(void) { - struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; + struct cpuinfo_arc_mmu *mmu = &mmuinfo; unsigned long flags; unsigned int entry; int num_tlb = mmu->sets * mmu->ways; @@ -560,89 +562,63 @@ void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, * the cpuinfo structure for later use. * No Validation is done here, simply read/convert the BCRs */ -void read_decode_mmu_bcr(void) +char *arc_mmu_mumbojumbo(int c, char *buf, int len) { - struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; - unsigned int tmp; - struct bcr_mmu_3 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, - u_itlb:4, u_dtlb:4; -#else - unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4, - ways:4, ver:8; -#endif - } *mmu3; - - struct bcr_mmu_4 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, - n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; -#else - /* DTLB ITLB JES JE JA */ - unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, - pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; -#endif - } *mmu4; + struct cpuinfo_arc_mmu *mmu = &mmuinfo; + unsigned int bcr, u_dtlb, u_itlb, sasid; + struct bcr_mmu_3 *mmu3; + struct bcr_mmu_4 *mmu4; + char super_pg[64] = ""; + int n = 0; - tmp = read_aux_reg(ARC_REG_MMU_BCR); - mmu->ver = (tmp >> 24); + bcr = read_aux_reg(ARC_REG_MMU_BCR); + mmu->ver = (bcr >> 24); if (is_isa_arcompact() && mmu->ver == 3) { - mmu3 = (struct bcr_mmu_3 *)&tmp; + mmu3 = (struct bcr_mmu_3 *)&bcr; mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1); mmu->sets = 1 << mmu3->sets; mmu->ways = 1 << mmu3->ways; - mmu->u_dtlb = mmu3->u_dtlb; - mmu->u_itlb = mmu3->u_itlb; - mmu->sasid = mmu3->sasid; + u_dtlb = mmu3->u_dtlb; + u_itlb = mmu3->u_itlb; + sasid = mmu3->sasid; } else { - mmu4 = (struct bcr_mmu_4 *)&tmp; + mmu4 = (struct bcr_mmu_4 *)&bcr; mmu->pg_sz_k = 1 << (mmu4->sz0 - 1); mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11); mmu->sets = 64 << mmu4->n_entry; mmu->ways = mmu4->n_ways * 2; - mmu->u_dtlb = mmu4->u_dtlb * 4; - mmu->u_itlb = mmu4->u_itlb * 4; - mmu->sasid = mmu4->sasid; - pae_exists = mmu->pae = mmu4->pae; + u_dtlb = mmu4->u_dtlb * 4; + u_itlb = mmu4->u_itlb * 4; + sasid = mmu4->sasid; + mmu->pae = mmu4->pae; } -} -char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) -{ - int n = 0; - struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu; - char super_pg[64] = ""; - - if (p_mmu->s_pg_sz_m) - scnprintf(super_pg, 64, "%dM Super Page %s", - p_mmu->s_pg_sz_m, - IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE)); + if (mmu->s_pg_sz_m) + scnprintf(super_pg, 64, "/%dM%s", + mmu->s_pg_sz_m, + IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) ? " (THP enabled)":""); n += scnprintf(buf + n, len - n, - "MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n", - p_mmu->ver, p_mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS, - p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways, - p_mmu->u_dtlb, p_mmu->u_itlb, - IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); + "MMU [v%x]\t: %dk%s, swalk %d lvl, JTLB %dx%d, uDTLB %d, uITLB %d%s%s\n", + mmu->ver, mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS, + mmu->sets, mmu->ways, + u_dtlb, u_itlb, + IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); return buf; } int pae40_exist_but_not_enab(void) { - return pae_exists && !is_pae40_enabled(); + return mmuinfo.pae && !is_pae40_enabled(); } void arc_mmu_init(void) { - struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; - char str[256]; + struct cpuinfo_arc_mmu *mmu = &mmuinfo; int compat = 0; - pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str))); - /* * Can't be done in processor.h due to header include dependencies */ @@ -719,7 +695,7 @@ volatile int dup_pd_silent; /* Be silent abt it or complain (default) */ void do_tlb_overlap_fault(unsigned long cause, unsigned long address, struct pt_regs *regs) { - struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu; + struct cpuinfo_arc_mmu *mmu = &mmuinfo; unsigned long flags; int set, n_ways = mmu->ways; From patchwork Tue Aug 15 00:47:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135611 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp157024vqo; Mon, 14 Aug 2023 19:23:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGOwr40LrxqLFq7DZL9r8H5d+0su0cbSq09nrDD9OiKCi5gmjbSDSeyLDhSaIa4JJtcooPf X-Received: by 2002:a05:6402:14d7:b0:523:4d60:71c0 with SMTP id f23-20020a05640214d700b005234d6071c0mr9995844edx.33.1692066216131; Mon, 14 Aug 2023 19:23:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692066216; cv=none; d=google.com; s=arc-20160816; b=pSWt9So3YSRPZN8GIm/VZCbGI+aYblphLNXtZPTf4LJW+04EF1rICXrBYMmdLeFkYZ lbQ8yhbkb22e3Ce1/NoyUxy5bIO9lTJp58rbM4cxYSPvv7HKx1xHlglNsftFPOJCwi+F hdX0ovV6xExAVkgLcGvRGmCgLIJd44QOXcc9FuYQ+ijezaoA8+MaXtohf9HkCHIf9kGn 149JKZ8afQWq84G4d0LppKF/V+k5Wtjp+PdwvEAEGfzmn/FV/4klawUyKBCyjNv5uvlE QjdCnrOgRAEaJ51HECGT4w3k9KQhMYL9Lm1cxQTgnWM23J0hbcibK/HFJLwXh5CfkqaZ mgEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8g1083WTxF5maS0CFrNPSwf03xcM+9kP9Y2nkwL0VJ8=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=nrFSXhGF5I+uMiWnK0zCX/C3gOUx4+H/I4kuBGePs2+i4G32H3FUrLG1JcbpGSPTZD K68qDcb3Pk2lokl2yl6W8viJjPC32Qyib8DYE9X14gfS26veKhFD6B2k3BO4cymZ7ksC 5lReD/u9N6gqqBkXu16CFYp9Yk5hFWLay21obZkdvFtm/4cdypG6Dm/WEO4/oqdTyfXc s7rioRuhDRvT96SuPzvNgFscBl2QkkaezI6n8Sc1NfRT3IYud6nbWDwLs7ldTeo9/jDS H7HgjRNLY0KBktQUx3fRcaMED1johrf75Da0bjl0Iu54Kq8dxO6eyqxLtbC4pjuFmZPw polA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=RepP7PpG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m2-20020aa7c482000000b005221da34ca8si8541758edq.377.2023.08.14.19.23.11; Mon, 14 Aug 2023 19:23:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=RepP7PpG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233747AbjHOAsg (ORCPT + 99 others); Mon, 14 Aug 2023 20:48:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233526AbjHOAsX (ORCPT ); Mon, 14 Aug 2023 20:48:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8711726 for ; Mon, 14 Aug 2023 17:48:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 71C9464B89 for ; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CE69C433CA; Tue, 15 Aug 2023 00:48:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060500; bh=qJhz5HZk3a2z6HLY6Omtsh1bvWUP5b6b9jSQlFYUi88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RepP7PpGxF7xtsdAuxnk2hkCRD+ZQNMd32rkSghTliLyWIUdiA4zyK5+uM3G8tT70 2r8axp88W8OIKiiEO/X4HJQOIMiG7DLSyCWdpJf54miqkalBpkkC2zjBYnQeozgWN/ uSIeTbJ14uhmVpTcdRtghJklZ9ZYjBbaFkkBgC+aMvHEvvBmN3kVrVhrUMMhz7Ycaa zBa3elptRKvyTTPjsxcqlr+Kzbe05s/FrRLWj2jkNNivgCd1qv06uimFrCsmvSQNNy 4fp0PQDcqxQE46n3vvVkpFrWrAaa1RyLHFHHD98vDFHgrnehV6fsb9Lawarxg6MQIA GshihXUuKkyfQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 06/20] ARC: boot log: eliminate struct cpuinfo_arc #2: cache Date: Mon, 14 Aug 2023 17:47:59 -0700 Message-Id: <20230815004813.555115-7-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774260024544979895 X-GMAIL-MSGID: 1774260024544979895 Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 37 ++++++- arch/arc/include/asm/setup.h | 1 - arch/arc/kernel/setup.c | 3 +- arch/arc/mm/cache.c | 171 ++++++++++++--------------------- 4 files changed, 97 insertions(+), 115 deletions(-) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index af00cbe9b850..cb1ad1bb4ece 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -206,6 +206,38 @@ struct bcr_mmu_4 { #endif }; +struct bcr_cache { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif +}; + +struct bcr_slc_cfg { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, way:2, lsz:2, sz:4; +#else + unsigned int sz:4, lsz:2, way:2, pad:24; +#endif +}; + +struct bcr_clust_cfg { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; +#else + unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; +#endif +}; + +struct bcr_volatile { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int start:4, limit:4, pad:22, order:1, disable:1; +#else + unsigned int disable:1, order:1, pad:22, limit:4, start:4; +#endif +}; + struct bcr_mpy { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; @@ -328,10 +360,6 @@ struct bcr_generic { * Generic structures to hold build configuration used at runtime */ -struct cpuinfo_arc_cache { - unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; -}; - struct cpuinfo_arc_bpu { unsigned int ver, full, num_cache, num_pred, ret_stk; }; @@ -341,7 +369,6 @@ struct cpuinfo_arc_ccm { }; struct cpuinfo_arc { - struct cpuinfo_arc_cache icache, dcache, slc; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; struct bcr_isa_arcv2 isa; diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 76443f198778..4c0bacd0ff5c 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -39,7 +39,6 @@ extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); extern void arc_cache_init(void); extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); -extern void read_decode_cache_bcr(void); extern void __init handle_uboot_args(void); diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 094461540f8a..3ea834941c1f 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -186,8 +186,6 @@ static void read_arc_build_cfg_regs(void) /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ read_decode_ccm_bcr(cpu); - read_decode_cache_bcr(); - if (is_isa_arcompact()) { struct bcr_fp_arcompact sp, dp; struct bcr_bpu_arcompact bpu; @@ -463,6 +461,7 @@ void setup_processor(void) pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str))); + pr_info("%s", arc_cache_mumbojumbo(cpu_id, str, sizeof(str))); arc_mmu_init(); arc_cache_init(); diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index bdaa4aa40947..7197bb845a40 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -28,6 +28,10 @@ int slc_enable = 1, ioc_enable = 1; unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */ unsigned long perip_end = 0xFFFFFFFF; /* legacy value */ +static struct cpuinfo_arc_cache { + unsigned int sz_k, line_len, colors; +} ic_info, dc_info, slc_info; + void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr, unsigned long sz, const int op, const int full_page); @@ -35,78 +39,24 @@ void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz); void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz); void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz); -char *arc_cache_mumbojumbo(int c, char *buf, int len) +static char *read_decode_cache_bcr_arcv2(int c, char *buf, int len) { - int n = 0; - struct cpuinfo_arc_cache *p; - -#define PR_CACHE(p, cfg, str) \ - if (!(p)->line_len) \ - n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ - else \ - n += scnprintf(buf + n, len - n, \ - str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ - (p)->sz_k, (p)->assoc, (p)->line_len, \ - (p)->vipt ? "VIPT" : "PIPT", \ - (p)->alias ? " aliasing" : "", \ - IS_USED_CFG(cfg)); - - PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); - PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); - - p = &cpuinfo_arc700[c].slc; - if (p->line_len) - n += scnprintf(buf + n, len - n, - "SLC\t\t: %uK, %uB Line%s\n", - p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); - - n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n", - perip_base, - IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) ")); - - return buf; -} - -/* - * Read the Cache Build Confuration Registers, Decode them and save into - * the cpuinfo structure for later use. - * No Validation done here, simply read/convert the BCRs - */ -static void read_decode_cache_bcr_arcv2(int cpu) -{ - struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc; + struct cpuinfo_arc_cache *p_slc = &slc_info; + struct bcr_identity ident; struct bcr_generic sbcr; - - struct bcr_slc_cfg { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:24, way:2, lsz:2, sz:4; -#else - unsigned int sz:4, lsz:2, way:2, pad:24; -#endif - } slc_cfg; - - struct bcr_clust_cfg { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; -#else - unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; -#endif - } cbcr; - - struct bcr_volatile { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int start:4, limit:4, pad:22, order:1, disable:1; -#else - unsigned int disable:1, order:1, pad:22, limit:4, start:4; -#endif - } vol; - + struct bcr_clust_cfg cbcr; + struct bcr_volatile vol; + int n = 0; READ_BCR(ARC_REG_SLC_BCR, sbcr); if (sbcr.ver) { + struct bcr_slc_cfg slc_cfg; READ_BCR(ARC_REG_SLC_CFG, slc_cfg); p_slc->sz_k = 128 << slc_cfg.sz; l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; + n += scnprintf(buf + n, len - n, + "SLC\t\t: %uK, %uB Line%s\n", + p_slc->sz_k, p_slc->line_len, IS_USED_RUN(slc_enable)); } READ_BCR(ARC_REG_CLUSTER_BCR, cbcr); @@ -129,70 +79,83 @@ static void read_decode_cache_bcr_arcv2(int cpu) ioc_enable = 0; } + READ_BCR(AUX_IDENTITY, ident); + /* HS 2.0 didn't have AUX_VOL */ - if (cpuinfo_arc700[cpu].core.family > 0x51) { + if (ident.family > 0x51) { READ_BCR(AUX_VOL, vol); perip_base = vol.start << 28; /* HS 3.0 has limit and strict-ordering fields */ - if (cpuinfo_arc700[cpu].core.family > 0x52) + if (ident.family > 0x52) perip_end = (vol.limit << 28) - 1; } + + n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n", + perip_base, + IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) ")); + + return buf; } -void read_decode_cache_bcr(void) +char *arc_cache_mumbojumbo(int c, char *buf, int len) { - struct cpuinfo_arc_cache *p_ic, *p_dc; - unsigned int cpu = smp_processor_id(); - struct bcr_cache { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; -#else - unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; -#endif - } ibcr, dbcr; + struct cpuinfo_arc_cache *p_ic = &ic_info, *p_dc = &dc_info; + struct bcr_cache ibcr, dbcr; + int vipt, assoc; + int n = 0; - p_ic = &cpuinfo_arc700[cpu].icache; READ_BCR(ARC_REG_IC_BCR, ibcr); - if (!ibcr.ver) goto dc_chk; - if (ibcr.ver <= 3) { + if (is_isa_arcompact() && (ibcr.ver <= 3)) { BUG_ON(ibcr.config != 3); - p_ic->assoc = 2; /* Fixed to 2w set assoc */ - } else if (ibcr.ver >= 4) { - p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */ + assoc = 2; /* Fixed to 2w set assoc */ + } else if (is_isa_arcv2() && (ibcr.ver >= 4)) { + assoc = 1 << ibcr.config; /* 1,2,4,8 */ } p_ic->line_len = 8 << ibcr.line_len; p_ic->sz_k = 1 << (ibcr.sz - 1); - p_ic->vipt = 1; - p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; + p_ic->colors = p_ic->sz_k/assoc/TO_KB(PAGE_SIZE); + + n += scnprintf(buf + n, len - n, + "I-Cache\t\t: %uK, %dway/set, %uB Line, VIPT%s%s\n", + p_ic->sz_k, assoc, p_ic->line_len, + p_ic->colors > 1 ? " aliasing" : "", + IS_USED_CFG(CONFIG_ARC_HAS_ICACHE)); dc_chk: - p_dc = &cpuinfo_arc700[cpu].dcache; READ_BCR(ARC_REG_DC_BCR, dbcr); - if (!dbcr.ver) goto slc_chk; - if (dbcr.ver <= 3) { + if (is_isa_arcompact() && (dbcr.ver <= 3)) { BUG_ON(dbcr.config != 2); - p_dc->assoc = 4; /* Fixed to 4w set assoc */ - p_dc->vipt = 1; - p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; - } else if (dbcr.ver >= 4) { - p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */ - p_dc->vipt = 0; - p_dc->alias = 0; /* PIPT so can't VIPT alias */ + vipt = 1; + assoc = 4; /* Fixed to 4w set assoc */ + p_dc->colors = p_dc->sz_k/assoc/TO_KB(PAGE_SIZE); + } else if (is_isa_arcv2() && (dbcr.ver >= 4)) { + vipt = 0; + assoc = 1 << dbcr.config; /* 1,2,4,8 */ + p_dc->colors = 1; /* PIPT so can't VIPT alias */ } p_dc->line_len = 16 << dbcr.line_len; p_dc->sz_k = 1 << (dbcr.sz - 1); + n += scnprintf(buf + n, len - n, + "D-Cache\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", + p_dc->sz_k, assoc, p_dc->line_len, + vipt ? "VIPT" : "PIPT", + p_dc->colors > 1 ? " aliasing" : "", + IS_USED_CFG(CONFIG_ARC_HAS_DCACHE)); + slc_chk: if (is_isa_arcv2()) - read_decode_cache_bcr_arcv2(cpu); + read_decode_cache_bcr_arcv2(c, buf + n, len - n); + + return buf; } /* @@ -1133,10 +1096,8 @@ static noinline void __init arc_ioc_setup(void) */ static noinline void __init arc_cache_init_master(void) { - unsigned int __maybe_unused cpu = smp_processor_id(); - if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { - struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; + struct cpuinfo_arc_cache *ic = &ic_info; if (!ic->line_len) panic("cache support enabled but non-existent cache\n"); @@ -1149,14 +1110,14 @@ static noinline void __init arc_cache_init_master(void) * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 */ - if (is_isa_arcv2() && ic->alias) + if (is_isa_arcv2() && ic->colors > 1) _cache_line_loop_ic_fn = __cache_line_loop_v3; else _cache_line_loop_ic_fn = __cache_line_loop; } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { - struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; + struct cpuinfo_arc_cache *dc = &dc_info; if (!dc->line_len) panic("cache support enabled but non-existent cache\n"); @@ -1168,14 +1129,13 @@ static noinline void __init arc_cache_init_master(void) /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ if (is_isa_arcompact()) { int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); - int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE); - if (dc->alias) { + if (dc->colors > 1) { if (!handled) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); - if (CACHE_COLORS_NUM != num_colors) + if (CACHE_COLORS_NUM != dc->colors) panic("CACHE_COLORS_NUM not optimized for config\n"); - } else if (!dc->alias && handled) { + } else if (handled && dc->colors == 1) { panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); } } @@ -1218,9 +1178,6 @@ static noinline void __init arc_cache_init_master(void) void __ref arc_cache_init(void) { unsigned int __maybe_unused cpu = smp_processor_id(); - char str[256]; - - pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str))); if (!cpu) arc_cache_init_master(); From patchwork Tue Aug 15 00:48:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135717 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp838800vqo; Tue, 15 Aug 2023 20:08:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHuUM6L3C7954YpHK+nWCDLubSs78hLSuPKrv7TOHQkxosGCmtL4fKXfP1nPwCxG+ASNycu X-Received: by 2002:a17:907:62a6:b0:99b:d244:2ac3 with SMTP id nd38-20020a17090762a600b0099bd2442ac3mr3988820ejc.9.1692155311243; Tue, 15 Aug 2023 20:08:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692155311; cv=none; d=google.com; s=arc-20160816; b=t0IidtCzvgnM8pg0ct8np7SNWBAPbDtCk9Bk2dDNOVGeZp03nW2XuoOLmzq4n5I+Hu mvzCbR+0F7ChKuzRFmmcmXhfiESG3ncqjPD2BnJ2ppjE/q1LZqv0VnrJke0svCnpMFSJ 0skNlhm8sPBnl/rnVyQoB2mlUduDZ04UzEnz0YpVs3mEnoVhpQtLsln31jONdGjoQrxX Im01rPKy6+tAg6nLFRXl0hGPgUovd8922/r0I3CAszNtIH/nWoEkzscmvZGW7ONRf5Xg vizuXVBw7zcYAXh1Nhja/sVR1xPDO7gqxis+oP+660QZ8CBtgiUZg6j9itVOwQ1G3OSp D3Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ifd5AjQy/ze2+e4Q5Y06lNQ6/z1rdMUnU2CN+bb5THU=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=ML7p9W8tPx1SY9DU+fgRBp8m97a+z5ZWuK4DeLtqDVN86UNLUuPJkiMhfLYTvXuz9g 577RScAoX9EN1x6yalWaL0o1C1OL72wR8vk0IPQz2XxD0FECmmMO5YgkCXg3SqM7/jrq vazhsq28I9aPt9aF3hrzwWpvSttYVL8//jiTOJJsSef1Wj7qeKsbOYb5OKEwLwTfeprM PPu2TmR0DYU3tYP7wNiXS3K/rMCahfek4rU335z888xmkvIuwMv9FrM4YVkoxTDBT64a 4EpsqfjFfC/ejMxDpZhEYcmUV/N6ALOQ/nLoZJuUeXIV+UwhTLV9u82z+UWWraDCv5RD PmgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QyMUGocd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Mon, 14 Aug 2023 17:48:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6F4B564A88 for ; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09758C433CB; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060501; bh=yrWuUhf9P1ssyMUb7IbxFKryWboz4RPeuI0NifoMGno=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QyMUGocdqRQxXPgXekFfbwRBL0IWCSwI3QN3Boyyyo1kLtTDDptYC8VOqP0XGVVFR FdcESXIRYthB5KoHSAXxdzlHlsS7iHD6WYlHfuMv9u5T5npBs7AYxSLwGFmB7qKB0k JPN8ZVNjTRb0jXe+F/OsGHkU1MpbTMYEP7QY4D3hddo5d5jaIclct4EKo+H2oIOWTa aDkyjYMAje8hWAY5fNTVJvZH03L3VBRkVCt6gmkjL6gR3F2V5ls/OG8qRThAWZ/0CK jvmM8czZDJyX8wuO/4QdBaOFkxXssvZkz4h4jM1R82K7C8twmy/muW0ZxuZiq5xRxD 9pyacHtJt9wwg== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 07/20] ARC: boot log: eliminate struct cpuinfo_arc #3: don't export Date: Mon, 14 Aug 2023 17:48:00 -0700 Message-Id: <20230815004813.555115-8-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774353447924742042 X-GMAIL-MSGID: 1774353447924742042 Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 2 -- arch/arc/kernel/mcip.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index cb1ad1bb4ece..160ee3fab1bd 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -384,8 +384,6 @@ struct cpuinfo_arc { struct bcr_mpy extn_mpy; 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Mon, 14 Aug 2023 17:48:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3F6E36307C for ; Tue, 15 Aug 2023 00:48:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A2A7C433C9; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060501; bh=Jo2S/GSy0n9P6B+6mtn0Rjm7jip3VoyzvKoQ5atT/BM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KhwOyTG42lc/xkQa1IFAi4RNtfiZaIAnE5+HLBvVRFmVkPvkBXi4SE1k8OGRwFWmh tZdAIUDVdP0GgjEe2HPIJFQTe/Q6CAi0WqjcvL4wJ3998RbhejEtPBzV9O5MjJ+JIq HIsUAFir7gy0Dg/bcSuV9yfpbJf+WJWzBQZPEV3vVorlsaCwvm0pNu7aoS7HqZtq+1 UZhbOUYYyH+OHx6QzGA5ma0X60jZDqQIkS6wkTDZS0pKrGOrAB4qJ+GIuon9SPdqoU zlVUs0H8zosYrzKCNxafBORecRZKjQl3/iEczd5+yuU1DFMpiGOM5TQECaekvAnxZ0 Rg7oIGrzHVfyA== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 08/20] ARC: boot log: eliminate struct cpuinfo_arc #4: boot log per ISA Date: Mon, 14 Aug 2023 17:48:01 -0700 Message-Id: <20230815004813.555115-9-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774286310146589096 X-GMAIL-MSGID: 1774286310146589096 - boot log now clearly per ISA - global struct cpuinfo_arc[] elimiated - local struct struct arcinfo kept for passing info between functions Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 33 +- arch/arc/include/asm/setup.h | 4 +- arch/arc/kernel/setup.c | 560 +++++++++++++++------------------ arch/arc/mm/cache.c | 10 +- arch/arc/mm/tlb.c | 4 +- 5 files changed, 268 insertions(+), 343 deletions(-) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 160ee3fab1bd..4b13f60fe7ca 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -23,7 +23,7 @@ #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ #define ARC_REG_XY_MEM_BCR 0x79 #define ARC_REG_MAC_BCR 0x7a -#define ARC_REG_MUL_BCR 0x7b +#define ARC_REG_MPY_BCR 0x7b #define ARC_REG_SWAP_BCR 0x7c #define ARC_REG_NORM_BCR 0x7d #define ARC_REG_MIXMAX_BCR 0x7e @@ -177,7 +177,7 @@ struct bcr_isa_arcv2 { #endif }; -struct bcr_uarch_build_arcv2 { +struct bcr_uarch_build { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, prod:8, maj:8, min:8; #else @@ -355,35 +355,6 @@ struct bcr_generic { #endif }; -/* - ******************************************************************* - * Generic structures to hold build configuration used at runtime - */ - -struct cpuinfo_arc_bpu { - unsigned int ver, full, num_cache, num_pred, ret_stk; -}; - -struct cpuinfo_arc_ccm { - unsigned int base_addr, sz; -}; - -struct cpuinfo_arc { - struct cpuinfo_arc_bpu bpu; - struct bcr_identity core; - struct bcr_isa_arcv2 isa; - const char *release, *name; - unsigned int vec_base; - struct cpuinfo_arc_ccm iccm, dccm; - struct { - unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, - fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4, - ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1, - timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; - } extn; - struct bcr_mpy extn_mpy; -}; - static inline int is_isa_arcv2(void) { return IS_ENABLED(CONFIG_ISA_ARCV2); diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 4c0bacd0ff5c..1c6db599e1fc 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -35,10 +35,10 @@ long __init arc_get_mem_sz(void); #define IS_AVAIL3(v, v2, s) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_DISABLED_RUN(v2)) extern void arc_mmu_init(void); -extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); +extern int arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); extern void arc_cache_init(void); -extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); +extern int arc_cache_mumbojumbo(int cpu_id, char *buf, int len); extern void __init handle_uboot_args(void); diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 3ea834941c1f..8749fcc8cfe3 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) @@ -43,19 +44,22 @@ const struct machine_desc *machine_desc; struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ -struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; +struct cpuinfo_arc { + int arcver; + unsigned int t0:1, t1:1; + struct { + unsigned long base; + unsigned int sz; + } iccm, dccm; +}; + +#ifdef CONFIG_ISA_ARCV2 -static const struct id_to_str arc_legacy_rel[] = { +static const struct id_to_str arc_hs_rel[] = { /* ID.ARCVER, Release */ -#ifdef CONFIG_ISA_ARCOMPACT - { 0x34, "R4.10"}, - { 0x35, "R4.11"}, -#else { 0x51, "R2.0" }, { 0x52, "R2.1" }, { 0x53, "R3.0" }, -#endif - { 0x00, NULL } }; static const struct id_to_str arc_hs_ver54_rel[] = { @@ -66,320 +70,294 @@ static const struct id_to_str arc_hs_ver54_rel[] = { { 3, "R4.00a"}, { 0xFF, NULL } }; +#endif -static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) +static int +arcompact_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len) { - if (is_isa_arcompact()) { - struct bcr_iccm_arcompact iccm; - struct bcr_dccm_arcompact dccm; + int n = 0; +#ifdef CONFIG_ISA_ARCOMPACT + char *cpu_nm, *isa_nm = "ARCompact"; + struct bcr_fp_arcompact fpu_sp, fpu_dp; + int atomic = 0, be, present; + int bpu_full, bpu_cache, bpu_pred; + struct bcr_bpu_arcompact bpu; + struct bcr_iccm_arcompact iccm; + struct bcr_dccm_arcompact dccm; + struct bcr_generic isa; - READ_BCR(ARC_REG_ICCM_BUILD, iccm); - if (iccm.ver) { - cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ - cpu->iccm.base_addr = iccm.base << 16; - } + READ_BCR(ARC_REG_ISA_CFG_BCR, isa); - READ_BCR(ARC_REG_DCCM_BUILD, dccm); - if (dccm.ver) { - unsigned long base; - cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ + if (!isa.ver) /* ISA BCR absent, use Kconfig info */ + atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); + else { + /* ARC700_BUILD only has 2 bits of isa info */ + atomic = isa.info & 1; + } - base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); - cpu->dccm.base_addr = base & ~0xF; - } - } else { - struct bcr_iccm_arcv2 iccm; - struct bcr_dccm_arcv2 dccm; - unsigned long region; - - READ_BCR(ARC_REG_ICCM_BUILD, iccm); - if (iccm.ver) { - cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ - if (iccm.sz00 == 0xF && iccm.sz01 > 0) - cpu->iccm.sz <<= iccm.sz01; - - region = read_aux_reg(ARC_REG_AUX_ICCM); - cpu->iccm.base_addr = region & 0xF0000000; - } + be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - READ_BCR(ARC_REG_DCCM_BUILD, dccm); - if (dccm.ver) { - cpu->dccm.sz = 256 << dccm.sz0; - if (dccm.sz0 == 0xF && dccm.sz1 > 0) - cpu->dccm.sz <<= dccm.sz1; + if (info->arcver < 0x34) + cpu_nm = "ARC750"; + else + cpu_nm = "ARC770"; - region = read_aux_reg(ARC_REG_AUX_DCCM); - cpu->dccm.base_addr = region & 0xF0000000; - } - } -} + n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s\n", + c, cpu_nm, isa_nm, IS_AVAIL1(be, "[Big-Endian]")); -static void decode_arc_core(struct cpuinfo_arc *cpu) -{ - struct bcr_uarch_build_arcv2 uarch; - const struct id_to_str *tbl; - - if (cpu->core.family < 0x54) { /* includes arc700 */ + READ_BCR(ARC_REG_FP_BCR, fpu_sp); + READ_BCR(ARC_REG_DPFP_BCR, fpu_dp); - for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) { - if (cpu->core.family == tbl->id) { - cpu->release = tbl->str; - break; - } - } + if (fpu_sp.ver | fpu_dp.ver) + n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", + IS_AVAIL1(fpu_sp.ver, "SP "), + IS_AVAIL1(fpu_dp.ver, "DP ")); - if (is_isa_arcompact()) - cpu->name = "ARC700"; - else if (tbl->str) - cpu->name = "HS38"; - else - cpu->name = cpu->release = "Unknown"; + READ_BCR(ARC_REG_BPU_BCR, bpu); + bpu_full = bpu.fam ? 1 : 0; + bpu_cache = 256 << (bpu.ent - 1); + bpu_pred = 256 << (bpu.ent - 1); - return; + n += scnprintf(buf + n, len - n, + "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", + IS_AVAIL1(bpu_full, "full"), + IS_AVAIL1(!bpu_full, "partial"), + bpu_cache, bpu_pred); + + READ_BCR(ARC_REG_ICCM_BUILD, iccm); + if (iccm.ver) { + info->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ + info->iccm.base = iccm.base << 16; } - /* - * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until - * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent - * releases only update it. - */ - READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); - - if (uarch.prod == 4) { - cpu->name = "HS48"; - cpu->extn.dual = 1; + READ_BCR(ARC_REG_DCCM_BUILD, dccm); + if (dccm.ver) { + unsigned long base; + info->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ - } else { - cpu->name = "HS38"; + base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); + info->dccm.base = base & ~0xF; } - for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) { - if (uarch.maj == tbl->id) { - cpu->release = tbl->str; - break; - } - } + /* ARCompact ISA specific sanity checks */ + present = fpu_dp.ver; /* SP has no arch visible regs */ + CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present); +#endif + return n; + } -static void read_arc_build_cfg_regs(void) +static int arcv2_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len) { - struct bcr_timer timer; - struct bcr_generic bcr; - struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; + int n = 0; +#ifdef CONFIG_ISA_ARCV2 + const char *release, *cpu_nm, *isa_nm = "ARCv2"; + int dual_issue = 0, dual_enb = 0, mpy_opt, present; + int bpu_full, bpu_cache, bpu_pred, bpu_ret_stk; + char mpy_nm[16], lpb_nm[32]; struct bcr_isa_arcv2 isa; - struct bcr_actionpoint ap; - - FIX_PTR(cpu); - - READ_BCR(AUX_IDENTITY, cpu->core); - decode_arc_core(cpu); + struct bcr_mpy mpy; + struct bcr_fp_arcv2 fpu; + struct bcr_bpu_arcv2 bpu; + struct bcr_lpb lpb; + struct bcr_iccm_arcv2 iccm; + struct bcr_dccm_arcv2 dccm; + struct bcr_erp erp; - READ_BCR(ARC_REG_TIMERS_BCR, timer); - cpu->extn.timer0 = timer.t0; - cpu->extn.timer1 = timer.t1; - cpu->extn.rtc = timer.rtc; + /* + * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until + * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent + * releases only update it. + */ - cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); + cpu_nm = "HS38"; - READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); + if (info->arcver > 0x50 && info->arcver <= 0x53) { + release = arc_hs_rel[info->arcver - 0x51].str; + } else { + const struct id_to_str *tbl; + struct bcr_uarch_build uarch; - /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ - read_decode_ccm_bcr(cpu); + READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); - if (is_isa_arcompact()) { - struct bcr_fp_arcompact sp, dp; - struct bcr_bpu_arcompact bpu; - - READ_BCR(ARC_REG_FP_BCR, sp); - READ_BCR(ARC_REG_DPFP_BCR, dp); - cpu->extn.fpu_sp = sp.ver ? 1 : 0; - cpu->extn.fpu_dp = dp.ver ? 1 : 0; - - READ_BCR(ARC_REG_BPU_BCR, bpu); - cpu->bpu.ver = bpu.ver; - cpu->bpu.full = bpu.fam ? 1 : 0; - if (bpu.ent) { - cpu->bpu.num_cache = 256 << (bpu.ent - 1); - cpu->bpu.num_pred = 256 << (bpu.ent - 1); + for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) { + if (uarch.maj == tbl->id) { + release = tbl->str; + break; + } } - } else { - struct bcr_fp_arcv2 spdp; - struct bcr_bpu_arcv2 bpu; - - READ_BCR(ARC_REG_FP_V2_BCR, spdp); - cpu->extn.fpu_sp = spdp.sp ? 1 : 0; - cpu->extn.fpu_dp = spdp.dp ? 1 : 0; - - READ_BCR(ARC_REG_BPU_BCR, bpu); - cpu->bpu.ver = bpu.ver; - cpu->bpu.full = bpu.ft; - cpu->bpu.num_cache = 256 << bpu.bce; - cpu->bpu.num_pred = 2048 << bpu.pte; - cpu->bpu.ret_stk = 4 << bpu.rse; - - /* if dual issue hardware, is it enabled ? */ - if (cpu->extn.dual) { + if (uarch.prod == 4) { unsigned int exec_ctrl; + cpu_nm = "HS48"; + dual_issue = 1; + /* if dual issue hardware, is it enabled ? */ READ_BCR(AUX_EXEC_CTRL, exec_ctrl); - cpu->extn.dual_enb = !(exec_ctrl & 1); + dual_enb = !(exec_ctrl & 1); } } - READ_BCR(ARC_REG_AP_BCR, ap); - if (ap.ver) { - cpu->extn.ap_num = 2 << ap.num; - cpu->extn.ap_full = !ap.min; - } - - READ_BCR(ARC_REG_SMART_BCR, bcr); - cpu->extn.smart = bcr.ver ? 1 : 0; - - READ_BCR(ARC_REG_RTT_BCR, bcr); - cpu->extn.rtt = bcr.ver ? 1 : 0; - READ_BCR(ARC_REG_ISA_CFG_BCR, isa); - /* some hacks for lack of feature BCR info in old ARC700 cores */ - if (is_isa_arcompact()) { - if (!isa.ver) /* ISA BCR absent, use Kconfig info */ - cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); - else { - /* ARC700_BUILD only has 2 bits of isa info */ - struct bcr_generic bcr = *(struct bcr_generic *)&isa; - cpu->isa.atomic = bcr.info & 1; - } - - cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); + n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", + c, cpu_nm, release, isa_nm, + IS_AVAIL1(isa.be, "[Big-Endian]"), + IS_AVAIL3(dual_issue, dual_enb, " Dual-Issue ")); + + READ_BCR(ARC_REG_MPY_BCR, mpy); + mpy_opt = 2; /* stock MPY/MPYH */ + if (mpy.dsp) /* OPT 7-9 */ + mpy_opt = mpy.dsp + 6; + + scnprintf(mpy_nm, 16, "mpy[opt %d] ", mpy_opt); + + READ_BCR(ARC_REG_FP_V2_BCR, fpu); + + n += scnprintf(buf + n, len - n, "ISA Extn\t: %s%s%s%s%s%s%s%s%s%s%s\n", + IS_AVAIL2(isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), + IS_AVAIL2(isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), + IS_AVAIL2(isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS), + IS_AVAIL1(mpy.ver, mpy_nm), + IS_AVAIL1(isa.div_rem, "div_rem "), + IS_AVAIL1((fpu.sp | fpu.dp), " FPU:"), + IS_AVAIL1(fpu.sp, " sp"), + IS_AVAIL1(fpu.dp, " dp")); + + READ_BCR(ARC_REG_BPU_BCR, bpu); + bpu_full = bpu.ft; + bpu_cache = 256 << bpu.bce; + bpu_pred = 2048 << bpu.pte; + bpu_ret_stk = 4 << bpu.rse; + + READ_BCR(ARC_REG_LPB_BUILD, lpb); + if (lpb.ver) { + unsigned int ctl; + ctl = read_aux_reg(ARC_REG_LPB_CTRL); + + scnprintf(lpb_nm, sizeof(lpb_nm), " Loop Buffer:%d %s", + lpb.entries, IS_DISABLED_RUN(!ctl)); + } - /* there's no direct way to distinguish 750 vs. 770 */ - if (unlikely(cpu->core.family < 0x34)) - cpu->name = "ARC750"; - } else { - cpu->isa = isa; + n += scnprintf(buf + n, len - n, + "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d%s\n", + IS_AVAIL1(bpu_full, "full"), + IS_AVAIL1(!bpu_full, "partial"), + bpu_cache, bpu_pred, bpu_ret_stk, + lpb_nm); + + READ_BCR(ARC_REG_ICCM_BUILD, iccm); + if (iccm.ver) { + unsigned long base; + info->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ + if (iccm.sz00 == 0xF && iccm.sz01 > 0) + info->iccm.sz <<= iccm.sz01; + base = read_aux_reg(ARC_REG_AUX_ICCM); + info->iccm.base = base & 0xF0000000; } -} -static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) -{ - struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; - struct bcr_identity *core = &cpu->core; - char mpy_opt[16]; - int n = 0; + READ_BCR(ARC_REG_DCCM_BUILD, dccm); + if (dccm.ver) { + unsigned long base; + info->dccm.sz = 256 << dccm.sz0; + if (dccm.sz0 == 0xF && dccm.sz1 > 0) + info->dccm.sz <<= dccm.sz1; + base = read_aux_reg(ARC_REG_AUX_DCCM); + info->dccm.base = base & 0xF0000000; + } - FIX_PTR(cpu); + /* Error Protection: ECC/Parity */ + READ_BCR(ARC_REG_ERP_BUILD, erp); + if (erp.ver) { + struct ctl_erp ctl; + READ_BCR(ARC_REG_ERP_CTRL, ctl); + /* inverted bits: 0 means enabled */ + n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", + IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), + IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), + IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); + } - n += scnprintf(buf + n, len - n, - "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", - core->family, core->cpu_id, core->chip_id); + /* ARCv2 ISA specific sanity checks */ + present = fpu.sp | fpu.dp | mpy.dsp; /* DSP and/or FPU */ + CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present); - n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", - cpu_id, cpu->name, cpu->release, - is_isa_arcompact() ? "ARCompact" : "ARCv2", - IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), - IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); + dsp_config_check(); +#endif + return n; +} - n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", - IS_AVAIL1(cpu->extn.timer0, "Timer0 "), - IS_AVAIL1(cpu->extn.timer1, "Timer1 "), - IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), - IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); +static char *arc_cpu_mumbojumbo(int c, struct cpuinfo_arc *info, char *buf, int len) +{ + struct bcr_identity ident; + struct bcr_timer timer; + struct bcr_generic bcr; + struct mcip_bcr mp; + struct bcr_actionpoint ap; + unsigned long vec_base; + int ap_num, ap_full, smart, rtt, n; - if (cpu->extn_mpy.ver) { - if (is_isa_arcompact()) { - scnprintf(mpy_opt, 16, "mpy"); - } else { + memset(info, 0, sizeof(info)); - int opt = 2; /* stock MPY/MPYH */ + READ_BCR(AUX_IDENTITY, ident); + info->arcver = ident.family; - if (cpu->extn_mpy.dsp) /* OPT 7-9 */ - opt = cpu->extn_mpy.dsp + 6; + n = scnprintf(buf, len, + "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", + ident.family, ident.cpu_id, ident.chip_id); - scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt); - } + if (is_isa_arcompact()) { + n += arcompact_mumbojumbo(c, info, buf + n, len - n); + } else if (is_isa_arcv2()){ + n += arcv2_mumbojumbo(c, info, buf + n, len - n); } - n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", - IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), - IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), - IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS), - IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt), - IS_AVAIL1(cpu->isa.div_rem, "div_rem ")); + n += arc_mmu_mumbojumbo(c, buf + n, len - n); + n += arc_cache_mumbojumbo(c, buf + n, len - n); - if (cpu->bpu.ver) { - n += scnprintf(buf + n, len - n, - "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", - IS_AVAIL1(cpu->bpu.full, "full"), - IS_AVAIL1(!cpu->bpu.full, "partial"), - cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); - - if (is_isa_arcv2()) { - struct bcr_lpb lpb; - - READ_BCR(ARC_REG_LPB_BUILD, lpb); - if (lpb.ver) { - unsigned int ctl; - ctl = read_aux_reg(ARC_REG_LPB_CTRL); - - n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", - lpb.entries, - IS_DISABLED_RUN(!ctl)); - } - } - n += scnprintf(buf + n, len - n, "\n"); - } + READ_BCR(ARC_REG_TIMERS_BCR, timer); + info->t0 = timer.t0; + info->t1 = timer.t1; - return buf; -} + READ_BCR(ARC_REG_MCIP_BCR, mp); + vec_base = read_aux_reg(AUX_INTR_VEC_BASE); -static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) -{ - int n = 0; - struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; + n += scnprintf(buf + n, len - n, + "Timers\t\t: %s%s%s%s%s%s\nVector Table\t: %#lx\n", + IS_AVAIL1(timer.t0, "Timer0 "), + IS_AVAIL1(timer.t1, "Timer1 "), + IS_AVAIL2(timer.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), + IS_AVAIL2(mp.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), + vec_base); - FIX_PTR(cpu); + READ_BCR(ARC_REG_AP_BCR, ap); + if (ap.ver) { + ap_num = 2 << ap.num; + ap_full = !ap.min; + } - n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); + READ_BCR(ARC_REG_SMART_BCR, bcr); + smart = bcr.ver ? 1 : 0; - if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) - n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", - IS_AVAIL1(cpu->extn.fpu_sp, "SP "), - IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); + READ_BCR(ARC_REG_RTT_BCR, bcr); + rtt = bcr.ver ? 1 : 0; - if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) { + if (ap.ver | smart | rtt) { n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s", - IS_AVAIL1(cpu->extn.smart, "smaRT "), - IS_AVAIL1(cpu->extn.rtt, "RTT ")); - if (cpu->extn.ap_num) { + IS_AVAIL1(smart, "smaRT "), + IS_AVAIL1(rtt, "RTT ")); + if (ap.ver) { n += scnprintf(buf + n, len - n, "ActionPoint %d/%s", - cpu->extn.ap_num, - cpu->extn.ap_full ? "full":"min"); + ap_num, + ap_full ? "full":"min"); } n += scnprintf(buf + n, len - n, "\n"); } - if (cpu->dccm.sz || cpu->iccm.sz) - n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", - cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), - cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); - - if (is_isa_arcv2()) { - - /* Error Protection: ECC/Parity */ - struct bcr_erp erp; - READ_BCR(ARC_REG_ERP_BUILD, erp); - - if (erp.ver) { - struct ctl_erp ctl; - READ_BCR(ARC_REG_ERP_CTRL, ctl); - - /* inverted bits: 0 means enabled */ - n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", - IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), - IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), - IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); - } - } + if (info->dccm.sz || info->iccm.sz) + n += scnprintf(buf + n, len - n, + "Extn [CCM]\t: DCCM @ %lx, %d KB / ICCM: @ %lx, %d KB\n", + info->dccm.base, TO_KB(info->dccm.sz), + info->iccm.base, TO_KB(info->iccm.sz)); return buf; } @@ -398,15 +376,15 @@ void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena) panic("Disable %s, hardware NOT present\n", opt_name); } -static void arc_chk_core_config(void) +/* + * ISA agnostic sanity checks + */ +static void arc_chk_core_config(struct cpuinfo_arc *info) { - struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; - int present = 0; - - if (!cpu->extn.timer0) + if (!info->t0) panic("Timer0 is not present!\n"); - if (!cpu->extn.timer1) + if (!info->t1) panic("Timer1 is not present!\n"); #ifdef CONFIG_ARC_HAS_DCCM @@ -414,35 +392,17 @@ static void arc_chk_core_config(void) * DCCM can be arbit placed in hardware. * Make sure it's placement/sz matches what Linux is built with */ - if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) + if ((unsigned int)__arc_dccm_base != info->dccm.base) panic("Linux built with incorrect DCCM Base address\n"); - if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz) + if (CONFIG_ARC_DCCM_SZ * SZ_1K != info->dccm.sz) panic("Linux built with incorrect DCCM Size\n"); #endif #ifdef CONFIG_ARC_HAS_ICCM - if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz) + if (CONFIG_ARC_ICCM_SZ * SZ_1K != info->iccm.sz) panic("Linux built with incorrect ICCM Size\n"); #endif - - /* - * FP hardware/software config sanity - * -If hardware present, kernel needs to save/restore FPU state - * -If not, it will crash trying to save/restore the non-existant regs - */ - - if (is_isa_arcompact()) { - /* only DPDP checked since SP has no arch visible regs */ - present = cpu->extn.fpu_dp; - CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present); - } else { - /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ - present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; - CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present); - - dsp_config_check(); - } } /* @@ -453,23 +413,19 @@ static void arc_chk_core_config(void) void setup_processor(void) { + struct cpuinfo_arc info; + int c = smp_processor_id(); char str[512]; - int cpu_id = smp_processor_id(); - read_arc_build_cfg_regs(); - arc_init_IRQ(); + pr_info("%s", arc_cpu_mumbojumbo(c, &info, str, sizeof(str))); + pr_info("%s", arc_platform_smp_cpuinfo()); - pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); - pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str))); - pr_info("%s", arc_cache_mumbojumbo(cpu_id, str, sizeof(str))); + arc_chk_core_config(&info); + arc_init_IRQ(); arc_mmu_init(); arc_cache_init(); - pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); - pr_info("%s", arc_platform_smp_cpuinfo()); - - arc_chk_core_config(); } static inline bool uboot_arg_invalid(unsigned long addr) @@ -616,6 +572,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) char *str; int cpu_id = ptr_to_cpu(v); struct device *cpu_dev = get_cpu_device(cpu_id); + struct cpuinfo_arc info; struct clk *cpu_clk; unsigned long freq = 0; @@ -628,7 +585,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (!str) goto done; - seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); + seq_printf(m, arc_cpu_mumbojumbo(cpu_id, &info, str, PAGE_SIZE)); cpu_clk = clk_get(cpu_dev, NULL); if (IS_ERR(cpu_clk)) { @@ -645,9 +602,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) loops_per_jiffy / (500000 / HZ), (loops_per_jiffy / (5000 / HZ)) % 100); - seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); - seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); - seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_platform_smp_cpuinfo()); free_page((unsigned long)str); diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 7197bb845a40..4510f805b21d 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -39,7 +39,7 @@ void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz); void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz); void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz); -static char *read_decode_cache_bcr_arcv2(int c, char *buf, int len) +static int read_decode_cache_bcr_arcv2(int c, char *buf, int len) { struct cpuinfo_arc_cache *p_slc = &slc_info; struct bcr_identity ident; @@ -94,10 +94,10 @@ static char *read_decode_cache_bcr_arcv2(int c, char *buf, int len) perip_base, IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) ")); - return buf; + return n; } -char *arc_cache_mumbojumbo(int c, char *buf, int len) +int arc_cache_mumbojumbo(int c, char *buf, int len) { struct cpuinfo_arc_cache *p_ic = &ic_info, *p_dc = &dc_info; struct bcr_cache ibcr, dbcr; @@ -153,9 +153,9 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len) slc_chk: if (is_isa_arcv2()) - read_decode_cache_bcr_arcv2(c, buf + n, len - n); + n += read_decode_cache_bcr_arcv2(c, buf + n, len - n); - return buf; + return n; } /* diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 17e32c707367..19deb8ca9c28 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -562,7 +562,7 @@ void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, * the cpuinfo structure for later use. * No Validation is done here, simply read/convert the BCRs */ -char *arc_mmu_mumbojumbo(int c, char *buf, int len) +int arc_mmu_mumbojumbo(int c, char *buf, int len) { struct cpuinfo_arc_mmu *mmu = &mmuinfo; unsigned int bcr, u_dtlb, u_itlb, sasid; @@ -606,7 +606,7 @@ char *arc_mmu_mumbojumbo(int c, char *buf, int len) u_dtlb, u_itlb, IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); - return buf; + return n; } int pae40_exist_but_not_enab(void) From patchwork Tue Aug 15 00:48:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135716 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp838027vqo; Tue, 15 Aug 2023 20:06:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuFgjnoWUkpNr6ObJRcA+U7cnpIf4lTTff4nCR69/p8QoTVkktyRSJQWlxaCVlyHCJWGU0 X-Received: by 2002:a05:651c:d6:b0:2b6:cb55:72bc with SMTP id 22-20020a05651c00d600b002b6cb5572bcmr499530ljr.1.1692155191416; Tue, 15 Aug 2023 20:06:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692155191; cv=none; d=google.com; s=arc-20160816; b=MulJfn9t3BtdczUzsZqISfb142xyBHjXQRNGAm4ZlxtifwvgMSmASYz/NshWN7s+rC eU3z42ZcvlHWbvfW4OHHz190KfqOmUnm1S2z/RISZJyMhD7JeXPNoQBhE0gLJ5tUA+x4 8enybbRqtP0SXkhGRR8JFT0w+UgG1nhel16UPNKWVGfZA0uIN+hEbF+5oJp4XgOFnuFk vx1kdSOuhz2zeuQ3uEmLWyQxjlfDOVcwXbYjnoSKEMMpB7NOp9ZS9jIvej3JNHbbKTUM lmNWkmhhgWQ/r4ct5iuGcSkUV6fOQlTzCjHIcw+vhHfnRNdt9Kin4/gLp39Qy8KqsDJD qYWA== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g5-20020a1709064e4500b00993178445a0si10339206ejw.310.2023.08.15.20.06.07; Tue, 15 Aug 2023 20:06:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="rA/LTrLM"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233720AbjHOAtE (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233488AbjHOAsZ (ORCPT ); Mon, 14 Aug 2023 20:48:25 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BD751733 for ; Mon, 14 Aug 2023 17:48:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9FC0964009 for ; Tue, 15 Aug 2023 00:48:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D42DEC433CA; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060502; bh=hhT1mF3skdDpP43eowGATSIN1CO8SgUeKtk2qpYb3S8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rA/LTrLMHU1IwchZrk2sbrR7xCFsiemGnDZxbS5r4Tmlt3Y4vQ9hg8zxUgPWNMKxc OLXD//dDHDXpmNk2b/YOH26z6pCRXsA6uBy3yPCwkhBadeqH2MiF+fREPkvHGPK2fg OsnUVww0uX6mP0CAZTwkVaVAh6NCX+/WdXQHAhNMT/FhaQjkJkgsg4pPyAuGO3aZOQ cYiKMI9q4eAg+WABMF+bGc1Vod1sISDR9BDYFSldhZmmvOgPC3fhRjMIPAU6OQMYH8 IMJDwluvPTox/ii04UozRDqx3sYaWauLOBVmH2QGUCkUCno8izwtWlST77h8fol2gA gsofnUuE4IIXw== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 09/20] ARC: entry: use gp to cache task pointer (vs. r25) Date: Mon, 14 Aug 2023 17:48:02 -0700 Message-Id: <20230815004813.555115-10-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774353322356005970 X-GMAIL-MSGID: 1774353322356005970 The motivation is eventual ABI considerations for ARCv3 but even without it this change us worthwhile as diffstat reduces 100 net lines r25 is a callee saved register, normally not saved by entry code in pt_regs. However because of its usage in CONFIG_ARC_CURR_IN_REG it needs to be. This in turn requires a whole bunch of special casing when we need to access r25. Then there is distinction between user mode r25 vs. kernel mode r25 - hence distinct SAVE_CALLEE_SAVED_{USER,KERNEL} Instead use gp which is a scratch register and thus saved already in entry code. This cleans things up significantly and much nocer on eyes: - SAVE_CALLEE_SAVED_{USER,KERNEL} are now exactly same - no special user_r25 slot in pt_reggs Note that typical global asm registers are callee-saved (r25), but gp is not callee-saved thus needs additional -ffixed- toggle Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 6 +- arch/arc/Makefile | 6 +- arch/arc/include/asm/current.h | 2 +- arch/arc/include/asm/entry-arcv2.h | 17 ++--- arch/arc/include/asm/entry-compact.h | 35 +++------ arch/arc/include/asm/entry.h | 107 ++++++++------------------- arch/arc/include/asm/ptrace.h | 6 +- arch/arc/kernel/asm-offsets.c | 2 - arch/arc/kernel/ctx_sw.c | 13 +--- arch/arc/kernel/ctx_sw_asm.S | 2 +- arch/arc/kernel/entry.S | 3 +- arch/arc/kernel/process.c | 11 --- arch/arc/kernel/ptrace.c | 2 - 13 files changed, 58 insertions(+), 154 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 47b4acc7d0c9..c92bacc1ff4c 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -492,11 +492,11 @@ config ARC_KVADDR_SIZE kernel-user gutter) config ARC_CURR_IN_REG - bool "Dedicate Register r25 for current_task pointer" + bool "cache current task pointer in gp" default y help - This reserved Register R25 to point to Current Task in - kernel mode. This saves memory access for each such access + This reserves gp register to point to Current Task in + kernel mode eliding memory access for each access config ARC_EMUL_UNALIGNED diff --git a/arch/arc/Makefile b/arch/arc/Makefile index 329400a1c355..2390dd042e36 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -28,14 +28,14 @@ cflags-y += $(tune-mcpu-def-y) endif endif - ifdef CONFIG_ARC_CURR_IN_REG # For a global register definition, make sure it gets passed to every file # We had a customer reported bug where some code built in kernel was NOT using -# any kernel headers, and missing the r25 global register +# any kernel headers, and missing the global register # Can't do unconditionally because of recursive include issues # due to LINUXINCLUDE += -include $(srctree)/arch/arc/include/asm/current.h +cflags-y += -ffixed-gp endif cflags-y += -fsection-anchors @@ -67,7 +67,7 @@ cflags-$(CONFIG_ARC_DW2_UNWIND) += -fasynchronous-unwind-tables $(cfi) # small data is default for elf32 tool-chain. If not usable, disable it # This also allows repurposing GP as scratch reg to gcc reg allocator disable_small_data := y -cflags-$(disable_small_data) += -mno-sdata -fcall-used-gp +cflags-$(disable_small_data) += -mno-sdata cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mbig-endian ldflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB diff --git a/arch/arc/include/asm/current.h b/arch/arc/include/asm/current.h index 9b9bdd3e6538..06be89f6f2f0 100644 --- a/arch/arc/include/asm/current.h +++ b/arch/arc/include/asm/current.h @@ -13,7 +13,7 @@ #ifdef CONFIG_ARC_CURR_IN_REG -register struct task_struct *curr_arc asm("r25"); +register struct task_struct *curr_arc asm("gp"); #define current (curr_arc) #else diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 0ff4c0610561..858742feab71 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -18,7 +18,6 @@ * | orig_r0 | * | event/ECR | * | bta | - * | user_r25 | * | gp | * | fp | * | sp | @@ -56,7 +55,7 @@ ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI ; - ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair + ; (B) Manually saved some regs: r12,r30, sp,fp,gp, ACCL pair #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE ; carve pt_regs on stack (case #3), PC/STAT32 already on stack @@ -157,17 +156,17 @@ st r10, [sp, PT_sp] ; SP (pt_regs->sp) -#ifdef CONFIG_ARC_CURR_IN_REG - st r25, [sp, PT_user_r25] - GET_CURR_TASK_ON_CPU r25 -#endif - #ifdef CONFIG_ARC_HAS_ACCL_REGS ST2 r58, r59, PT_r58 #endif /* clobbers r10, r11 registers pair */ DSP_SAVE_REGFILE_IRQ + +#ifdef CONFIG_ARC_CURR_IN_REG + GET_CURR_TASK_ON_CPU gp +#endif + .endm /*------------------------------------------------------------------------*/ @@ -188,10 +187,6 @@ sr r10, [AUX_USER_SP] 1: -#ifdef CONFIG_ARC_CURR_IN_REG - ld r25, [sp, PT_user_r25] -#endif - /* clobbers r10, r11 registers pair */ DSP_RESTORE_REGFILE_IRQ diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 67ff06e15cea..e3383e1cb040 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -151,14 +151,6 @@ /* ARC700 doesn't provide auto-stack switching */ SWITCH_TO_KERNEL_STK -#ifdef CONFIG_ARC_CURR_IN_REG - /* Treat r25 as scratch reg (save on stack) and load with "current" */ - PUSH r25 - GET_CURR_TASK_ON_CPU r25 -#else - sub sp, sp, 4 -#endif - st.a r0, [sp, -8] /* orig_r0 needed for syscall (skip ECR slot) */ sub sp, sp, 4 /* skip pt_regs->sp, already saved above */ @@ -179,6 +171,11 @@ lr r10, [ecr] st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */ + +#ifdef CONFIG_ARC_CURR_IN_REG + /* gp already saved on stack: now load with "current" */ + GET_CURR_TASK_ON_CPU gp +#endif .endm /*-------------------------------------------------------------- @@ -208,11 +205,8 @@ POP gp RESTORE_R12_TO_R0 -#ifdef CONFIG_ARC_CURR_IN_REG - ld r25, [sp, 12] -#endif ld sp, [sp] /* restore original sp */ - /* orig_r0, ECR, user_r25 skipped automatically */ + /* orig_r0, ECR skipped automatically */ .endm /* Dummy ECR values for Interrupts */ @@ -229,13 +223,6 @@ SWITCH_TO_KERNEL_STK -#ifdef CONFIG_ARC_CURR_IN_REG - /* Treat r25 as scratch reg (save on stack) and load with "current" */ - PUSH r25 - GET_CURR_TASK_ON_CPU r25 -#else - sub sp, sp, 4 -#endif PUSH 0x003\LVL\()abcd /* Dummy ECR */ sub sp, sp, 8 /* skip orig_r0 (not needed) @@ -255,6 +242,10 @@ PUSHAX lp_start PUSHAX bta_l\LVL\() +#ifdef CONFIG_ARC_CURR_IN_REG + /* gp already saved on stack: now load with "current" */ + GET_CURR_TASK_ON_CPU gp +#endif .endm /*-------------------------------------------------------------- @@ -282,11 +273,7 @@ POP gp RESTORE_R12_TO_R0 -#ifdef CONFIG_ARC_CURR_IN_REG - ld r25, [sp, 12] -#endif - ld sp, [sp] /* restore original sp */ - /* orig_r0, ECR, user_r25 skipped automatically */ + ld sp, [sp] /* restore original sp; orig_r0, ECR skipped implicitly */ .endm /* Get thread_info of "current" tsk */ diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h index 2980bc9b7653..49c2e090cb5c 100644 --- a/arch/arc/include/asm/entry.h +++ b/arch/arc/include/asm/entry.h @@ -91,7 +91,7 @@ * Helpers to save/restore callee-saved regs: * used by several macros below *-------------------------------------------------------------*/ -.macro SAVE_R13_TO_R24 +.macro SAVE_R13_TO_R25 PUSH r13 PUSH r14 PUSH r15 @@ -104,9 +104,11 @@ PUSH r22 PUSH r23 PUSH r24 + PUSH r25 .endm -.macro RESTORE_R24_TO_R13 +.macro RESTORE_R25_TO_R13 + POP r25 POP r24 POP r23 POP r22 @@ -121,81 +123,31 @@ POP r13 .endm -/*-------------------------------------------------------------- - * Collect User Mode callee regs as struct callee_regs - needed by - * fork/do_signal/unaligned-access-emulation. - * (By default only scratch regs are saved on entry to kernel) - * - * Special handling for r25 if used for caching Task Pointer. - * It would have been saved in task->thread.user_r25 already, but to keep - * the interface same it is copied into regular r25 placeholder in - * struct callee_regs. - *-------------------------------------------------------------*/ +/* + * save user mode callee regs as struct callee_regs + * - needed by fork/do_signal/unaligned-access-emulation. + */ .macro SAVE_CALLEE_SAVED_USER + SAVE_R13_TO_R25 +.endm - mov r12, sp ; save SP as ref to pt_regs - SAVE_R13_TO_R24 - -#ifdef CONFIG_ARC_CURR_IN_REG - ; Retrieve orig r25 and save it with rest of callee_regs - ld r12, [r12, PT_user_r25] - PUSH r12 -#else - PUSH r25 -#endif - +/* + * restore user mode callee regs as struct callee_regs + * - could have been changed by ptrace tracer or unaligned-access fixup + */ +.macro RESTORE_CALLEE_SAVED_USER + RESTORE_R25_TO_R13 .endm -/*-------------------------------------------------------------- - * Save kernel Mode callee regs at the time of Contect Switch. - * - * Special handling for r25 if used for caching Task Pointer. - * Kernel simply skips saving it since it will be loaded with - * incoming task pointer anyways - *-------------------------------------------------------------*/ +/* + * save/restore kernel mode callee regs at the time of context switch + */ .macro SAVE_CALLEE_SAVED_KERNEL - - SAVE_R13_TO_R24 - -#ifdef CONFIG_ARC_CURR_IN_REG - sub sp, sp, 4 -#else - PUSH r25 -#endif + SAVE_R13_TO_R25 .endm -/*-------------------------------------------------------------- - * Opposite of SAVE_CALLEE_SAVED_KERNEL - *-------------------------------------------------------------*/ .macro RESTORE_CALLEE_SAVED_KERNEL - -#ifdef CONFIG_ARC_CURR_IN_REG - add sp, sp, 4 /* skip usual r25 placeholder */ -#else - POP r25 -#endif - RESTORE_R24_TO_R13 -.endm - -/*-------------------------------------------------------------- - * Opposite of SAVE_CALLEE_SAVED_USER - * - * ptrace tracer or unaligned-access fixup might have changed a user mode - * callee reg which is saved back to usual r25 storage location - *-------------------------------------------------------------*/ -.macro RESTORE_CALLEE_SAVED_USER - -#ifdef CONFIG_ARC_CURR_IN_REG - POP r12 -#else - POP r25 -#endif - RESTORE_R24_TO_R13 - - ; SP is back to start of pt_regs -#ifdef CONFIG_ARC_CURR_IN_REG - st r12, [sp, PT_user_r25] -#endif + RESTORE_R25_TO_R13 .endm /*-------------------------------------------------------------- @@ -231,10 +183,10 @@ #ifdef CONFIG_SMP -/*------------------------------------------------- +/* * Retrieve the current running task on this CPU - * 1. Determine curr CPU id. - * 2. Use it to index into _current_task[ ] + * - loads it from backing _current_task[] (and can't use the + * caching reg for current task */ .macro GET_CURR_TASK_ON_CPU reg GET_CPU_ID \reg @@ -256,7 +208,7 @@ add2 \tmp, @_current_task, \tmp st \tsk, [\tmp] #ifdef CONFIG_ARC_CURR_IN_REG - mov r25, \tsk + mov gp, \tsk #endif .endm @@ -271,21 +223,20 @@ .macro SET_CURR_TASK_ON_CPU tsk, tmp st \tsk, [@_current_task] #ifdef CONFIG_ARC_CURR_IN_REG - mov r25, \tsk + mov gp, \tsk #endif .endm #endif /* SMP / UNI */ -/* ------------------------------------------------------------------ +/* * Get the ptr to some field of Current Task at @off in task struct - * -Uses r25 for Current task ptr if that is enabled + * - Uses current task cached in reg if enabled */ - #ifdef CONFIG_ARC_CURR_IN_REG .macro GET_CURR_TASK_FIELD_PTR off, reg - add \reg, r25, \off + add \reg, gp, \off .endm #else diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index cf90fcd2a628..e9798f46cdc4 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -52,11 +52,9 @@ struct pt_regs { }; unsigned long event; }; - - unsigned long user_r25; }; -#define MAX_REG_OFFSET offsetof(struct pt_regs, user_r25) +#define MAX_REG_OFFSET offsetof(struct pt_regs, event) #else @@ -79,8 +77,6 @@ struct pt_regs { unsigned long bta; /* bta_l1, bta_l2, erbta */ - unsigned long user_r25; - unsigned long r26; /* gp */ unsigned long fp; unsigned long sp; /* user/kernel sp depending on where we came from */ diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index 0e884036ab74..37324fd9a72f 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -63,8 +63,6 @@ int main(void) DEFINE(PT_blink, offsetof(struct pt_regs, blink)); DEFINE(PT_lpe, offsetof(struct pt_regs, lp_end)); DEFINE(PT_lpc, offsetof(struct pt_regs, lp_count)); - DEFINE(PT_user_r25, offsetof(struct pt_regs, user_r25)); - DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c index bf16f777a0bc..40d89440b7e4 100644 --- a/arch/arc/kernel/ctx_sw.c +++ b/arch/arc/kernel/ctx_sw.c @@ -38,11 +38,7 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) "st.a r22, [sp, -4] \n\t" "st.a r23, [sp, -4] \n\t" "st.a r24, [sp, -4] \n\t" -#ifndef CONFIG_ARC_CURR_IN_REG "st.a r25, [sp, -4] \n\t" -#else - "sub sp, sp, 4 \n\t" /* usual r25 placeholder */ -#endif /* set ksp of outgoing task in tsk->thread.ksp */ #if KSP_WORD_OFF <= 255 @@ -58,7 +54,7 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) /* * setup _current_task with incoming tsk. - * optionally, set r25 to that as well + * optionally, set caching reg to that as well * For SMP extra work to get to &_current_task[cpu] * (open coded SET_CURR_TASK_ON_CPU) */ @@ -72,19 +68,14 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) "st %2, [r24] \n\t" #endif #ifdef CONFIG_ARC_CURR_IN_REG - "mov r25, %2 \n\t" + "mov gp, %2 \n\t" #endif /* get ksp of incoming task from tsk->thread.ksp */ "ld.as sp, [%2, %1] \n\t" /* start loading it's CALLEE reg file */ - -#ifndef CONFIG_ARC_CURR_IN_REG "ld.ab r25, [sp, 4] \n\t" -#else - "add sp, sp, 4 \n\t" -#endif "ld.ab r24, [sp, 4] \n\t" "ld.ab r23, [sp, 4] \n\t" "ld.ab r22, [sp, 4] \n\t" diff --git a/arch/arc/kernel/ctx_sw_asm.S b/arch/arc/kernel/ctx_sw_asm.S index 02c461484761..95cba6265e2b 100644 --- a/arch/arc/kernel/ctx_sw_asm.S +++ b/arch/arc/kernel/ctx_sw_asm.S @@ -49,7 +49,7 @@ __switch_to: SET_CURR_TASK_ON_CPU r1, r3 /* reload SP with kernel mode stack pointer in task->thread.ksp */ - ld.as sp, [r1, (TASK_THREAD + THREAD_KSP)/4] + ld.as sp, [r1, KSP_WORD_OFF] /* restore the registers */ RESTORE_CALLEE_SAVED_KERNEL diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index 54e91df678dd..cd26e0fa5044 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -210,7 +210,6 @@ trap_with_param: ; Save callee regs in case gdb wants to have a look ; SP will grow up by size of CALLEE Reg-File - ; NOTE: clobbers r12 SAVE_CALLEE_SAVED_USER ; save location of saved Callee Regs @ thread_struct->pc @@ -318,7 +317,7 @@ resume_user_mode_begin: ; tracer might call PEEKUSR(CALLEE reg) ; ; NOTE: SP will grow up by size of CALLEE Reg-File - SAVE_CALLEE_SAVED_USER ; clobbers r12 + SAVE_CALLEE_SAVED_USER ; save location of saved Callee Regs @ thread_struct->callee GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10 diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index 980b71da2f61..96f591508142 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -162,7 +162,6 @@ asmlinkage void ret_from_fork(void); * | SP | * | orig_r0 | * | event/ECR | - * | user_r25 | * ------------------ <===== END of PAGE */ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) @@ -243,16 +242,6 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) */ c_callee->r25 = task_thread_info(p)->thr_ptr; -#ifdef CONFIG_ARC_CURR_IN_REG - /* - * setup usermode thread pointer #2: - * however for this special use of r25 in kernel, __switch_to() sets - * r25 for kernel needs and only in the final return path is usermode - * r25 setup, from pt_regs->user_r25. So set that up as well - */ - c_regs->user_r25 = c_callee->r25; -#endif - return 0; } diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c index 2abdcd9b09e8..8226df3163fe 100644 --- a/arch/arc/kernel/ptrace.c +++ b/arch/arc/kernel/ptrace.c @@ -47,7 +47,6 @@ static const struct pt_regs_offset regoffset_table[] = { REG_OFFSET_NAME(sp), REG_OFFSET_NAME(orig_r0), REG_OFFSET_NAME(event), - REG_OFFSET_NAME(user_r25), REG_OFFSET_END, }; @@ -57,7 +56,6 @@ static const struct pt_regs_offset regoffset_table[] = { REG_OFFSET_NAME(orig_r0), REG_OFFSET_NAME(event), REG_OFFSET_NAME(bta), - REG_OFFSET_NAME(user_r25), REG_OFFSET_NAME(r26), REG_OFFSET_NAME(fp), REG_OFFSET_NAME(sp), From patchwork Tue Aug 15 00:48:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135863 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b82d:0:b0:3f2:4152:657d with SMTP id z13csp537180vqi; Thu, 17 Aug 2023 01:09:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGbYSQfPOU8SawCp7jHez+CnSAx+Z39FCUxk/RL6DbDIl5sMnTG6UCRSqsL2Cf0Zc6pLh6W X-Received: by 2002:a17:90b:3b49:b0:26b:4a9e:3c7e with SMTP id ot9-20020a17090b3b4900b0026b4a9e3c7emr3811670pjb.4.1692259759239; Thu, 17 Aug 2023 01:09:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692259759; cv=none; d=google.com; s=arc-20160816; b=PABE3IqUtuXHMbm+0Kk+0voNDqfIPRIApHjTJ6w4wCtD4Jgh4nivxS8Xa864h5/KVZ hbBLnwUjPlJDC9ICn0ditCO+57xgbXbjQL6YThnUtIFMnN4KOgsqSEz2wNzH3Vz0rMx5 l8uWCsiNG5Mo1v45s9M1xTLTwJQJjT3JSqAOpHko9X/FlrvCMuQI0Gd+TmSwKLvcCofY 0BamBDGljSo0psWeGqIDgmJSI2U5AKCS3w9KDszwziVmVf4nzT0r4wArGbizcTHbx32F KIJxoJfHsmFPxSAObAMi1qS8Rt45PEXVtSxEbts6ReluTFZ/aL+uoJmLOd3qj3fJF1CV /d4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ujOiclhME9Yo3gSB4LMVq+mbOs/pyrlOwOd9l3gf5a8=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=hsh72IPWIKqQK8l6+Ps9m7iqqwtsiZkBw551LXqh731Ta3fIjIWhKchpdwcDDc2YU+ mVwU/L+eLTKrj5KvOS92HO3xC6YyQ4UfyATkvxqLrVquYbe06oMhm6VZZosCC5Iq6Qge d5j3UtY6ZOExwmTCVJUVh/1IKwnl4LuWfGeLygirgXc8FuGL0pIBeHqSx1rAWRLyTQR9 Q4cVO5xQgeWwsfp1zH7EA/dh8PbKV5WBBk5hNuRS3ICmF1Wx7V+jOI1DIUtoglX5IeaV TX81D52ngYb0LK56F5xaJmapo7UXWfaNufIO4/L3npRxwTI9vEMSjPwx1143L7xhoRBa Zr/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=jIuvLqPb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gx5-20020a17090b124500b0026806ed3fd8si1079922pjb.71.2023.08.17.01.09.05; Thu, 17 Aug 2023 01:09:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=jIuvLqPb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233775AbjHOAsj (ORCPT + 99 others); Mon, 14 Aug 2023 20:48:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233530AbjHOAsX (ORCPT ); Mon, 14 Aug 2023 20:48:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F5B11723 for ; Mon, 14 Aug 2023 17:48:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A241F64BEE for ; Tue, 15 Aug 2023 00:48:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D212C433CC; Tue, 15 Aug 2023 00:48:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060502; bh=yWcyUxif3dikEYknmSArzeGyfZedu8yajJX9cu4DT8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jIuvLqPbU//pLE4JPxKRp9UCHkrq9i+/o1874YalJxOHW1DzCuOc5eTpgw+36PDDD 2aOy8LOzN/4I/Y66XzxsCN/UDZ1ZlY544oyu35GmmcdnL7yq0qCBggnlJcDCF580Rx b2xdpHvMrUc/wnQ1wJTJYlgeosSMYovaiGmHWOcPHkxLTCNCtCKV3v7sRF8bov3N6R 4KTt9Ifyn9CofxXD/PVV8Ebi4mYtym7AeLTudA5ZA+xApAxDL242HS3ZDBNETyHs/y qpHDFhaLXhhTveQNORVxZZ6zFk+UD+YbDI7/VrH5bxw/OVgzuk2z7VRZE21OhoWNSA vlDa9wN4DEArQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 10/20] ARC: kernel stack: INIT_THREAD need not setup @init_stack in @ksp Date: Mon, 14 Aug 2023 17:48:03 -0700 Message-Id: <20230815004813.555115-11-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774462969477843585 X-GMAIL-MSGID: 1774462969477843585 There are 2 pointers to kernel mode stack of a task - task_struct.stack: base address of stack page (max possible stack top) - thread_info.ksp : runtime stack top in __switch_to INIT_THREAD was setting up ksp to stack base which was not really needed - it would get overwritten with dynamic value on first call to __switch_to when init is switched out for the very first time. - generic code already does init_task.stack = init_stack and ARC code uses that to retrieve task's stack base. Signed-off-by: Vineet Gupta --- arch/arc/include/asm/processor.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index fb844fce1ab6..82ddc929d6e7 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -33,9 +33,7 @@ struct thread_struct { #endif }; -#define INIT_THREAD { \ - .ksp = sizeof(init_stack) + (unsigned long) init_stack, \ -} +#define INIT_THREAD { } /* Forward declaration, a strange C thing */ struct task_struct; From patchwork Tue Aug 15 00:48:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135627 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp257672vqo; Tue, 15 Aug 2023 00:11:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGy+SHDzQ9HwjUNmY8aM6d2fAB8lNTxyVf/9uuIYMXaMjM2YuReSsZbbR4nV+B3qCB9zvh1 X-Received: by 2002:a17:906:3013:b0:99b:ed18:7a10 with SMTP id 19-20020a170906301300b0099bed187a10mr8971179ejz.36.1692083503430; Tue, 15 Aug 2023 00:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692083503; cv=none; d=google.com; s=arc-20160816; b=A3VfZGER6pm230evHA92ClcphSUGTSF7CWDPDWMrBYpDxSHoYXB/M2QPiY+mG1vi51 BO3ZFNWFOgFZBPCL7h4ftvOrc0flDURKuuQOqEYrOlw8ngmwnBQSChmJrr7DEFp9eevf b29p2/ghqo507tRYPItyQYxfjo9KGfUJv5Ika0JA3WZmPXGWBSSJAZ6sKShppxga1zzU vhrydgBolj/x44fs6ah//HCdQhaGr5R0jvRhQVqwn1/dK3ZslS6ukQelnotd2XTTvngQ IoEmFNvnZluD5XKP2Wy+d0//JfUxdFsM5piZzKJgvyk9QHogJHxM8yzBzRwwM+uq+lXq 2Tdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fvUpZ67AKE33I7F07ljFtLr+zBPhE37JWvoZPbUq3fc=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=BuNVF0BdrFTlebAyo+os+yc2BJu0/y0sHh3d6EkuBxeVkP15Ko2GjH4JINqeGvoXDJ fJrZ3uqvtAxGeIN3K5mI2ri8j8BMWMu5M2KX6ZjWp4mTA6mgTziNi24PDV0xV3ccRXhu ktxZ2Ercaa0vEdNkj192PlfpeGqjTePrCoZvrhnTQiM5D5E82aDqfqYKu3rmj37aPoRW uIHvNB6okPqMSlNRk2ysC2XVzs8zFvxPPICvrYYHod3YC8ffuYUASmLx7xFUROsBwzXa 9u+Knrjisj55gjmZtr9Qgu5Eg5rK/zIfI2qonN0avAOGp7iNo5Zh2HwX4nbLG3x5WuAj j/2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=f0cdlB7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i21-20020a170906a29500b0099b4948325bsi8976139ejz.31.2023.08.15.00.11.09; Tue, 15 Aug 2023 00:11:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=f0cdlB7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233679AbjHOAtA (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233477AbjHOAsZ (ORCPT ); Mon, 14 Aug 2023 20:48:25 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A4951726 for ; Mon, 14 Aug 2023 17:48:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6D1F360B9D for ; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9BAD4C433C9; Tue, 15 Aug 2023 00:48:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060502; bh=Bg9dTJaDB6ft5D9/0UBWehGD1kWgD8ZN9J/FDF/TexY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f0cdlB7IicBynG/qM4sTxEVOSTdMqLrjvgygkSRWeDxiSQVm6aGL/vSZWhbf5gwj6 VpqkhER5twL2nqdsvmQQXXWvCV+9JCgP30NZhmDJFLZP8EQ1mGb2UWffn/cbCnMQen sVI8wBWduzinxevKV9DMEkdEckfD4loVlNHOO0XwPC6nF48xHpKu8kZ6+3AZvqIfKU BO8P9/lO06sfyv57ylwaKc9SuV9jmvrOYD5/NltdjdIHIMJNldLZq02+FEq45YYOxM y5bxdb0nbAAxbUX5qbIsgpiXkBmOUx582BK5Y0NFtROCl9XwndpV08Db/BNL9TDt8d 9krxZe8PUhp7A== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 11/20] ARC: __switch_to: asm with dwarf ops (vs. inline asm) Date: Mon, 14 Aug 2023 17:48:04 -0700 Message-Id: <20230815004813.555115-12-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774278151673932535 X-GMAIL-MSGID: 1774278151673932535 __switch_to() is final step of context switch, swapping kernel modes stack (and callee regs) of outgoing task with next task. It is also the starting point of stack unwinging of a sleeping task and captures SP, FP, BLINK and the corresponding dwarf info. Back when dinosaurs still roamed around, ARC gas didn't support CFI pseudo ops and gcc was responsible for generating dwarf info. Thus it had to be written in "C" with inline asm to do the hand crafting of stack. The function prologue (and crucial saving of blink etc) was still gcc generated but not visible in code. Likewise dwarf info was missing. Now with modern tools, we can make things more obvious by writing the code in asm and adding approproate dwarf cfi pseudo ops. This is mostly non functional change, except for slight chnages to asm - ARCompact doesn't support MOV_S fp, sp, so we use MOV Signed-off-by: Vineet Gupta --- arch/arc/include/asm/dwarf.h | 32 +++++++---- arch/arc/kernel/Makefile | 9 +-- arch/arc/kernel/ctx_sw.c | 103 ----------------------------------- arch/arc/kernel/ctx_sw_asm.S | 72 +++++++++++++----------- 4 files changed, 61 insertions(+), 155 deletions(-) delete mode 100644 arch/arc/kernel/ctx_sw.c diff --git a/arch/arc/include/asm/dwarf.h b/arch/arc/include/asm/dwarf.h index 5f4de05bd4ee..a0d5ebe1bc3f 100644 --- a/arch/arc/include/asm/dwarf.h +++ b/arch/arc/include/asm/dwarf.h @@ -10,23 +10,31 @@ #ifdef ARC_DW2_UNWIND_AS_CFI -#define CFI_STARTPROC .cfi_startproc -#define CFI_ENDPROC .cfi_endproc -#define CFI_DEF_CFA .cfi_def_cfa -#define CFI_REGISTER .cfi_register -#define CFI_REL_OFFSET .cfi_rel_offset -#define CFI_UNDEFINED .cfi_undefined +#define CFI_STARTPROC .cfi_startproc +#define CFI_ENDPROC .cfi_endproc +#define CFI_DEF_CFA .cfi_def_cfa +#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset +#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register +#define CFI_OFFSET .cfi_offset +#define CFI_REL_OFFSET .cfi_rel_offset +#define CFI_REGISTER .cfi_register +#define CFI_RESTORE .cfi_restore +#define CFI_UNDEFINED .cfi_undefined #else #define CFI_IGNORE # -#define CFI_STARTPROC CFI_IGNORE -#define CFI_ENDPROC CFI_IGNORE -#define CFI_DEF_CFA CFI_IGNORE -#define CFI_REGISTER CFI_IGNORE -#define CFI_REL_OFFSET CFI_IGNORE -#define CFI_UNDEFINED CFI_IGNORE +#define CFI_STARTPROC CFI_IGNORE +#define CFI_ENDPROC CFI_IGNORE +#define CFI_DEF_CFA CFI_IGNORE +#define CFI_DEF_CFA_OFFSET CFI_IGNORE +#define CFI_DEF_CFA_REGISTER CFI_IGNORE +#define CFI_OFFSET CFI_IGNORE +#define CFI_REL_OFFSET CFI_IGNORE +#define CFI_REGISTER CFI_IGNORE +#define CFI_RESTORE CFI_IGNORE +#define CFI_UNDEFINED CFI_IGNORE #endif /* !ARC_DW2_UNWIND_AS_CFI */ diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile index 0723d888ac44..95fbf9364c67 100644 --- a/arch/arc/kernel/Makefile +++ b/arch/arc/kernel/Makefile @@ -5,6 +5,8 @@ obj-y := head.o arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o +obj-y += ctx_sw_asm.o + obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o @@ -24,11 +26,4 @@ ifdef CONFIG_ISA_ARCOMPACT CFLAGS_fpu.o += -mdpfp endif -ifdef CONFIG_ARC_DW2_UNWIND -CFLAGS_ctx_sw.o += -fno-omit-frame-pointer -obj-y += ctx_sw.o -else -obj-y += ctx_sw_asm.o -endif - extra-y := vmlinux.lds diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c deleted file mode 100644 index 40d89440b7e4..000000000000 --- a/arch/arc/kernel/ctx_sw.c +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) - * - * Vineetg: Aug 2009 - * -"C" version of lowest level context switch asm macro called by schedular - * gcc doesn't generate the dward CFI info for hand written asm, hence can't - * backtrace out of it (e.g. tasks sleeping in kernel). - * So we cheat a bit by writing almost similar code in inline-asm. - * -This is a hacky way of doing things, but there is no other simple way. - * I don't want/intend to extend unwinding code to understand raw asm - */ - -#include -#include -#include - -#define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) - -struct task_struct *__sched -__switch_to(struct task_struct *prev_task, struct task_struct *next_task) -{ - unsigned int tmp; - unsigned int prev = (unsigned int)prev_task; - unsigned int next = (unsigned int)next_task; - - __asm__ __volatile__( - /* FP/BLINK save generated by gcc (standard function prologue */ - "st.a r13, [sp, -4] \n\t" - "st.a r14, [sp, -4] \n\t" - "st.a r15, [sp, -4] \n\t" - "st.a r16, [sp, -4] \n\t" - "st.a r17, [sp, -4] \n\t" - "st.a r18, [sp, -4] \n\t" - "st.a r19, [sp, -4] \n\t" - "st.a r20, [sp, -4] \n\t" - "st.a r21, [sp, -4] \n\t" - "st.a r22, [sp, -4] \n\t" - "st.a r23, [sp, -4] \n\t" - "st.a r24, [sp, -4] \n\t" - "st.a r25, [sp, -4] \n\t" - - /* set ksp of outgoing task in tsk->thread.ksp */ -#if KSP_WORD_OFF <= 255 - "st.as sp, [%3, %1] \n\t" -#else - /* - * Workaround for NR_CPUS=4k - * %1 is bigger than 255 (S9 offset for st.as) - */ - "add2 r24, %3, %1 \n\t" - "st sp, [r24] \n\t" -#endif - - /* - * setup _current_task with incoming tsk. - * optionally, set caching reg to that as well - * For SMP extra work to get to &_current_task[cpu] - * (open coded SET_CURR_TASK_ON_CPU) - */ -#ifndef CONFIG_SMP - "st %2, [@_current_task] \n\t" -#else - "lr r24, [identity] \n\t" - "lsr r24, r24, 8 \n\t" - "bmsk r24, r24, 7 \n\t" - "add2 r24, @_current_task, r24 \n\t" - "st %2, [r24] \n\t" -#endif -#ifdef CONFIG_ARC_CURR_IN_REG - "mov gp, %2 \n\t" -#endif - - /* get ksp of incoming task from tsk->thread.ksp */ - "ld.as sp, [%2, %1] \n\t" - - /* start loading it's CALLEE reg file */ - "ld.ab r25, [sp, 4] \n\t" - "ld.ab r24, [sp, 4] \n\t" - "ld.ab r23, [sp, 4] \n\t" - "ld.ab r22, [sp, 4] \n\t" - "ld.ab r21, [sp, 4] \n\t" - "ld.ab r20, [sp, 4] \n\t" - "ld.ab r19, [sp, 4] \n\t" - "ld.ab r18, [sp, 4] \n\t" - "ld.ab r17, [sp, 4] \n\t" - "ld.ab r16, [sp, 4] \n\t" - "ld.ab r15, [sp, 4] \n\t" - "ld.ab r14, [sp, 4] \n\t" - "ld.ab r13, [sp, 4] \n\t" - - /* last (ret value) = prev : although for ARC it mov r0, r0 */ - "mov %0, %3 \n\t" - - /* FP/BLINK restore generated by gcc (standard func epilogue */ - - : "=r"(tmp) - : "n"(KSP_WORD_OFF), "r"(next), "r"(prev) - : "blink" - ); - - return (struct task_struct *)tmp; -} diff --git a/arch/arc/kernel/ctx_sw_asm.S b/arch/arc/kernel/ctx_sw_asm.S index 95cba6265e2b..59d779004e64 100644 --- a/arch/arc/kernel/ctx_sw_asm.S +++ b/arch/arc/kernel/ctx_sw_asm.S @@ -13,48 +13,54 @@ #define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) -;################### Low Level Context Switch ########################## +; IN +; - r0: prev task (also current) +; - r1: next task +; OUT +; - r0: prev task (so r0 not touched) .section .sched.text,"ax",@progbits - .align 4 - .global __switch_to - .type __switch_to, @function -__switch_to: - CFI_STARTPROC - - /* Save regs on kernel mode stack of task */ - st.a blink, [sp, -4] - st.a fp, [sp, -4] +ENTRY_CFI(__switch_to) + + /* save kernel stack frame regs of @prev task */ + push blink + CFI_DEF_CFA_OFFSET 4 + CFI_OFFSET r31, -4 + + push fp + CFI_DEF_CFA_OFFSET 8 + CFI_OFFSET r27, -8 + + mov fp, sp + CFI_DEF_CFA_REGISTER r27 + + /* kernel mode callee regs of @prev */ SAVE_CALLEE_SAVED_KERNEL - /* Save the now KSP in task->thread.ksp */ + /* save final SP to @prev->thread.ksp */ #if KSP_WORD_OFF <= 255 st.as sp, [r0, KSP_WORD_OFF] #else /* Workaround for NR_CPUS=4k as ST.as can only take s9 offset */ - add2 r24, r0, KSP_WORD_OFF - st sp, [r24] + add2 r10, r0, KSP_WORD_OFF + st sp, [r10] #endif - /* - * Return last task in r0 (return reg) - * On ARC, Return reg = First Arg reg = r0. - * Since we already have last task in r0, - * don't need to do anything special to return it - */ - - /* - * switch to new task, contained in r1 - * Temp reg r3 is required to get the ptr to store val - */ - SET_CURR_TASK_ON_CPU r1, r3 - - /* reload SP with kernel mode stack pointer in task->thread.ksp */ - ld.as sp, [r1, KSP_WORD_OFF] - - /* restore the registers */ + /* update @next in _current_task[] and GP register caching it */ + SET_CURR_TASK_ON_CPU r1, r10 + + /* load SP from @next->thread.ksp */ + ld.as sp, [r1, KSP_WORD_OFF] + + /* restore callee regs, stack frame regs of @next */ RESTORE_CALLEE_SAVED_KERNEL - ld.ab fp, [sp, 4] - ld.ab blink, [sp, 4] - j [blink] + pop fp + CFI_RESTORE r27 + CFI_DEF_CFA r28, 4 + + pop blink + CFI_RESTORE r31 + CFI_DEF_CFA_OFFSET 0 + + j [blink] END_CFI(__switch_to) From patchwork Tue Aug 15 00:48:05 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t13-20020a170906178d00b0099399ac6fdesi8796371eje.79.2023.08.15.05.52.42; Tue, 15 Aug 2023 05:53:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JPICftR2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233727AbjHOAtG (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233443AbjHOAsZ (ORCPT ); Mon, 14 Aug 2023 20:48:25 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED2D21723 for ; Mon, 14 Aug 2023 17:48:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CF08F642F4 for ; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B27DC433C8; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060503; bh=p90a7Qg6Ptt+87HfozDxeBWnT7x0j/a/uXJ7Xzg5jo0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JPICftR2uoctpaTDC/uhVMjqyaTUTkdnhquXsWf5JuTEaW/04J0vvIbR5NQcoD6zM MxLbfQDuAbVZldH771jELVhSIB+7U7P79aImi0S/N67GgRR8E8NWBGW2eru9vS59Rf NwIwskkCEek0z1pXsHQ4g8Y2xRyHfnUIqCtSr9ZXESwHFP78jArvFWOUTthzzwrlzy 917qNzQxgVdUnPHY5R3XwutN7x+tg0/y69nqwTabPogZ6vwU9f3EkxUX8h+oBEjCJV 8HTKc8FwY+kSu4riLOG2lAcxFUrMPppyFuRBkNFLqH+rKJZpcondMNCodmVQjozvh0 KLj49eljVAxoQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 12/20] ARC: __switch_to: move ksp to thread_info from thread_struct Date: Mon, 14 Aug 2023 17:48:05 -0700 Message-Id: <20230815004813.555115-13-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774299631584242026 X-GMAIL-MSGID: 1774299631584242026 task's arch specific bits are carried in 2 places - embedded thread_struct in task_struct - associated thread_info (hoisted in task's stack page) and syntactically: (thread_info *)(task_struct->stack) ksp (dynamic kernel stack top) currently lives in thread_struct but given its deep location in task struct likely to cache miss when accessed from __switch_to(). Moving it to thread_info would be more efficient given proximity to frequently accessed items such as preempt_count thus very likely to be in cache, specially in schedular code. Note however that currently tsk.thread.ksp takes 1 memory access (off of tsk pointer) while new code tsk->stack.ksp would take 2, but likely to be in cache. Moreover if task is current the 2nd reference can be elided and instead derived from SP as (SP & ~(THREAD_SIZE - 1)) All of this also makes __switch_to() code simpler and we can see the 2 ways of retirving ksp (descrobed above) in new code. Signed-off-by: Vineet Gupta --- arch/arc/include/asm/processor.h | 3 +-- arch/arc/include/asm/thread_info.h | 10 +++++----- arch/arc/kernel/asm-offsets.c | 2 +- arch/arc/kernel/ctx_sw_asm.S | 22 ++++++++++------------ arch/arc/kernel/process.c | 6 +++--- 5 files changed, 20 insertions(+), 23 deletions(-) diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index 82ddc929d6e7..d606658e2fe7 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -22,7 +22,6 @@ * struct thread_info */ struct thread_struct { - unsigned long ksp; /* kernel mode stack pointer */ unsigned long callee_reg; /* pointer to callee regs */ unsigned long fault_address; /* dbls as brkpt holder as well */ #ifdef CONFIG_ARC_DSP_SAVE_RESTORE_REGS @@ -54,7 +53,7 @@ struct task_struct; * Where about of Task's sp, fp, blink when it was last seen in kernel mode. * Look in process.c for details of kernel stack layout */ -#define TSK_K_ESP(tsk) (tsk->thread.ksp) +#define TSK_K_ESP(tsk) (task_thread_info(tsk)->ksp) #define TSK_K_REG(tsk, off) (*((unsigned long *)(TSK_K_ESP(tsk) + \ sizeof(struct callee_regs) + off))) diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h index 6ba7fe417095..4c530cf131f3 100644 --- a/arch/arc/include/asm/thread_info.h +++ b/arch/arc/include/asm/thread_info.h @@ -37,16 +37,16 @@ */ struct thread_info { unsigned long flags; /* low level flags */ + unsigned long ksp; /* kernel mode stack top in __switch_to */ int preempt_count; /* 0 => preemptable, <0 => BUG */ - struct task_struct *task; /* main task structure */ - __u32 cpu; /* current CPU */ + int cpu; /* current CPU */ unsigned long thr_ptr; /* TLS ptr */ + struct task_struct *task; /* main task structure */ }; /* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. + * initilaize thread_info for any @tsk + * - this is not related to init_task per se */ #define INIT_THREAD_INFO(tsk) \ { \ diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index 37324fd9a72f..5b47d09b925e 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -20,13 +20,13 @@ int main(void) BLANK(); - DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); DEFINE(THREAD_CALLEE_REG, offsetof(struct thread_struct, callee_reg)); DEFINE(THREAD_FAULT_ADDR, offsetof(struct thread_struct, fault_address)); BLANK(); + DEFINE(THREAD_INFO_KSP, offsetof(struct thread_info, ksp)); DEFINE(THREAD_INFO_FLAGS, offsetof(struct thread_info, flags)); DEFINE(THREAD_INFO_PREEMPT_COUNT, offsetof(struct thread_info, preempt_count)); diff --git a/arch/arc/kernel/ctx_sw_asm.S b/arch/arc/kernel/ctx_sw_asm.S index 59d779004e64..48e1f21976ed 100644 --- a/arch/arc/kernel/ctx_sw_asm.S +++ b/arch/arc/kernel/ctx_sw_asm.S @@ -11,8 +11,6 @@ #include /* For the SAVE_* macros */ #include -#define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) - ; IN ; - r0: prev task (also current) ; - r1: next task @@ -37,19 +35,19 @@ ENTRY_CFI(__switch_to) /* kernel mode callee regs of @prev */ SAVE_CALLEE_SAVED_KERNEL - /* save final SP to @prev->thread.ksp */ -#if KSP_WORD_OFF <= 255 - st.as sp, [r0, KSP_WORD_OFF] -#else - /* Workaround for NR_CPUS=4k as ST.as can only take s9 offset */ - add2 r10, r0, KSP_WORD_OFF - st sp, [r10] -#endif + /* + * save final SP to @prev->thread_info.ksp + * @prev is "current" so thread_info derived from SP + */ + GET_CURR_THR_INFO_FROM_SP r10 + st sp, [r10, THREAD_INFO_KSP] + /* update @next in _current_task[] and GP register caching it */ SET_CURR_TASK_ON_CPU r1, r10 - /* load SP from @next->thread.ksp */ - ld.as sp, [r1, KSP_WORD_OFF] + /* load SP from @next->thread_info.ksp */ + ld r10, [r1, TASK_THREAD_INFO] + ld sp, [r10, THREAD_INFO_KSP] /* restore callee regs, stack frame regs of @next */ RESTORE_CALLEE_SAVED_KERNEL diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index 96f591508142..186ceab661eb 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -141,7 +141,7 @@ asmlinkage void ret_from_fork(void); * | unused | * | | * ------------------ - * | r25 | <==== top of Stack (thread.ksp) + * | r25 | <==== top of Stack (thread_info.ksp) * ~ ~ * | --to-- | (CALLEE Regs of kernel mode) * | r13 | @@ -181,14 +181,14 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) c_callee = ((struct callee_regs *)childksp) - 1; /* - * __switch_to() uses thread.ksp to start unwinding stack + * __switch_to() uses thread_info.ksp to start unwinding stack * For kernel threads we don't need to create callee regs, the * stack layout nevertheless needs to remain the same. * Also, since __switch_to anyways unwinds callee regs, we use * this to populate kernel thread entry-pt/args into callee regs, * so that ret_from_kernel_thread() becomes simpler. */ - p->thread.ksp = (unsigned long)c_callee; /* THREAD_KSP */ + task_thread_info(p)->ksp = (unsigned long)c_callee; /* THREAD_INFO_KSP */ /* __switch_to expects FP(0), BLINK(return addr) at top */ childksp[0] = 0; /* fp */ From patchwork Tue Aug 15 00:48:06 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f15-20020a056402160f00b005216d397e43si8798622edv.494.2023.08.15.03.33.34; Tue, 15 Aug 2023 03:34:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=C2veBvhq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233823AbjHOAtP (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233601AbjHOAs2 (ORCPT ); Mon, 14 Aug 2023 20:48:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B61C1710 for ; Mon, 14 Aug 2023 17:48:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CF57264582 for ; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 688D1C433CC; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060503; bh=lz9Xbt2pIM+wlhtUOQLjEgvHMc8ZUwQY9IxV1Z3dysI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C2veBvhqA9Z5n37BDVb5IeOyiO2dL8X+PUCyzC8dMAz1TLXEWC4f28/kkyWsldXEl hU+JwEP2W40YKQI6VrRs8vqoPUIKag5lDbi8fuLnXiUmSZtHdiJwrujRqSCRB94KC2 5+K8uV9N0Mb05RCuzXIeNqMAeaquTVMXC3XW30Y800PEBY2DFPbNqnoceN914KIaeo TpqwP0rGEytV3jKWGJMhK/1lrEpUajOngBkPai7FGAnvKdESft50UbjGPORwVDkI5Z Ye3F/Ix2Oh8IadPkgby4gEyIwp3bez5/kCSOoGWcELEOcwtXKs8apt/6ZCogY2ap8q ajk7EQEn/TtNA== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 13/20] ARC: entry: rework (non-functional) Date: Mon, 14 Aug 2023 17:48:06 -0700 Message-Id: <20230815004813.555115-14-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774290878033327657 X-GMAIL-MSGID: 1774290878033327657 - comments update - rename syscall_trace_entry - use PT_xxx in entry code Signed-off-by: Vineet Gupta --- arch/arc/include/asm/entry-arcv2.h | 23 ++++++++------ arch/arc/include/asm/entry-compact.h | 3 +- arch/arc/include/asm/ptrace.h | 2 +- arch/arc/kernel/asm-offsets.c | 1 + arch/arc/kernel/entry.S | 45 +++++++++++++--------------- arch/arc/kernel/ptrace.c | 2 +- 6 files changed, 39 insertions(+), 37 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 858742feab71..a38ed505b3de 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -48,14 +48,18 @@ /*------------------------------------------------------------------------*/ .macro INTERRUPT_PROLOGUE - ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following: + ; Before jumping to Interrupt Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0) ; 3. Auto save: (mandatory) Push PC and STAT32 on stack ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE - ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI + ; 4a. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI ; - ; (B) Manually saved some regs: r12,r30, sp,fp,gp, ACCL pair + ; Now + ; 4b. If Auto-save (optional) not enabled in hw, manually save them + ; 5. Manually save: r12,r30, sp,fp,gp, ACCL pair + ; + ; At the end, SP points to pt_regs #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE ; carve pt_regs on stack (case #3), PC/STAT32 already on stack @@ -73,13 +77,14 @@ /*------------------------------------------------------------------------*/ .macro EXCEPTION_PROLOGUE - ; (A) Before jumping to Exception Vector, hardware micro-ops did following: + ; Before jumping to Exception Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) ; - ; (B) Manually save the complete reg file below + ; Now manually save rest of reg file + ; At the end, SP points to pt_regs - sub sp, sp, SZ_PT_REGS ; carve pt_regs + sub sp, sp, SZ_PT_REGS ; carve space for pt_regs ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first @@ -136,8 +141,8 @@ ST2 gp, fp, PT_r26 ; gp (r26), fp (r27) - st r12, [sp, PT_sp + 4] - st r30, [sp, PT_sp + 8] + st r12, [sp, PT_r12] + st r30, [sp, PT_r30] ; Saving pt_regs->sp correctly requires some extra work due to the way ; Auto stack switch works @@ -244,7 +249,7 @@ btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP - ld r10, [sp, PT_event + 4] + ld r10, [sp, PT_bta] sr r10, [erbta] LD2 r10, r11, PT_ret diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index e3383e1cb040..4e2ae82779ed 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -170,12 +170,13 @@ PUSHAX erbta lr r10, [ecr] - st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */ + st r10, [sp, PT_event] #ifdef CONFIG_ARC_CURR_IN_REG /* gp already saved on stack: now load with "current" */ GET_CURR_TASK_ON_CPU gp #endif + ; OUTPUT: r10 has ECR expected by EV_Trap .endm /*-------------------------------------------------------------- diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index e9798f46cdc4..2bf8ea96ea21 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -75,7 +75,7 @@ struct pt_regs { unsigned long event; }; - unsigned long bta; /* bta_l1, bta_l2, erbta */ + unsigned long bta; /* erbta */ unsigned long r26; /* gp */ unsigned long fp; diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index 5b47d09b925e..e46688975868 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -47,6 +47,7 @@ int main(void) DEFINE(PT_status32, offsetof(struct pt_regs, status32)); DEFINE(PT_event, offsetof(struct pt_regs, event)); + DEFINE(PT_bta, offsetof(struct pt_regs, bta)); DEFINE(PT_sp, offsetof(struct pt_regs, sp)); DEFINE(PT_r0, offsetof(struct pt_regs, r0)); DEFINE(PT_r1, offsetof(struct pt_regs, r1)); diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index cd26e0fa5044..f291fc8476d7 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -160,20 +160,19 @@ END(EV_Extension) ; syscall Tracing ; --------------------------------------------- tracesys: - ; save EFA in case tracer wants the PC of traced task - ; using ERET won't work since next-PC has already committed + ; safekeep EFA (r12) if syscall tracer wanted PC + ; for traps, ERET is pre-commit so points to next-PC GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11 st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address - ; PRE Sys Call Ptrace hook - mov r0, sp ; pt_regs needed - bl @syscall_trace_entry + ; PRE syscall trace hook + mov r0, sp ; pt_regs + bl @syscall_trace_enter ; Tracing code now returns the syscall num (orig or modif) mov r8, r0 ; Do the Sys Call as we normally would. - ; Validate the Sys Call number cmp r8, NR_syscalls - 1 mov.hi r0, -ENOSYS bhi tracesys_exit @@ -190,36 +189,36 @@ tracesys: ld r6, [sp, PT_r6] ld r7, [sp, PT_r7] ld.as r9, [sys_call_table, r8] - jl [r9] ; Entry into Sys Call Handler + jl [r9] tracesys_exit: - st r0, [sp, PT_r0] ; sys call return value in pt_regs + st r0, [sp, PT_r0] - ;POST Sys Call Ptrace Hook + ; POST syscall trace hook mov r0, sp ; pt_regs needed bl @syscall_trace_exit - b ret_from_exception ; NOT ret_from_system_call at is saves r0 which - ; we'd done before calling post hook above + + ; don't call ret_from_system_call as it saves r0, already done above + b ret_from_exception ; --------------------------------------------- ; Breakpoint TRAP ; --------------------------------------------- trap_with_param: mov r0, r12 ; EFA in case ptracer/gdb wants stop_pc - mov r1, sp + mov r1, sp ; pt_regs - ; Save callee regs in case gdb wants to have a look - ; SP will grow up by size of CALLEE Reg-File + ; save callee regs in case tracer/gdb wants to peek SAVE_CALLEE_SAVED_USER - ; save location of saved Callee Regs @ thread_struct->pc + ; safekeep ref to callee regs GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10 st sp, [r10, THREAD_CALLEE_REG] - ; Call the trap handler + ; call the non syscall trap handler bl do_non_swi_trap - ; unwind stack to discard Callee saved Regs + ; unwind stack to discard callee regs DISCARD_CALLEE_SAVED_USER b ret_from_exception @@ -237,31 +236,27 @@ ENTRY(EV_Trap) FAKE_RET_FROM_EXCPN - ;============ TRAP 1 :breakpoints - ; Check ECR for trap with arg (PROLOGUE ensures r10 has ECR) + ;============ TRAP N : breakpoints, kprobes etc bmsk.f 0, r10, 7 bnz trap_with_param - ;============ TRAP (no param): syscall top level + ;============ TRAP 0 (no param): syscall - ; If syscall tracing ongoing, invoke pre-post-hooks + ; syscall tracing ongoing, invoke pre-post-hooks around syscall GET_CURR_THR_INFO_FLAGS r10 and.f 0, r10, _TIF_SYSCALL_WORK bnz tracesys ; this never comes back ;============ Normal syscall case - ; syscall num shd not exceed the total system calls avail cmp r8, NR_syscalls - 1 mov.hi r0, -ENOSYS bhi .Lret_from_system_call - ; Offset into the syscall_table and call handler ld.as r9,[sys_call_table, r8] - jl [r9] ; Entry into Sys Call Handler + jl [r9] .Lret_from_system_call: - st r0, [sp, PT_r0] ; sys call return value in pt_regs ; fall through to ret_from_exception diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c index 8226df3163fe..14ea7406f5cd 100644 --- a/arch/arc/kernel/ptrace.c +++ b/arch/arc/kernel/ptrace.c @@ -339,7 +339,7 @@ long arch_ptrace(struct task_struct *child, long request, return ret; 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Mon, 14 Aug 2023 17:48:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 96AAB64006 for ; Tue, 15 Aug 2023 00:48:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C98F9C433C7; Tue, 15 Aug 2023 00:48:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060504; bh=u267G5jkhUA2JZr0XnWTZStLuMWUHc9Rgpk/dYQh5G4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ASFBYNfgI8UKmQU2xybw7HWbdahnGkvkBKXmuux3FGHHYJr2LAor+IQiUoOX/yrZ+ IkJz8/kHlfOsarUPlnTgeDn51+heWIXsSabeIg6u4xPvzkMQeQINyS7/FQ73x86k49 fj/j70xVZRxghfaVJf9Mp7nhfi/u9CAuQAV1/LLxnJKExyh6dNN9UcTWUBdhPMenkU ftGLEbRHf9lY5lATxrfsqWL0/t8tlZVuEsFK21U3DoHNvOuBvyxX/RxIaP8CmrI5fK ej8ffxCfQaL3iXSAMbB6SoAnXsGaGC+jLwPveUJWB4EA7C04wmtRAxfTOSj0eMkNed VPKVKUMwHJWGQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 14/20] ARC: entry: ARcompact EV_ProtV to use r10 directly Date: Mon, 14 Aug 2023 17:48:07 -0700 Message-Id: <20230815004813.555115-15-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774277307855485554 X-GMAIL-MSGID: 1774277307855485554 Signed-off-by: Vineet Gupta --- arch/arc/kernel/entry-compact.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index 5cb0cd7e4eab..77f0090554c5 100644 --- a/arch/arc/kernel/entry-compact.S +++ b/arch/arc/kernel/entry-compact.S @@ -254,9 +254,8 @@ END(handle_interrupt_level1) ENTRY(EV_TLBProtV) - EXCEPTION_PROLOGUE + EXCEPTION_PROLOGUE ; ECR returned in r10 - mov r2, r10 ; ECR set into r10 already lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above) ; Exception auto-disables further Intr/exceptions. @@ -273,8 +272,7 @@ ENTRY(EV_TLBProtV) ; -Access Violation : 00_23_(00|01|02|03)_00 ; x r w r+w ; -Unaligned Access : 00_23_04_00 - ; - bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f + bbit1 r10, ECR_C_BIT_PROTV_MISALIG_DATA, 4f ;========= (6a) Access Violation Processing ======== bl do_page_fault From patchwork Tue Aug 15 00:48:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135608 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp136797vqo; Mon, 14 Aug 2023 18:24:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF064fajFuw0fuqPMgIobIQbjIPWrXAGf79VepZ0XLwdjqt48mvjpqlRtSnW2PMXtL32Z5P X-Received: by 2002:a05:6a00:24d4:b0:686:b94a:3879 with SMTP id d20-20020a056a0024d400b00686b94a3879mr12296302pfv.18.1692062651938; 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Mon, 14 Aug 2023 17:48:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EADB64BD3 for ; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3440DC433CB; Tue, 15 Aug 2023 00:48:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060504; bh=8tSfMGnAd50oKVThmqq7FfKvCcOhK1uCIhtjujNgeQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qSFPXhmTH+ypX1rtN/dHmPJaaNRWsqIQ7b4KRWeHq7rgad0ebhL2oshth6MtFfuuw DP7MaCtJ8wO/PNXsqee6Qcy7ULH8xyehvV5mXqSfkP5nNOkSYqrynfT1KsGSd2Dmbr J4y0QjriFENCS4lLHlkd50YQ851oqCGVeKObYb04NMXIqoFowkSE35TdT0gsODcBep vInYcQSJFrnWAvDF+hL0nRJu2y5t3o7E0gMrfQp0gEp0VzsdfEnuRhw0o9beRtPh7P CllckWVfnUx4neT5fms8LtjLoJ7uIC9/qfWg607LcRSdB8av52Iu6AeI8fCnMvJkOK wTDsgj9tuCvQg== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 15/20] ARC: entry: EV_MachineCheck dont re-read ECR Date: Mon, 14 Aug 2023 17:48:08 -0700 Message-Id: <20230815004813.555115-16-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774256287318411628 X-GMAIL-MSGID: 1774256287318411628 Signed-off-by: Vineet Gupta --- arch/arc/kernel/entry.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index f291fc8476d7..46582fbebcf2 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -95,16 +95,15 @@ END(instr_service) ENTRY(EV_MachineCheck) - EXCEPTION_PROLOGUE + EXCEPTION_PROLOGUE ; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id lw11-20020a170906bccb00b0099b4e5359besi11333700ejb.4.2023.08.15.20.47.18; Tue, 15 Aug 2023 20:47:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=rRaAtYIJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233781AbjHOAtN (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233605AbjHOAs2 (ORCPT ); Mon, 14 Aug 2023 20:48:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D6621738 for ; Mon, 14 Aug 2023 17:48:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1136C64C14 for ; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9BEC2C433C9; Tue, 15 Aug 2023 00:48:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060504; bh=DWOQf7BgGfqZ+22gQ6ffUoChhYoSGVqmPO66zjXjnNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rRaAtYIJ6piW19T/JUgE6niXrjB3KdxRAazmOMrDppMHSfM52f63T6aEi+IIbJ2Ec fvFr+005hVOjjhDKk+rv2byauQXCHICwX1BuYvGYPTgqvgKh521AlVHw5Sf4B7SGzI vWvCsuxT+fpqhk646EeqcV4vkJM/40+4MqE7fkSZU6n9wPQ4F0anTOrbCVXkTwdSBx 306lJaa3UwLFaZ8kqhRmFHeNBjHeDxG9BMqbJMiDZtWuOo1mFtogItc9whzgHaWl2c 3QiAJiVnE5FNxFASl2qCch8bq7257UbyNwz25roDzXupMZo909u1u2DWQjBEdu/MjU SC2VVjAveUQww== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 16/20] ARC: entry: Add more common chores to EXCEPTION_PROLOGUE Date: Mon, 14 Aug 2023 17:48:09 -0700 Message-Id: <20230815004813.555115-17-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774355915783932856 X-GMAIL-MSGID: 1774355915783932856 THe high level structure of most ARC exception handlers is 1. save regfile with EXCEPTION_PROLOGUE 2. setup r0: EFA (not part of pt_regs) 3. setup r1: pointer to pt_regs (SP) 4. drop down to pure kernel mode (from exception) 5. call the Linux "C" handler Remove the boiler plate code by moving #2, #3, #4 into #1. The exceptions to most exceptions are syscall Trap and Machine check which don't do some of above for various reasons, so call a newly introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original EXCEPTION_PROLOGUE) Signed-off-by: Vineet Gupta --- arch/arc/include/asm/entry-arcv2.h | 12 +++++++++++- arch/arc/include/asm/entry-compact.h | 12 +++++++++++- arch/arc/kernel/entry-arcv2.S | 15 --------------- arch/arc/kernel/entry-compact.S | 10 ---------- arch/arc/kernel/entry.S | 19 ++----------------- 5 files changed, 24 insertions(+), 44 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index a38ed505b3de..11b48ab39154 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -75,7 +75,7 @@ .endm /*------------------------------------------------------------------------*/ -.macro EXCEPTION_PROLOGUE +.macro EXCEPTION_PROLOGUE_KEEP_AE ; Before jumping to Exception Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack @@ -104,6 +104,16 @@ ; OUTPUT: r10 has ECR expected by EV_Trap .endm +.macro EXCEPTION_PROLOGUE + + EXCEPTION_PROLOGUE_KEEP_AE ; return ECR in r10 + + lr r0, [efa] + mov r1, sp + + FAKE_RET_FROM_EXCPN ; clobbers r9 +.endm + /*------------------------------------------------------------------------ * This macro saves the registers manually which would normally be autosaved * by hardware on taken interrupts. It is used by diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 4e2ae82779ed..a0e760eb35a8 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -140,7 +140,7 @@ * * After this it is safe to call the "C" handlers *-------------------------------------------------------------*/ -.macro EXCEPTION_PROLOGUE +.macro EXCEPTION_PROLOGUE_KEEP_AE /* Need at least 1 reg to code the early exception prologue */ PROLOG_FREEUP_REG r9, @ex_saved_reg1 @@ -179,6 +179,16 @@ ; OUTPUT: r10 has ECR expected by EV_Trap .endm +.macro EXCEPTION_PROLOGUE + + EXCEPTION_PROLOGUE_KEEP_AE ; return ECR in r10 + + lr r0, [efa] + mov r1, sp + + FAKE_RET_FROM_EXCPN ; clobbers r9 +.endm + /*-------------------------------------------------------------- * Restore all registers used by system call or Exceptions * SP should always be pointing to the next free stack element diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S index a7e6a2174187..2e49c81c8086 100644 --- a/arch/arc/kernel/entry-arcv2.S +++ b/arch/arc/kernel/entry-arcv2.S @@ -125,11 +125,6 @@ ENTRY(mem_service) EXCEPTION_PROLOGUE - lr r0, [efa] - mov r1, sp - - FAKE_RET_FROM_EXCPN - bl do_memory_error b ret_from_exception END(mem_service) @@ -138,11 +133,6 @@ ENTRY(EV_Misaligned) EXCEPTION_PROLOGUE - lr r0, [efa] ; Faulting Data address - mov r1, sp - - FAKE_RET_FROM_EXCPN - SAVE_CALLEE_SAVED_USER mov r2, sp ; callee_regs @@ -163,11 +153,6 @@ ENTRY(EV_TLBProtV) EXCEPTION_PROLOGUE - lr r0, [efa] ; Faulting Data address - mov r1, sp ; pt_regs - - FAKE_RET_FROM_EXCPN - mov blink, ret_from_exception b do_page_fault diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S index 77f0090554c5..c218285cff87 100644 --- a/arch/arc/kernel/entry-compact.S +++ b/arch/arc/kernel/entry-compact.S @@ -256,16 +256,6 @@ ENTRY(EV_TLBProtV) EXCEPTION_PROLOGUE ; ECR returned in r10 - lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above) - - ; Exception auto-disables further Intr/exceptions. - ; Re-enable them by pretending to return from exception - ; (so rest of handler executes in pure K mode) - - FAKE_RET_FROM_EXCPN - - mov r1, sp ; Handle to pt_regs - ;------ (5) Type of Protection Violation? ---------- ; ; ProtV Hardware Exception is triggered for Access Faults of 2 types diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index 46582fbebcf2..089f6680518f 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -80,11 +80,6 @@ ENTRY(instr_service) EXCEPTION_PROLOGUE - lr r0, [efa] - mov r1, sp - - FAKE_RET_FROM_EXCPN - bl do_insterror_or_kprobe b ret_from_exception END(instr_service) @@ -95,7 +90,7 @@ END(instr_service) ENTRY(EV_MachineCheck) - EXCEPTION_PROLOGUE ; ECR returned in r10 + EXCEPTION_PROLOGUE_KEEP_AE ; ECR returned in r10 lr r0, [efa] mov r1, sp @@ -128,11 +123,6 @@ ENTRY(EV_PrivilegeV) EXCEPTION_PROLOGUE - lr r0, [efa] - mov r1, sp - - FAKE_RET_FROM_EXCPN - bl do_privilege_fault b ret_from_exception END(EV_PrivilegeV) @@ -144,11 +134,6 @@ ENTRY(EV_Extension) EXCEPTION_PROLOGUE - lr r0, [efa] - mov r1, sp - - FAKE_RET_FROM_EXCPN - bl do_extension_fault b ret_from_exception END(EV_Extension) @@ -229,7 +214,7 @@ trap_with_param: ENTRY(EV_Trap) - EXCEPTION_PROLOGUE + EXCEPTION_PROLOGUE_KEEP_AE lr r12, [efa] From patchwork Tue Aug 15 00:48:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135926 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b82d:0:b0:3f2:4152:657d with SMTP id z13csp876167vqi; Thu, 17 Aug 2023 10:57:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHw9hwFT22tTQJ1Qu4aG8uKdiv9ajsSQ3M+2YIzrl1DlTxXvV2lUAjxe3I2cceBRch9V8T X-Received: by 2002:a05:6a20:13c5:b0:133:d17d:193a with SMTP id ho5-20020a056a2013c500b00133d17d193amr416012pzc.59.1692295076566; Thu, 17 Aug 2023 10:57:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692295076; cv=none; d=google.com; s=arc-20160816; b=q63ZWqQvUEoAGWmmp688UeZVi88JLg2NkRCrAFUDpDuzweUgewQZG9vmL7X2qhqOWj t7iSQfCEwcazaytX1Id4CI2+K/TD5N85ccT3qjg1UyP6WhEnSaFKzzSB9ou+FCl8Niqx TsVj+1v3fScGzKk/TTpzvlmfP8kB1pZcq1dyqS7+t/nQfwt/E3uk9KUFYL/ayxreC89e KnNPiHXIbIsPSuUuvhj8yuc0Fhqw6RS1DC3eu3RYlVMoIztmU/N2UUlS8MS09RRzZd9o 7eJYdH1x2MMzh+xyoMKddtqFNCAMWnXkpIheKyCAfuSEBaE33gR/UCPZ2SU6g55Ykse4 Km+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZPxU2WdACqPwsMFYIOSn86KNWj009MJYU2OxAl20CrQ=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=VN/TsM+QN3HGcMal4Gm5alGrqtux3Wf9BTiGUp3Bkr7BIlq6k1t7ieC/96Ta7SRkM+ b2mXXrUwKyK+o6a/a+NqYtgF3b+wTGYkgIxXNEJUDBSUuHI1P9CCV8zCMQIwdApnX7PD SPt/cOb2Dgucx6PfxEVMwa1bwrRTy60JZqH4RU+OR7yX7hjpZMJgzku/Fk/CJ30JEKf2 yEuIkcJAzWkMgG2oY53KdRXAXLxr4UcI5KzLKJ/u7PqVgk6gGrFhpZG+Xh9H6H4CoRWi 4qrXoZfKDzP2qiuYNVDo/p8a6P5EZIucgzV8/kY5PGP+6UUv2zf/aVQLWhoVuo+4gaU0 8XNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=t1jppoqe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i24-20020a63e918000000b0056554a5464fsi13989204pgh.787.2023.08.17.10.57.43; Thu, 17 Aug 2023 10:57:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=t1jppoqe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233759AbjHOAtL (ORCPT + 99 others); Mon, 14 Aug 2023 20:49:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233626AbjHOAs2 (ORCPT ); Mon, 14 Aug 2023 20:48:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0462A1739 for ; Mon, 14 Aug 2023 17:48:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D775164C2B for ; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B40AC433CD; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060505; bh=UNDMqVBFCNk6b1A03SE3areXfHWhTB+t/pNxpu/gslg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t1jppoqe4US9n9CGmBpjEdhEDn/TAzPypdmyx2qsmvGkC4Fsrvz1YK8nGKZPZIPtL KaP1p3emDMTLGqHKVl6INVBT4/rGCeH5Zmjt9w9mZnqk9FUuHIDk2zYUGhHporY5nB vBfmVQVHSkPQRKtiA/fLKb3DcQUBnPttO7yR75Td8mKu/SG1Dc/eC9R5C0G5Zb3BCo u8NweEctbBX9ulBOo/exaaNWIB/RgaMrXjp8jIPq4AZPBmcGhYfvX0Mrsou7LcO9AS 3W4xyDlz2wvr3Y2oQ2brfWCjaEGyWfueA+q1tY/zNdLDWIo2W050oXOEV0rF+57Hy3 Txbdvr4ocgh0A== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 17/20] ARC: entry: replace 8 byte OR with 4 byte BSET Date: Mon, 14 Aug 2023 17:48:10 -0700 Message-Id: <20230815004813.555115-18-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774500002279129549 X-GMAIL-MSGID: 1774500002279129549 FAKE_RET_FROM_EXCEPTION drops down to pure kernel mode. It currently has an 8 byte instruction which can be replaced with 4 byte BSET This is applicable to both ARCv2 and ARCv3 entr code. ARCv2 current ------------ 00000804 : ... 874: 216a 1280 lr r9,[status32] 878: 2146 1809 bic r9,r9,0x20 87c: 2105 1f89 8000 0000 or r9,r9,0x80000000 ^^^^^^^^^ 884: 2029 8240 kflag r9 ARCv2 after ---------- 000007e0 : ... 850: 216a 1280 lr r9,[status32] 854: 2150 1149 bclr r9,r9,0x5 858: 214f 17c9 bset r9,r9,0x1f 85c: 2029 8240 kflag r9 Signed-off-by: Vineet Gupta --- arch/arc/include/asm/entry-arcv2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 11b48ab39154..f7c9b3915d10 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -274,8 +274,8 @@ .macro FAKE_RET_FROM_EXCPN lr r9, [status32] - bic r9, r9, STATUS_AE_MASK - or r9, r9, STATUS_IE_MASK + bclr r9, r9, STATUS_AE_BIT + bset r9, r9, STATUS_IE_BIT kflag r9 .endm From patchwork Tue Aug 15 00:48:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135641 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp314308vqo; Tue, 15 Aug 2023 02:44:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzUf/UEMNxcsZMjgrpODp+bWAiSA53NwDC6oVWDfMDHqpPJtbkpwZJVaMOuN3AcjPbTM7I X-Received: by 2002:a19:6547:0:b0:4f8:6abe:5249 with SMTP id c7-20020a196547000000b004f86abe5249mr7632982lfj.3.1692092673773; Tue, 15 Aug 2023 02:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692092673; cv=none; d=google.com; s=arc-20160816; b=A6U07iRbyGF0KOhyXozaSXutK36+MhLryLYwdX42RiYi6El059OhzvvjYatlvDR/Ki UcEvT5/rMBMjqqsAiyiR1GdI4aQ5BAFWH9lAJy52VYQKkb6fb4FyNUac/Dw+tAHm0ew9 JIEWcLcEShR4PQoVzQSeorjoVlhmEJoFCFOFT2X2VE6UcmdxTsD1XgmgpfFtNoK+NzVk 22nhsEEuGs0EbSNPKB8TNN0QZdWhAEBkI0GA/2Vq0W23RhsQl6QWA7/7S4N0F3JrKgBl ZuYNqstnQQ7yKlCJcWCB1W8UL/W4SRJffKctwXpT5qp9IzJdzTGXH7k9TsJEPirz4TXM Kp4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8PpDo0GaENBY/ZwBTM+McebaoAQPTDXRRYKeOmyYrhM=; fh=pU3/8cu9yvGtRhZz+04fy928CRCHy2kGYoR0fnliYkk=; b=ev9K/TWPGhWO5afS8DBL99k2qhsg9BWLglW2LohfdM7oh48XBoI7Pz4YKrZmRVEFpa /oRvnyZacnuZV/3m8p+5KC2Qy3BjDVEsxtUe7TF1fkR2CjQDIOYf8L+XFFHmYHdR1nAH 5ZmCeFb9Pz/2x/QDQEmHQiba1TLl7Bd6i8oQvGc1tQaPMJrPHs+2ZM83N9UlGOTlmzvD ZZ0vVX5Y6m4jHiJb8FuQx1ZpMOy3EXW9ApghJhZkzvsr9LOC1BMfBJ8FH7HkNlUyLZTv LLGP2E1zZQza47SBSRlwCBEw6sl/z9B1Qug1EUiKH1s6o8dSZthPxLXbFyee+Pu89NIn u4tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ZQpQdGjS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Mon, 14 Aug 2023 17:48:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 42FA464BE3 for ; Tue, 15 Aug 2023 00:48:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70AADC433B8; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060505; bh=8yzb+sbCX12KdZw39xAAHItl2pY4cwsnTFjWa/DTVAQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZQpQdGjSNETNvnzLPZG3ecN/fOw0xs2lGstiz8aH9SZVlwB3ahjh3PEsWy7ulohdl XQFm+7zIVBfNYqRmAxxI5ib0lWi7Wd0npD8a3I+4HNsWXRelO5Fnl8MES+kZnNRrMi syDed7P/hUN2s6KTTmB0oZ0h93D6fAmuOmiWH5+wsGcP8pvD1V15tXky99Ppcf4upv vtEFZGSATQzsCUaesp8/gEt8hGbaVgcR/IfqXneMQ7jDfqurZT54VHcZBLO/rgr394 tNQtixRGJMXWkljhHEfXNTqf6Blcxi8Z2nZRFFF6vdt+Y0Lj+UQp0M6cZ8laM2Hw0j RsFwWUZyxgrNQ== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 18/20] ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne Date: Mon, 14 Aug 2023 17:48:11 -0700 Message-Id: <20230815004813.555115-19-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774287767246719885 X-GMAIL-MSGID: 1774287767246719885 ARCv2 current ------------ 000007e0 : 7e0: 2482 3c01 sub sp,sp,112 7e4: 1c28 3006 std r0r1,[sp,40] 7e8: 1c30 3086 std r2r3,[sp,48] 7ec: 1c38 3106 std r4r5,[sp,56] 7f0: 1c40 3186 std r6r7,[sp,64] 7f4: 1c48 3206 std r8r9,[sp,72] 7f8: 1c50 3286 std r10r11,[sp,80] 7fc: 1c58 37c0 st blink,[sp,88] 800: 1c0c 36c0 st fp,[sp,12] 804: 1c18 3680 st gp,[sp,24] 808: 1c10 3780 st r30,[sp,16] 80c: 1c14 3300 st r12,[sp,20] 810: 226a 1340 lr r10,[aux_user_sp] 814: 22ca 1702 mov.ne r10,sp 818: 22c0 1f82 0000 0070 add.ne r10,r10,0x70 ^^^^^^^^^ With fix -------- 000007b4 : 7b4: 2482 3c01 sub sp,sp,112 7b8: 1c28 3006 std r0r1,[sp,40] 7bc: 1c30 3086 std r2r3,[sp,48] 7c0: 1c38 3106 std r4r5,[sp,56] 7c4: 1c40 3186 std r6r7,[sp,64] 7c8: 1c48 3206 std r8r9,[sp,72] 7cc: 1c50 3286 std r10r11,[sp,80] 7d0: 1c58 37c0 st blink,[sp,88] 7d4: 1c0c 36c0 st fp,[sp,12] 7d8: 1c18 3680 st gp,[sp,24] 7dc: 1c10 3780 st r30,[sp,16] 7e0: 1c14 3300 st r12,[sp,20] 7e4: 226a 1340 lr r10,[aux_user_sp] 7e8: 22ca 1702 mov.ne r10,sp 7ec: 22d5 1722 add2.ne r10,r10,0x1c Signed-off-by: Vineet Gupta --- arch/arc/include/asm/entry-arcv2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index f7c9b3915d10..a030eae93d35 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -167,7 +167,7 @@ ; ISA requires ADD.nz to have same dest and src reg operands mov.nz r10, sp - add.nz r10, r10, SZ_PT_REGS ; K mode SP + add2.nz r10, r10, SZ_PT_REGS/4 ; K mode SP st r10, [sp, PT_sp] ; SP (pt_regs->sp) From patchwork Tue Aug 15 00:48:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135609 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp145651vqo; Mon, 14 Aug 2023 18:50:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHNKYZ3P/nJLAkBS7Mq9/gxCgbdYhLfVXXpTSM77JfwZ5BdvAeiFUK080vosS8f1qDOVVee X-Received: by 2002:a05:6358:7f1a:b0:133:b42:69ca with SMTP id p26-20020a0563587f1a00b001330b4269camr7481356rwn.18.1692064243799; Mon, 14 Aug 2023 18:50:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692064243; cv=none; d=google.com; s=arc-20160816; b=MjwkkXCyDcR/pCzxLt3yuK7OjtZNlE/B4qG7oO4pUhMohLDwZOefTwfX1fFjuDDeYX PdW8r2OnclHlUBri8b4ghjJZC61qnpLf2u82ryMypBWAWPOAccBazrHE51VFszMLjiJu 7PxUqFRJnNXJDvhyb5sOO9KTsWLCN9WEyU75VtEJA90upF7nDXZGmSriN1zasHCj/LAx GyazuElXfpoMIfjWIuTaNRrblhBm6jtN7euMbhwI3Y4Ha0KIS6Ks3Qq1XZz23snkOdNe DtbupQLkW7nKQwWGyfZo20DEgSrJ2Ior776qY/PgiB8fStUWDv4cfT/fQ97Z4PvnBduO lcAg== ARC-Message-Signature: i=1; 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Mon, 14 Aug 2023 17:48:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4330A64872 for ; Tue, 15 Aug 2023 00:48:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D26A6C433CA; Tue, 15 Aug 2023 00:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060506; bh=1BADrAn43TtzTGU0kqF+Zvl5nVwUsJU38y9W7psm8MY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eLNu23dD5QSdJObrGEnxdpemvcC+18UMeZE6hXgAPhHQsgLsKHCJpbuYRTXrmFiOV XwNeEPKWd4f4HEWCq8BmFzCLDFiq7h0eql8936uifKcufKQoRj7R3wP0JVBwCE/QPj +JfIgxZz9hNn/d/JRuVUApX33VjifohyA6IoCcpwoNfNKVt4Mth3WBgVRFQ6cpCFlw r+9GpehN5tWaVb+hponcVkSEs9p6BhGrX350OkycjBIlbxbNvd+KaodssBjtGJ3Ffa 5oq7iSd1G97VRfO4d2gQ8Y/hIZOhWB6lPdfCPecRf+CIANaA011C5RtKQydctsFS0F +pB5GqP/WaecA== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 19/20] ARCv2: entry: rearrange pt_regs slightly Date: Mon, 14 Aug 2023 17:48:12 -0700 Message-Id: <20230815004813.555115-20-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774257956893477889 X-GMAIL-MSGID: 1774257956893477889 Instead of r26,fp,sp,r12,r30 order as fp,r30,r12,r26,sp - keeps SP at well known position (right abive hardware autosave) - r26,r12 saved specifically for ARCv2 (and not in ARCv3) kept closer for easy ifdef'ry later Signed-off-by: Vineet Gupta --- arch/arc/include/asm/entry-arcv2.h | 12 ++++++------ arch/arc/include/asm/ptrace.h | 9 +++++---- arch/arc/kernel/asm-offsets.c | 7 ++++--- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index a030eae93d35..4d13320e0c1b 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -149,10 +149,10 @@ */ .macro __SAVE_REGFILE_SOFT - ST2 gp, fp, PT_r26 ; gp (r26), fp (r27) - - st r12, [sp, PT_r12] + st fp, [sp, PT_fp] ; r27 st r30, [sp, PT_r30] + st r12, [sp, PT_r12] + st r26, [sp, PT_r26] ; gp ; Saving pt_regs->sp correctly requires some extra work due to the way ; Auto stack switch works @@ -187,10 +187,10 @@ /*------------------------------------------------------------------------*/ .macro __RESTORE_REGFILE_SOFT - LD2 gp, fp, PT_r26 ; gp (r26), fp (r27) - - ld r12, [sp, PT_r12] + ld fp, [sp, PT_fp] ld r30, [sp, PT_r30] + ld r12, [sp, PT_r12] + ld r26, [sp, PT_r26] ; Restore SP (into AUX_USER_SP) only if returning to U mode ; - for K mode, it will be implicitly restored as stack is unwound diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index 2bf8ea96ea21..3a054b695f28 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -77,11 +77,10 @@ struct pt_regs { unsigned long bta; /* erbta */ - unsigned long r26; /* gp */ unsigned long fp; - unsigned long sp; /* user/kernel sp depending on where we came from */ - - unsigned long r12, r30; + unsigned long r30; + unsigned long r12; + unsigned long r26; /* gp */ #ifdef CONFIG_ARC_HAS_ACCL_REGS unsigned long r58, r59; /* ACCL/ACCH used by FPU / DSP MPY */ @@ -90,6 +89,8 @@ struct pt_regs { unsigned long DSP_CTRL; #endif + unsigned long sp; /* user/kernel sp depending on entry */ + /*------- Below list auto saved by h/w -----------*/ unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11; diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index e46688975868..478768c88f46 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -62,11 +62,9 @@ int main(void) DEFINE(PT_r26, offsetof(struct pt_regs, r26)); DEFINE(PT_ret, offsetof(struct pt_regs, ret)); DEFINE(PT_blink, offsetof(struct pt_regs, blink)); + OFFSET(PT_fp, pt_regs, fp); DEFINE(PT_lpe, offsetof(struct pt_regs, lp_end)); DEFINE(PT_lpc, offsetof(struct pt_regs, lp_count)); - DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); - DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); - #ifdef CONFIG_ISA_ARCV2 OFFSET(PT_r12, pt_regs, r12); OFFSET(PT_r30, pt_regs, r30); @@ -79,5 +77,8 @@ int main(void) OFFSET(PT_DSP_CTRL, pt_regs, DSP_CTRL); #endif + DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); + DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); + return 0; } From patchwork Tue Aug 15 00:48:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 135635 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:3f2:4152:657d with SMTP id x8csp291651vqo; Tue, 15 Aug 2023 01:43:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEKDlZlVI2nmDeI0tUloYJKtKNLN6HLKaFK6U8fE3BXd8d1X8zrI0Rm6reZF3SYaMHVTdsu X-Received: by 2002:a05:6808:158c:b0:3a1:e7fb:76fc with SMTP id t12-20020a056808158c00b003a1e7fb76fcmr16113296oiw.17.1692089026916; Tue, 15 Aug 2023 01:43:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692089026; cv=none; d=google.com; s=arc-20160816; b=d6cf8S8C5vwwjIfjzv1ZrMt8KdHuXgk4wD266K+DABAs38Ker4yzx5S20BcFyyG2yo GmlGf0gFvK9vyYrxc+p4GcyAgNttgfkoOqCwt8YJOdraWE0N8oRJgTjt2RhNC8QQBPr8 RaOqFVxsur0VOPqOBaFUjx83fcYwUXxyPtGYNRlulEeCK/IRQa8Es1ITU9WDtR65W5mg BjJISyToVANBFZ5u02A5DXlPa6JxO8t3tr7xh9WfbODru+EfVkCNTUBFg+T/w3HLasS4 crXkDDhqU2JmIPGAQy+Kllpt17iDt+zE7D4OCmNC/RT3dbVh8HonsVww7+P3VMZnTJ3d E+iA== ARC-Message-Signature: i=1; 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Mon, 14 Aug 2023 17:48:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0D67160B9D for ; Tue, 15 Aug 2023 00:48:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DF11C433C9; Tue, 15 Aug 2023 00:48:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060506; bh=QEDl/IHEChN9kap/CMDzsElMt/XGCzh6+0rqR7kcifs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SbX1hBMpvpq0DzM119asALPJPEMun258wift5k5TvzhnFzI6aenEsMcZYv8vWj9pg fD0tSYaAoc7RbF53FWrdropZrPKXIDgPH+gulFKX1ojHO0Fu1PCdr2sOWR/HZpQLBw uBYdGVN9ovqgsZnV+m6Myr4LqayiDKlJn0YsajAwC6B9oxJ1vr9s/gZ/Evhyb7BBNW zD0KTZm58jDqgjBPpIOBC7N67F5TVzXX2hqoM14MgWut6/E4D+jJo0xvj/ajnHzwxe U5q3BnbcQoIvinTHvROJblhjEB368NYhZjstiWkz3CNFM+AOfIyIDdd2ega+ssESYc QAmUSXGfzkFLw== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 20/20] ARC: pt_regs: create seperate type for ecr Date: Mon, 14 Aug 2023 17:48:13 -0700 Message-Id: <20230815004813.555115-21-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774283943308639824 X-GMAIL-MSGID: 1774283943308639824 Reduces duplication in each ISA specific pt_regs Signed-off-by: Vineet Gupta --- arch/arc/include/asm/ptrace.h | 45 +++++++++++++--------------------- arch/arc/kernel/asm-offsets.c | 2 +- arch/arc/kernel/kgdb.c | 2 +- arch/arc/kernel/ptrace.c | 4 +-- arch/arc/kernel/traps.c | 4 +-- arch/arc/kernel/troubleshoot.c | 13 +++++----- arch/arc/mm/fault.c | 6 ++--- 7 files changed, 32 insertions(+), 44 deletions(-) diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index 3a054b695f28..724e3fe31ed5 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -12,6 +12,17 @@ #ifndef __ASSEMBLY__ +typedef union { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned long state:8, vec:8, cause:8, param:8; +#else + unsigned long param:8, cause:8, vec:8, state:8; +#endif + }; + unsigned long full; +} ecr_reg; + /* THE pt_regs: Defines how regs are saved during entry into kernel */ #ifdef CONFIG_ISA_ARCOMPACT @@ -40,18 +51,7 @@ struct pt_regs { * Last word used by Linux for extra state mgmt (syscall-restart) * For interrupts, use artificial ECR values to note current prio-level */ - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned long state:8, ecr_vec:8, - ecr_cause:8, ecr_param:8; -#else - unsigned long ecr_param:8, ecr_cause:8, - ecr_vec:8, state:8; -#endif - }; - unsigned long event; - }; + ecr_reg ecr; }; #define MAX_REG_OFFSET offsetof(struct pt_regs, event) @@ -62,18 +62,7 @@ struct pt_regs { unsigned long orig_r0; - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned long state:8, ecr_vec:8, - ecr_cause:8, ecr_param:8; -#else - unsigned long ecr_param:8, ecr_cause:8, - ecr_vec:8, state:8; -#endif - }; - unsigned long event; - }; + ecr_reg ecr; /* Exception Cause Reg */ unsigned long bta; /* erbta */ @@ -131,13 +120,13 @@ struct callee_regs { /* return 1 if PC in delay slot */ #define delay_mode(regs) ((regs->status32 & STATUS_DE_MASK) == STATUS_DE_MASK) -#define in_syscall(regs) ((regs->ecr_vec == ECR_V_TRAP) && !regs->ecr_param) -#define in_brkpt_trap(regs) ((regs->ecr_vec == ECR_V_TRAP) && regs->ecr_param) +#define in_syscall(regs) ((regs->ecr.vec == ECR_V_TRAP) && !regs->ecr.param) +#define in_brkpt_trap(regs) ((regs->ecr.vec == ECR_V_TRAP) && regs->ecr.param) #define STATE_SCALL_RESTARTED 0x01 -#define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED) -#define syscall_restartable(reg) !(reg->state & STATE_SCALL_RESTARTED) +#define syscall_wont_restart(regs) (regs->ecr.state |= STATE_SCALL_RESTARTED) +#define syscall_restartable(regs) !(regs->ecr.state & STATE_SCALL_RESTARTED) #define current_pt_regs() \ ({ \ diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index 478768c88f46..f77deb799175 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -46,7 +46,7 @@ int main(void) BLANK(); DEFINE(PT_status32, offsetof(struct pt_regs, status32)); - DEFINE(PT_event, offsetof(struct pt_regs, event)); + DEFINE(PT_event, offsetof(struct pt_regs, ecr)); DEFINE(PT_bta, offsetof(struct pt_regs, bta)); DEFINE(PT_sp, offsetof(struct pt_regs, sp)); DEFINE(PT_r0, offsetof(struct pt_regs, r0)); diff --git a/arch/arc/kernel/kgdb.c b/arch/arc/kernel/kgdb.c index 345a0000554c..4f2b5951454f 100644 --- a/arch/arc/kernel/kgdb.c +++ b/arch/arc/kernel/kgdb.c @@ -175,7 +175,7 @@ void kgdb_trap(struct pt_regs *regs) * with trap_s 4 (compiled) breakpoints, continuation needs to * start after the breakpoint. */ - if (regs->ecr_param == 3) + if (regs->ecr.param == 3) instruction_pointer(regs) -= BREAK_INSTR_SIZE; kgdb_handle_exception(1, SIGTRAP, 0, regs); diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c index 14ea7406f5cd..e0c233c178b1 100644 --- a/arch/arc/kernel/ptrace.c +++ b/arch/arc/kernel/ptrace.c @@ -46,7 +46,7 @@ static const struct pt_regs_offset regoffset_table[] = { REG_OFFSET_NAME(r0), REG_OFFSET_NAME(sp), REG_OFFSET_NAME(orig_r0), - REG_OFFSET_NAME(event), + REG_OFFSET_NAME(ecr), REG_OFFSET_END, }; @@ -54,7 +54,7 @@ static const struct pt_regs_offset regoffset_table[] = { static const struct pt_regs_offset regoffset_table[] = { REG_OFFSET_NAME(orig_r0), - REG_OFFSET_NAME(event), + REG_OFFSET_NAME(ecr), REG_OFFSET_NAME(bta), REG_OFFSET_NAME(r26), REG_OFFSET_NAME(fp), diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c index 2f7eb786695b..9b9570b79362 100644 --- a/arch/arc/kernel/traps.c +++ b/arch/arc/kernel/traps.c @@ -110,9 +110,7 @@ void do_machine_check_fault(unsigned long address, struct pt_regs *regs) */ void do_non_swi_trap(unsigned long address, struct pt_regs *regs) { - unsigned int param = regs->ecr_param; - - switch (param) { + switch (regs->ecr.param) { case 1: trap_is_brkpt(address, regs); break; diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c index 7654c2e42dc0..d5b3ed2c58f5 100644 --- a/arch/arc/kernel/troubleshoot.c +++ b/arch/arc/kernel/troubleshoot.c @@ -115,8 +115,8 @@ static void show_ecr_verbose(struct pt_regs *regs) /* For Data fault, this is data address not instruction addr */ address = current->thread.fault_address; - vec = regs->ecr_vec; - cause_code = regs->ecr_cause; + vec = regs->ecr.vec; + cause_code = regs->ecr.cause; /* For DTLB Miss or ProtV, display the memory involved too */ if (vec == ECR_V_DTLB_MISS) { @@ -154,7 +154,7 @@ static void show_ecr_verbose(struct pt_regs *regs) pr_cont("Misaligned r/w from 0x%08lx\n", address); #endif } else if (vec == ECR_V_TRAP) { - if (regs->ecr_param == 5) + if (regs->ecr.param == 5) pr_cont("gcc generated __builtin_trap\n"); } else { pr_cont("Check Programmer's Manual\n"); @@ -184,9 +184,10 @@ void show_regs(struct pt_regs *regs) if (user_mode(regs)) show_faulting_vma(regs->ret); /* faulting code, not data */ - pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\nSTAT: 0x%08lx", - regs->event, current->thread.fault_address, regs->ret, - regs->status32); + pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n", + regs->ecr.full, current->thread.fault_address, regs->ret); + + pr_info("STAT32: 0x%08lx", regs->status32); #define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : "" diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c index 26e5823c5710..95119a5e7761 100644 --- a/arch/arc/mm/fault.c +++ b/arch/arc/mm/fault.c @@ -100,10 +100,10 @@ void do_page_fault(unsigned long address, struct pt_regs *regs) if (faulthandler_disabled() || !mm) goto no_context; - if (regs->ecr_cause & ECR_C_PROTV_STORE) /* ST/EX */ + if (regs->ecr.cause & ECR_C_PROTV_STORE) /* ST/EX */ write = 1; - else if ((regs->ecr_vec == ECR_V_PROTV) && - (regs->ecr_cause == ECR_C_PROTV_INST_FETCH)) + else if ((regs->ecr.vec == ECR_V_PROTV) && + (regs->ecr.cause == ECR_C_PROTV_INST_FETCH)) exec = 1; flags = FAULT_FLAG_DEFAULT;