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Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sricharan Ramabadhran Signed-off-by: Sricharan Ramabadhran Signed-off-by: Varadarajan Narayanan --- v7: Move 'compatible' to be the first entry In the example have 'usb-phy' instead of 'usb2-phy' Add 'Reviewed-by: Krzysztof Kozlowski' 'make dt_binding_check DT_SCHEMA_FILES=qcom,ipq5332-usb-hsphy.yaml' passed 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom,ipq5332-usb-hsphy.yaml dtbs_check' passed v6: Add 'Co-developed-by: Sricharan' Add 'const' to compatible, vdd-supply Remove label and use usb2-phy for nodename in the example v5: Add '#phy-cells', to be able to use generic phy Remove 'Reviewed-by: Krzysztof Kozlowski' due to above change v4: Move M31 URL to description Remove maxItems and relevant content from clock-names Change node name to generic name 'make dt_binding_check DT_SCHEMA_FILES=qcom' passed v3: Incorporate review comments. Will bring in ipq5018 compatible string while posting ipq5018 usb patchset. v1: Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml Drop default binding "m31,usb-hsphy" Add clock Remove 'oneOf' from compatible Remove 'qscratch' region from register space as it is not needed Remove reset-names Fix the example definition --- .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml new file mode 100644 index 0000000..2671a04 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: M31 USB PHY + +maintainers: + - Sricharan Ramabadhran + - Varadarajan Narayanan + +description: + USB M31 PHY (https://www.m31tech.com) found in Qualcomm + IPQ5018, IPQ5332 SoCs. + +properties: + compatible: + items: + - const: qcom,ipq5332-usb-hsphy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cfg_ahb + + resets: + maxItems: 1 + + vdd-supply: + description: + Phandle to 5V regulator supply to PHY digital circuit. + +additionalProperties: false + +examples: + - | + #include + usb-phy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "cfg_ahb"; + + #phy-cells = <0>; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + + vdd-supply = <®ulator_fixed_5p0>; + }; From patchwork Mon Aug 14 08:06:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 135216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp2599449vqi; Mon, 14 Aug 2023 01:28:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHXWrDUOvpO37paYhah3/WF+McXiHLJLTdN3lTAwNKFjI2xRaQnc60Z/0BFWfmmrDNZAD0Y X-Received: by 2002:a05:6402:184c:b0:51e:362d:b172 with SMTP id v12-20020a056402184c00b0051e362db172mr6540906edy.32.1692001710982; Mon, 14 Aug 2023 01:28:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692001710; cv=none; d=google.com; s=arc-20160816; b=M3oWRwXvQ4HgLBV/4dFTelsi2X0aY2yGup00pWifb5gG5yqRcaM5xRdd0z5yzrU18C tS4PxAglunbDkJjuXjVNlB5zo7T8CcPzUHLZ3YtwnjgryL0ZtV9HPQMWI0sNQ9LGv173 TFP4rJE68X4FuFwtLgcF2YXxCf8u4KqRBlQe56B4mykZwpXMAi7YxWAhJ8YSwAaLqUXz 8gSIFClZ20Yzn18/4qTOHPwlhurW2U5FX+xrsqFg3ml0HDdfa8J/daEtPnhD4px1PcTj OE+dArxF1D59nQXrekJQ4X50elAxFFman4RXc2Z9hNEWR6m8PUS6NuCga6PKxjEk1V4a 9oNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=c1XxotIfgEZhTv+JF9U5BxxuXAXFBJ/jxr22/bY6Pgo=; fh=0k2HJcQX94dKFWJ5tuN/W9uwe9Rj3tjxabABZ2i+WP0=; b=Vc39HXU690poaArb/RSnwqitVl/zko6ZzsqF8w3V4HN3GIKDfOGC+H3L1G09xbYguB UOMBUbdRJ8iUMZV7QzM8BAOYFFG7OzLTKi+cVjm/N83ouHJ7AYGlNAAEdL4sDJe1fxhV w0m+hY8TLeUzpRV+Gth0fl/XYi4/LcaOQ0n5uaz0fV9o0g/x1qdVVDKrwAgpwZFlx1TM dDQKMWm/BP4Bcg/0OlQpooGa2aSelsE7yXgviTit4O3OdddCiBVTH1eThze6TO1jAT5N fCpjjz1I7j4miSfMZwceHPkV3m6K/JkUjXhC1PDg3D/ScVipVjHTD+ErbpCrbk2DdBSU F7JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="g9oO5cv/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan Reviewed-by: Bjorn Andersson --- v8: Change commit subject and message per review comments Don't include of_platform.h Change struct init coding style GENMASK -> BIT for one define v6: Kconfig:Add COMPILE_TEST and remove USB_GADGET from 'depends' Change 'selects' USB_PHY -> GENERIC_PHY Driver: Use correct headers const int -> unsigned int for 'nregs' in private data Use generic names for clk, phy in m31 phy structure Init register details directly instead of using macro Use dev_err_probe in the error paths of driver probe v5: Kconfig and Makefile:- place snippet according to sorted order Use generic phy instead of usb-phy Use ARRAY_SIZE for reg init instead of blank last entry Fix copyright year v4: Remove unused enum Error handling for devm_clk_get v1: Combine driver, makefile and kconfig into 1 patch Remove 'qscratch' region and its usage. The controller driver takes care of those settings Use compatible/data to handle ipq5332 init Drop the default case Get resources by index instead of name as there is only one resource Add clock Fix review comments in the driver --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-m31.c | 294 ++++++++++++++++++++++++++++++++++++ 3 files changed, 306 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index ced6038..d891058 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -143,6 +143,17 @@ config PHY_QCOM_EUSB2_REPEATER PMICs. The repeater is paired with a Synopsys eUSB2 Phy on Qualcomm SOCs. +config PHY_QCOM_M31_USB + tristate "Qualcomm M31 HS PHY driver support" + depends on USB && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable this to support M31 HS PHY transceivers on Qualcomm chips + with DWC3 USB core. It handles PHY initialization, clock + management required after resetting the hardware and power + management. This driver is required even for peripheral only or + host only mode configurations. + config PHY_QCOM_USB_HS tristate "Qualcomm USB HS PHY module" depends on USB_ULPI_BUS diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index df94581..ffd609a 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o +obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c new file mode 100644 index 0000000..ed08072 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-m31.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2014-2023, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB2PHY_PORT_UTMI_CTRL1 0x40 + +#define USB2PHY_PORT_UTMI_CTRL2 0x44 + #define UTMI_ULPI_SEL BIT(7) + #define UTMI_TEST_MUX_SEL BIT(6) + +#define HS_PHY_CTRL_REG 0x10 + #define UTMI_OTG_VBUS_VALID BIT(20) + #define SW_SESSVLD_SEL BIT(28) + +#define USB_PHY_UTMI_CTRL0 0x3c + +#define USB_PHY_UTMI_CTRL5 0x50 + #define POR_EN BIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54 + #define COMMONONN BIT(7) + #define FSEL BIT(4) + #define RETENABLEN BIT(3) + #define FREQ_24MHZ (BIT(6) | BIT(4)) + +#define USB_PHY_HS_PHY_CTRL2 0x64 + #define USB2_SUSPEND_N_SEL BIT(3) + #define USB2_SUSPEND_N BIT(2) + #define USB2_UTMI_CLK_EN BIT(1) + +#define USB_PHY_CFG0 0x94 + #define UTMI_PHY_OVERRIDE_EN BIT(1) + +#define USB_PHY_REFCLK_CTRL 0xa0 + #define CLKCORE BIT(1) + +#define USB2PHY_PORT_POWERDOWN 0xa4 + #define POWER_UP BIT(0) + #define POWER_DOWN 0 + +#define USB_PHY_FSEL_SEL 0xb8 + #define FREQ_SEL BIT(0) + +#define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc + #define USB2_0_TX_ENABLE BIT(2) + +#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8 + #define HSTX_SLEW_RATE_565PS GENMASK(1, 0) + #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3) + #define ODT_VALUE_38_02_OHM GENMASK(7, 6) + +#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc + #define ODT_VALUE_45_02_OHM BIT(2) + #define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0) + +#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4 + #define XCFG_COARSE_TUNE_NUM BIT(1) + #define XCFG_FINE_TUNE_NUM BIT(3) + +struct m31_phy_regs { + u32 off; + u32 val; + u32 delay; +}; + +struct m31_priv_data { + bool ulpi_mode; + const struct m31_phy_regs *regs; + unsigned int nregs; +}; + +struct m31_phy_regs m31_ipq5332_regs[] = { + { + USB_PHY_CFG0, + UTMI_PHY_OVERRIDE_EN, + 0 + }, + { + USB_PHY_UTMI_CTRL5, + POR_EN, + 15 + }, + { + USB_PHY_FSEL_SEL, + FREQ_SEL, + 0 + }, + { + USB_PHY_HS_PHY_CTRL_COMMON0, + COMMONONN | FREQ_24MHZ | RETENABLEN, + 0 + }, + { + USB_PHY_UTMI_CTRL5, + POR_EN, + 0 + }, + { + USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN, + 0 + }, + { + USB2PHY_USB_PHY_M31_XCFGI_11, + XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, + 0 + }, + { + USB2PHY_USB_PHY_M31_XCFGI_4, + HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM, + 0 + }, + { + USB2PHY_USB_PHY_M31_XCFGI_1, + USB2_0_TX_ENABLE, + 0 + }, + { + USB2PHY_USB_PHY_M31_XCFGI_5, + ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA, + 4 + }, + { + USB_PHY_UTMI_CTRL5, + 0x0, + 0 + }, + { + USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N | USB2_UTMI_CLK_EN, + 0 + }, +}; + +struct m31usb_phy { + struct phy *phy; + void __iomem *base; + const struct m31_phy_regs *regs; + int nregs; + + struct regulator *vreg; + struct clk *clk; + struct reset_control *reset; + + bool ulpi_mode; +}; + +static int m31usb_phy_init(struct phy *phy) +{ + struct m31usb_phy *qphy = phy_get_drvdata(phy); + const struct m31_phy_regs *regs = qphy->regs; + int i, ret; + + ret = regulator_enable(qphy->vreg); + if (ret) { + dev_err(&phy->dev, "failed to enable regulator, %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(qphy->clk); + if (ret) { + if (qphy->vreg) + regulator_disable(qphy->vreg); + dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); + return ret; + } + + /* Perform phy reset */ + reset_control_assert(qphy->reset); + udelay(5); + reset_control_deassert(qphy->reset); + + /* configure for ULPI mode if requested */ + if (qphy->ulpi_mode) + writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2); + + /* Enable the PHY */ + writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN); + + /* Turn on phy ref clock */ + for (i = 0; i < qphy->nregs; i++) { + writel(regs[i].val, qphy->base + regs[i].off); + if (regs[i].delay) + udelay(regs[i].delay); + } + + return 0; +} + +static int m31usb_phy_shutdown(struct phy *phy) +{ + struct m31usb_phy *qphy = phy_get_drvdata(phy); + + /* Disable the PHY */ + writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN); + + clk_disable_unprepare(qphy->clk); + + regulator_disable(qphy->vreg); + + return 0; +} + +static const struct phy_ops m31usb_phy_gen_ops = { + .power_on = m31usb_phy_init, + .power_off = m31usb_phy_shutdown, + .owner = THIS_MODULE, +}; + +static int m31usb_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + const struct m31_priv_data *data; + struct device *dev = &pdev->dev; + struct m31usb_phy *qphy; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + qphy->reset = devm_reset_control_get_exclusive_by_index(dev, 0); + if (IS_ERR(qphy->reset)) + return PTR_ERR(qphy->reset); + + qphy->clk = devm_clk_get(dev, NULL); + if (IS_ERR(qphy->clk)) + return dev_err_probe(dev, PTR_ERR(qphy->clk), + "failed to get clk\n"); + + data = of_device_get_match_data(dev); + qphy->regs = data->regs; + qphy->nregs = data->nregs; + qphy->ulpi_mode = data->ulpi_mode; + + qphy->phy = devm_phy_create(dev, NULL, &m31usb_phy_gen_ops); + if (IS_ERR(qphy->phy)) + return dev_err_probe(dev, PTR_ERR(qphy->phy), + "failed to create phy\n"); + + qphy->vreg = devm_regulator_get(dev, "vdda-phy"); + if (IS_ERR(qphy->vreg)) + return dev_err_probe(dev, PTR_ERR(qphy->phy), + "failed to get vreg\n"); + + phy_set_drvdata(qphy->phy, qphy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered M31 USB phy\n"); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct m31_priv_data m31_ipq5332_data = { + .ulpi_mode = false, + .regs = m31_ipq5332_regs, + .nregs = ARRAY_SIZE(m31_ipq5332_regs), +}; + +static const struct of_device_id m31usb_phy_id_table[] = { + { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, m31usb_phy_id_table); + +static struct platform_driver m31usb_phy_driver = { + .probe = m31usb_phy_probe, + .driver = { + .name = "qcom-m31usb-phy", + .of_match_table = m31usb_phy_id_table, + }, +}; + +module_platform_driver(m31usb_phy_driver); + +MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Aug 14 08:06:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 135232 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp2606754vqi; Mon, 14 Aug 2023 01:48:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFefbRHTrqjpYSsR42bA4637K6WhTUTcb9tj70R93Nq8YX5psXeP1GyVNwC7UZ52EU5/Uc9 X-Received: by 2002:a05:6a20:8f29:b0:126:42ce:bd44 with SMTP id b41-20020a056a208f2900b0012642cebd44mr15581985pzk.17.1692002888400; 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Signed-off-by: Varadarajan Narayanan --- v6: Remove clock names Move the nodes to address sorted location v5: Use generic phy instead of usb-phy 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check' passed 'DT_CHECKER_FLAGS='-v -m' DT_SCHEMA_FILES=qcom dt_binding_check' passed v4: Change node name Remove blank line 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed v1: Rename phy node Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy Remove 'qscratch' from phy node Fix alignment and upper-case hex no.s Add clock definition for the phy Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() in dwc3/core.c takes the frequency from ref clock and calculates fladj as appropriate. --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db..c45d9d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -145,6 +145,19 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + usbphy0: phy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; @@ -290,6 +303,48 @@ status = "disabled"; }; + usb: usb2@8a00000 { + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + + interrupts = ; + interrupt-names = "hs_phy_irq"; + + clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "core", + "iface", + "sleep", + "mock_utmi"; + + resets = <&gcc GCC_USB_BCR>; + + qcom,select-utmi-as-pipe-clk; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + usb2_0_dwc: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x08a00000 0xe000>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = ; + phy-names = "usb2-phy"; + phys = <&usbphy0>; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ From patchwork Mon Aug 14 08:06:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 135227 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp2605753vqi; Mon, 14 Aug 2023 01:45:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG57ub03nopdo0ESQhHD443Nltk7FYovzTDqcgN8Jx4AMIidPESprAq/tSCmHXeWG9JsUt6 X-Received: by 2002:a17:902:a402:b0:1bd:c485:e0c8 with SMTP id p2-20020a170902a40200b001bdc485e0c8mr7458678plq.17.1692002715840; Mon, 14 Aug 2023 01:45:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692002715; cv=none; d=google.com; s=arc-20160816; b=je3t2YxRZHipzMWdA1YsI0qYoFhDYPKlrby9LuhPWXEN65AMBMeWQHyq97I+Dl/0tE XyR5sjjKywLod1FzOC1kBaEwUZ664ENFk4QK8PYfjFUQtTbpbeb35/ZyjdJ8aVAckHQ0 UCcY9T4Wtvhl8CFv/9+JlU0AtbZ/R9+6dWy38it5ayt0oAKuQ/gNEU/UjfZP+oG/FT67 ClKDqdSsEb8i6w/CQXMmmZwBcQoa3R0UMTH+WXqxY3nrQLEexOoLF3JaT+U8ZQEyoMRH /t78c1vUegiyqhh5gExwk1jQgGwKlHAF22nLmN/H3UDkHfAxfzfmqqPEAh0BFLV5fidF YxFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=qs9N8rfFTVwVbHCl3QcliIEoiN2bxMMKsoxhS6BMiLo=; fh=0k2HJcQX94dKFWJ5tuN/W9uwe9Rj3tjxabABZ2i+WP0=; b=Whd3ByqHSlAflaafdD6AXtCJqok4Emfnk1qBEmwnBZbWl1kB9U4LWQRvOPNA/2GpzC CCflZXYgOaHD0dWChf8G2MpTaG3NiQ7C4wIzDCxxSaree4zbq6cyiw0RIXqaJxLPb/Ec PfHrL85ricKDHSGWLZdH+DdCmaUqVWW9UmbJH9B9jGAFTuWPZDknOfSTpCLpzwt8xdZA ecgk49YzdIgFCUVzuKm+KONjbzw7R4wTIn56GVcScfTsffNalT5Jr2gReAp/fLm2/z1A NsvJfVH5n6cX27TJ7Xm5sUOCfmS/Y+jOz1jhLJZ7LMGCRHa7/IMPT8ZRk+aiTGnyEgnZ QuiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kssEuOnN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan --- v6: Add vdd-supply and corresponding regulator v1: Enable usb-phy node --- arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index f96b0c8..b4099a2f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -12,6 +12,15 @@ / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6"; compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332"; + + regulator_fixed_5p0: s0500 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_5p0"; + }; }; &blsp1_spi0 { @@ -79,3 +88,17 @@ bias-pull-up; }; }; + +&usbphy0 { + vdd-supply = <®ulator_fixed_5p0>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb2_0_dwc { + dr_mode = "host"; +}; From patchwork Mon Aug 14 08:06:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 135264 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp2625836vqi; Mon, 14 Aug 2023 02:36:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF0TmLfyuEQuhIQeU1w4cloONpSuEyqY//mQueIUJY3LShLvRft3DjqZYxMXAW1CJgUdr8n X-Received: by 2002:a05:6a20:7354:b0:13f:53b1:c05d with SMTP id v20-20020a056a20735400b0013f53b1c05dmr8593727pzc.47.1692005771502; Mon, 14 Aug 2023 02:36:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692005771; cv=none; d=google.com; s=arc-20160816; b=VyVj9NTmp3bTW09we/pJy7Vl35IRMZogaeaXQ0WzPa5DwQ6oxCdhnt4BNMx3os5HSg 5zWYwHIfzBShSP8u0qWZECKfc6dJr9dxM+YbD8FTDLc66h7OMPTBbnj9mddB9eop+Ovb lOjiw9s1My5zeyhypx8HyG0uCUQ2mVR7rCCcZZvHGRNuRXu/Qw8BkFKA0sR80w3EurTA c942MoGFATdDQOjWHiNtNLuxKmyOO8n/mGLovR9HUV08t2ASZr1PeYrw5Sh8wfO3CAq4 KoBLiDVrnGBXhe77nR4hbrDSQm8gleG2cIKi2RXhxpJNmmFpzs7ea50oeu/meXjPswat 1fhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=i62uhHykeo0dVzCMO8QhNLNMVqEDeRoKE1YJQDPMeQk=; fh=0k2HJcQX94dKFWJ5tuN/W9uwe9Rj3tjxabABZ2i+WP0=; b=A9n8AmLmSytOMLicFnYzsIZyr+xaqPM77yTUScTBGXiYhvWzz16wdQARuTgKQHE2qw 8OsHmCzabetWWW55Mp0bP7ldn5SNM+X5TJdqVB8kTmpA/cWzKVjYAQTeGS3Q3+uOCq0w kRArWKFQ2vvaqTLGDt3Xj5YEcwuy2rQZRj7mpD0ZWfK+ZMLcY1iarjh/eUH1lwhodEeE ge34RuYI4EBtkLNEahvr6inqKbeinAcH+aqx/8rS3lkWC9/AXsaDDIKkcAgFmzwiG9hh O+zg8salXbEzm3+Td/gVXjUBjVR4lE/9bbpAjDO6uVNWbIs0jgSprcrgQkq7GpL//EZA +l3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="FkhD/N5J"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan --- v2: Add full stop to commit log. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bf13d5c..04daaac 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1416,6 +1416,7 @@ CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m CONFIG_PHY_QCOM_USB_HS_28NM=m CONFIG_PHY_QCOM_USB_SS=m CONFIG_PHY_QCOM_SGMII_ETH=m +CONFIG_PHY_QCOM_M31_USB=m CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y CONFIG_PHY_RCAR_GEN3_PCIE=y CONFIG_PHY_RCAR_GEN3_USB2=y