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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v2-20020a056402184200b0052542a773dasi3525717edy.528.2023.08.14.00.39.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Aug 2023 00:39:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="UZ2/2B9g"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 789843858416 for ; Mon, 14 Aug 2023 07:39:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 789843858416 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691998790; bh=QQUH2utiWsFEHG5ml2YHF78YHDCmh2ua2GRELe2T2Mk=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=UZ2/2B9gWwEgiJMsXdYKBxFCGL3IEfT5VJmhCIZALROmBPiT+FVs5XQtjTpNFGkfD 11xzVZVkcHvHwZIRNNZn/CycI4UF00TdP2oT+O+h93AFWLWOvYhvGKL2OHpKcu9o32 +oV11v8fDu8/hGGytchDJnLFvcdkiGb25BZVZvHw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 0C7133858D39 for ; Mon, 14 Aug 2023 07:39:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0C7133858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10801"; a="362133659" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="362133659" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 00:39:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10801"; a="798729208" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="798729208" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2023 00:39:03 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 1D03E100A81B; Mon, 14 Aug 2023 15:39:03 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFSQRT rounding mode intrinsic API Date: Mon, 14 Aug 2023 15:39:02 +0800 Message-Id: <20230814073902.722885-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774189325146164297 X-GMAIL-MSGID: 1774189325146164297 From: Pan Li This patch would like to support the rounding mode API for the VFSQRT as the below samples. * __riscv_vfsqrt_v_f32m1_rm * __riscv_vfsqrt_v_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class unop_frm): New class for frm. (vfsqrt_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfsqrt_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-sqrt.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 17 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 ++ .../riscv/rvv/base/float-point-sqrt.c | 31 +++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b458560a040..2074dac0f16 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -631,6 +631,21 @@ public: } }; +/* Implements below instructions for frm + - vfsqrt +*/ +template +class unop_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ())); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2415,6 +2430,7 @@ static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj; static CONSTEXPR const unop vfsqrt_obj; +static CONSTEXPR const unop_frm vfsqrt_frm_obj; static CONSTEXPR const float_misc vfrsqrt7_obj; static CONSTEXPR const float_misc vfrec7_obj; static CONSTEXPR const binop vfmin_obj; @@ -2662,6 +2678,7 @@ BASE (vfwmsac_frm) BASE (vfwnmsac) BASE (vfwnmsac_frm) BASE (vfsqrt) +BASE (vfsqrt_frm) BASE (vfrsqrt7) BASE (vfrec7) BASE (vfmin) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 85e8b9a3769..5c91381bd4c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -184,6 +184,7 @@ extern const function_base *const vfwmsac_frm; extern const function_base *const vfwnmsac; extern const function_base *const vfwnmsac_frm; extern const function_base *const vfsqrt; +extern const function_base *const vfsqrt_frm; extern const function_base *const vfrsqrt7; extern const function_base *const vfrec7; extern const function_base *const vfmin; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 7e2a4ab2969..a821aca6a4b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -388,6 +388,8 @@ DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds, f_wwfv_ops) // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) +DEF_RVV_FUNCTION (vfsqrt_frm, alu_frm, full_preds, f_v_ops) + // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c new file mode 100644 index 00000000000..afd1fb2b8f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfsqrt_vv_f32m1_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfsqrt_v_f32m1_rm (op1, 0, vl); +} + +vfloat32m1_t +test_vfsqrt_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfsqrt_v_f32m1_rm_m (mask, op1, 1, vl); +} + +vfloat32m1_t +test_riscv_vfsqrt_vv_f32m1 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfsqrt_v_f32m1 (op1, vl); +} + +vfloat32m1_t +test_vfsqrt_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfsqrt_v_f32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */