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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c8-20020a17090654c800b0098dfb10f3a6si5672444ejp.107.2023.08.12.17.57.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Aug 2023 17:57:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Yo5XlD0c; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D155E3858C33 for ; Sun, 13 Aug 2023 00:57:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D155E3858C33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691888262; bh=8sjAiDcDSYrBkQFtDuB5CeTmde+MHhhVw+vBFZInXC4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Yo5XlD0cFIrWdh+T3H0AG37vSDY1Gcnsc5d+ZwLSFDtDMFJA1V/AbR5KNQBUG/f+G 69h+Up/eoAakvhcuAewhkQ74b+o/MpxIxKHBUPo6D4Jszz2Vf0FeLMarVQ2DMUEaLe cBs2xRGJEe38/RS9udDumj2zrAajIWtjFP++NVNI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 88AFC3858D32 for ; Sun, 13 Aug 2023 00:56:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 88AFC3858D32 X-IronPort-AV: E=McAfee;i="6600,9927,10800"; a="438192525" X-IronPort-AV: E=Sophos;i="6.01,169,1684825200"; d="scan'208";a="438192525" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2023 17:56:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10800"; a="979580750" X-IronPort-AV: E=Sophos;i="6.01,169,1684825200"; d="scan'208";a="979580750" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga006.fm.intel.com with ESMTP; 12 Aug 2023 17:56:51 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 80CEE1007EC5; Sun, 13 Aug 2023 08:56:50 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com Subject: [PATCH v4] Mode-Switching: Fix SET_SRC ICE for create_pre_exit Date: Sun, 13 Aug 2023 08:56:21 +0800 Message-Id: <20230813005621.591927-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807122247.1881775-1-pan2.li@intel.com> References: <20230807122247.1881775-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774073429262094595 X-GMAIL-MSGID: 1774073429262094595 From: Pan Li In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will be only 1 operand when SET_SRC in create_pre_exit. For example as below. (insn 13 9 14 2 (clobber (reg/i:TI 10 a0)) "gcc/testsuite/gcc.dg/pr78148.c":24:1 -1 (expr_list:REG_UNUSED (reg/i:TI 10 a0) (nil))) Unfortunately, SET_SRC requires at least 2 operands and then Segment Fault here. For SH4 part result in Segment Fault, it looks like only valid when the return_copy_pat is load or something like that. Thus, this patch try to fix it by restrict the SET insn for SET_SRC. Signed-off-by: Pan Li gcc/ChangeLog: * mode-switching.cc (create_pre_exit): Add SET insn check. gcc/testsuite/ChangeLog: * gcc.target/riscv/mode-switch-ice-1.c: New test. --- gcc/mode-switching.cc | 1 + .../gcc.target/riscv/mode-switch-ice-1.c | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc index 64ae2bc29c3..f483c831c35 100644 --- a/gcc/mode-switching.cc +++ b/gcc/mode-switching.cc @@ -411,6 +411,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes) conflict with address reloads. */ if (copy_start >= ret_start && copy_start + copy_num <= ret_end + && GET_CODE (return_copy_pat) == SET && OBJECT_P (SET_SRC (return_copy_pat))) forced_late_switch = true; break; diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c new file mode 100644 index 00000000000..1b34a471904 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct A { char e, f; }; + +struct B +{ + int g; + struct A h[4]; +}; + +extern void bar (int, int); + +struct B foo (void) +{ + bar (2, 1); +} + +void baz () +{ + foo (); +}