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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k17-20020a170902c41100b001b6aa82743esi5757833plk.271.2023.08.12.15.45.10; Sat, 12 Aug 2023 15:45:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N2dGHaG0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231202AbjHLUpT (ORCPT + 99 others); Sat, 12 Aug 2023 16:45:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230415AbjHLUpN (ORCPT ); Sat, 12 Aug 2023 16:45:13 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B6AE10F2; Sat, 12 Aug 2023 13:45:16 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37CKiwGw095270; Sat, 12 Aug 2023 15:44:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691873098; bh=KDMPwakXHnBm1lyuJMieItLxASOIXvE4C4DW6HKNztU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N2dGHaG0b7qGs71o83Dcd1oQhPZnCuFkpcq6a2wqH2mPQ92TZAUCqJeqBXJhyAQS+ n2IAGwjqFnvfzm6lqvcqj08fAUfu5pitI2o3zGBXhcUpkBP0NcXEmso2+M2AjQFO3P prCoYumRq3So1Af0lry08atYCRxIqQf/lZRAuSsg= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37CKiwbk127046 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 12 Aug 2023 15:44:58 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 12 Aug 2023 15:44:58 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 12 Aug 2023 15:44:58 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37CKivss067879; Sat, 12 Aug 2023 15:44:58 -0500 From: Achal Verma To: Vignesh Raghavendra , Lorenzo Pieralisi , Krzysztof Wilczy_ski , Rob Herring , Bjorn Helgaas CC: , , , , Achal Verma Subject: [PATCH 1/2] PCI: cadence: Advertise ARI Forwarding Supported Date: Sun, 13 Aug 2023 02:14:54 +0530 Message-ID: <20230812204455.479510-2-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230812204455.479510-1-a-verma1@ti.com> References: <20230812204455.479510-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774065104040852129 X-GMAIL-MSGID: 1774065104040852129 J7 PCIe Root Complex has ARI Forwarding Support (advertised by PCI_EXP_DEVCAP2_ARI bit) which means support for forwarding of TLPs addressed to functions with function number greater than 7 but for some PCIe instances on J7, PCI_EXP_DEVCAP2_ARI bit is cleared which prevents accessing functions with function number > 7. Setting the PCI_EXP_DEVCAP2_ARI explicitly, resolves the issue. Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence-host.c | 7 +++++++ drivers/pci/controller/cadence/pcie-cadence.h | 12 ++++++++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 2c3b3af59271..7e94eb94f29c 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -73,6 +73,7 @@ struct j721e_pcie_data { unsigned int quirk_disable_flr:1; u32 linkdown_irq_regfield; unsigned int byte_access_allowed:1; + unsigned int set_afs_bit:1; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -292,6 +293,7 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = { .quirk_retrain_flag = true, .byte_access_allowed = false, .linkdown_irq_regfield = LINK_DOWN, + .set_afs_bit = true, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { @@ -304,6 +306,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { .quirk_detect_quiet_flag = true, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .set_afs_bit = true, }; static const struct j721e_pcie_data j7200_pcie_ep_data = { @@ -393,6 +396,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) rc = pci_host_bridge_priv(bridge); rc->quirk_retrain_flag = data->quirk_retrain_flag; rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; + rc->set_afs_bit = data->set_afs_bit; cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 5b14f7ee3c79..fc696d94f7a2 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -507,6 +507,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) struct cdns_pcie *pcie; struct resource *res; int ret; + u32 pcie_cap2; bridge = pci_host_bridge_from_priv(rc); if (!bridge) @@ -536,6 +537,12 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) if (rc->quirk_detect_quiet_flag) cdns_pcie_detect_quiet_min_delay_set(&rc->pcie); + if (rc->set_afs_bit) { + pcie_cap2 = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_DEVCAP2); + pcie_cap2 |= PCI_EXP_DEVCAP2_ARI; + cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_DEVCAP2, pcie_cap2); + } + cdns_pcie_host_enable_ptm_response(pcie); ret = cdns_pcie_start_link(pcie); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 190786e47df9..7a5d05f3febc 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -329,6 +329,7 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; unsigned int quirk_retrain_flag:1; unsigned int quirk_detect_quiet_flag:1; + unsigned int set_afs_bit:1; }; /** @@ -457,6 +458,17 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) return cdns_pcie_read_sz(addr, 0x2); } +static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, + u32 reg, u32 value) +{ + writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg) +{ + return readl(pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) From patchwork Sat Aug 12 20:44:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 134954 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1902940vqi; Sat, 12 Aug 2023 14:27:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFAfsCA8atVP+lRfdNzkMzdSF2sqakA+JLes7VA+buNUOyJ2NIZFezdvJy8HtMaaik/a5IH X-Received: by 2002:a17:90b:e8b:b0:263:e133:b9c9 with SMTP id fv11-20020a17090b0e8b00b00263e133b9c9mr3571171pjb.34.1691875653817; Sat, 12 Aug 2023 14:27:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875653; cv=none; d=google.com; s=arc-20160816; b=euBeNCNkAK/GNBGsKmvYrhL8MM69aNwPQnZQv0faLxZel5hInfj6wOhWp6r3Ess/fd dXcOBCunC4/qXjWRXfSpQUuFpB98tyOqbiq0qimUx6TM/E+lkneIg/fRJJa4kgCYG0Vl KxllLV3LC3k7CTPUQnO+vvSl7eTGKoTfxB2LBk09h+selxBp98/JEFxORpcDZUp1Dk9S vrPNZLJDa8UGcKh+DnrV/8rB3F1GfN5SoDNfHRg+B2wwItoF1VPKqCn2AwxHYyMI1hK8 hZD5BLkp1lpBtAGawkT01fbUmvB8poBj+3SP/G+nIpfVGiE9vrCgyL8WRepOM3mN24G6 myOQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q4-20020a17090a1b0400b0026901c2adcasi5440594pjq.132.2023.08.12.14.27.15; Sat, 12 Aug 2023 14:27:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=G6VXDDfa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230393AbjHLUpN (ORCPT + 99 others); Sat, 12 Aug 2023 16:45:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229480AbjHLUpL (ORCPT ); Sat, 12 Aug 2023 16:45:11 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 786FA10F2; Sat, 12 Aug 2023 13:45:14 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37CKj0el089686; Sat, 12 Aug 2023 15:45:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691873100; bh=qs98ZG5d9WEE5HuZu48lVDNnMP0B6h7oimiTl2Sa3j8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G6VXDDfa48ICViV9UhbFOpqnUCubfDhvg56vIBLbeGNZllPAT48PyhuWnRwLERk7Q FCnAQwil+lz9CVFmXBHCWeW+pXowqUDB80QERCvXYQe/seVhfitpKtbbWY6Rqy0Y5V E6RkkFIpYjbQvxD/UosVYflb+6LvtkvUA8c0XdeQ= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37CKj0CC076204 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 12 Aug 2023 15:45:00 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 12 Aug 2023 15:44:59 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 12 Aug 2023 15:44:59 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37CKixqD067906; Sat, 12 Aug 2023 15:44:59 -0500 From: Achal Verma To: Vignesh Raghavendra , Lorenzo Pieralisi , Krzysztof Wilczy_ski , Rob Herring , Bjorn Helgaas CC: , , , , Achal Verma Subject: [PATCH 2/2] PCI: cadence: Clear the ARI Capability Next Function Number of the last function Date: Sun, 13 Aug 2023 02:14:55 +0530 Message-ID: <20230812204455.479510-3-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230812204455.479510-1-a-verma1@ti.com> References: <20230812204455.479510-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060205891152397 X-GMAIL-MSGID: 1774060205891152397 From: Jasko-EXT Wojciech Next Function Number field in ARI Capability Register for last function must be zero by default as per the PCIe specification, indicating there is no next higher number function but that's not happening in our case, so this patch clears the Next Function Number field for last function used. Signed-off-by: Jasko-EXT Wojciech Signed-off-by: Achal Verma Reviewed-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 14 +++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index b8b655d4047e..8742b2f594fd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie *pcie = &ep->pcie; struct device *dev = pcie->dev; int max_epfs = sizeof(epc->function_num_map) * 8; - int ret, value, epf; + int ret, epf, last_fn; + u32 reg, value; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -573,6 +574,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) */ cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. + * Clearing Next Function Number field for the last function used. + */ + last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value = cdns_pcie_readl(pcie, reg); + value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + if (ep->quirk_disable_flr) { for (epf = 0; epf < max_epfs; epf++) { if (!(epc->function_num_map & BIT(epf))) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 7a5d05f3febc..adcab11e62cd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -130,6 +130,12 @@ #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 +/* + * Endpoint PF Registers + */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + /* * Root Port Registers (PCI configuration space for the root port function) */