From patchwork Sat Aug 12 19:58:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134938 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1887263vqi; Sat, 12 Aug 2023 13:38:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIzz2V29T1KjfA0xnmM0ndPrng2s5S5/O/yZLWDDLYihoaFQ82+nq+g0xIV/2Yi/p1hjNJ X-Received: by 2002:a17:902:9341:b0:1bc:5d0:e8e8 with SMTP id g1-20020a170902934100b001bc05d0e8e8mr3745880plp.20.1691872713505; Sat, 12 Aug 2023 13:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691872713; cv=none; d=google.com; s=arc-20160816; b=P3uEtDWmyxDkuktkTiY3lfs5qHxDQI+xIgxuhXlCNstUDqfe6K1EzU1A6oW5l+62Dd RjmKyOtzy+Uq+M/ivk5qCR5dsMWJ+SyBtrplnLPDZdQFFteAkXEZdU0DEYKj46taizwO uQEnUmh4xkIQfSoQPzYwLqeaKQitf6mWU+BTACPUVgUa2D1ONfH4EKaPG5xd0Tw33eG9 9DA5drCOI1AB0cTM6X/VQcIUANxpiampcv4hZcA7A3envof//uw9PbeTABWKt67p2V4C 0xjkIucldtZ09nWYnQI22OGJQYNL7uxAJ/MejecmPUWCPRrbI7XojQwOIfJxAUsO3VpW u6qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=vZfu3hn1QJAjVwqJekBOL9H9dLKGyIEaYNIR6HaO1RM=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=TVbQ/MWOrF8KJinAUS2LMIUIJcyyBzcC8mow0yMcQuT3MbxhvsRZ0WgRqheBDhmBqH 96df3lYpZ9aG8EPvi1EQYp2C8MMfkp4/r8y7Dp6E80nuJU80tftZ+QMJEtngKKMPYogb JiR2QjiDFO27GLvb2NvMc48Zq1lXe0BSBp/qwJkfwDfV8MQB11nm8iMR+PNcOWjl46L7 dBUGEwgkFeE2Eu9Ii8He/slGJB/xumihtVwlM4SbZIcoIW1KcjQgejPuGv7hDiepLLca YpFQhqoXmMITy+8OIn5QU8YYqw1jG8vwlYRHh9H6b4VeC6ZrjEv5GuRN1xl7SdFEoY3A hnDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=24XntUOd; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g2-20020a170902e38200b001bb8704e6f3si5215897ple.278.2023.08.12.13.38.11; Sat, 12 Aug 2023 13:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=24XntUOd; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjHLUAJ (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230119AbjHLUAG (ORCPT ); Sat, 12 Aug 2023 16:00:06 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6F0B270C for ; Sat, 12 Aug 2023 12:59:45 -0700 (PDT) Message-ID: <20230812195727.600549655@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vZfu3hn1QJAjVwqJekBOL9H9dLKGyIEaYNIR6HaO1RM=; b=24XntUOddusKNsOZmHUCaWBvLuTGkAp5p3D3uvdIQaUzM3D99QfyTmTMup1AIXBjqUGMFf UawDG36uAudfPOE/D0g6uA0xkEgpJn7FVPHniRkM+gN9i3g3wRMNJw3qAPxDiQet114hEH ZgTzbul3QutO72+HY3X1IiztBw6TqsjKTsnebdFbuydsaL4a3padt4oYgEy0cq5OMqq1k0 /oo2crioPgIawXv9QRkth55aDoUeO8RvCTufWUAAD7NDPRa7o1hKQE94RMxOsBHi7yVZcq tbORMsdRzyb96qWWyYYxDnw6BisKb1gwXImw0n7GD83Dap3SdAZDK0abkcwr6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vZfu3hn1QJAjVwqJekBOL9H9dLKGyIEaYNIR6HaO1RM=; b=ixS7kBELq974kNgFX6sjcFSbnaOqnTVjhEZEZFwRpb5/+I5o44bmY+8h35RcAz7y9cm4K8 GRYlsY1G7+WTx2Dg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 01/37] x86/mm: Remove unused microcode.h include References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:38 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774057122618191269 X-GMAIL-MSGID: 1774057122618191269 From: Thomas Gleixner No usage for anything in that header. Signed-off-by: Thomas Gleixner --- arch/x86/mm/init.c | 1 - 1 file changed, 1 deletion(-) --- --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -20,7 +20,6 @@ #include #include #include /* for MAX_DMA_PFN */ -#include #include #include #include From patchwork Sat Aug 12 19:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134945 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1889765vqi; Sat, 12 Aug 2023 13:48:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEk7mCJJxlF2msMfzQyihhmOgDVvJaZ1wL05XYJLat367NH7PmC4z6gcCpTooRxWkERbqOz X-Received: by 2002:a05:6a00:b93:b0:687:8dba:4ca8 with SMTP id g19-20020a056a000b9300b006878dba4ca8mr4525925pfj.30.1691873280662; Sat, 12 Aug 2023 13:48:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691873280; cv=none; d=google.com; s=arc-20160816; b=DCSwUmnNtfkx3nTcSE6LZNb6q0rPJtMpLBOBkVAlDBf/sRyVquFgNeEZW/c2Fq3KNf dyJuS7kBkxBdFEp6TIn6pTQ+P1YvZlq4Gcf5+Un20D2Agqc/Ix+FrKsR4vpfyRufZHCw fw/u+dSOE+VzU2/fn/3PzWak7A/swmsmdVGjH7prD3kul7yyNVCEsqhAqbWtAUkF3a4R xJ4rqEqLs2rlwASmLXsE7MO/DplHr1emSyLrtLMUmhin1rWN32pomW26FFyRvpRepJyK 65doVJSSq88nqyarE7MskPKPLgjuqgifFDTxyA8jekx0IZW+YEur75Hx+KxkqBOaygpG UjEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=o4sJeRL5IQ24hTsdSNsR5sgJziqs8oAOJ4qtUOnODjK1UMql/VYPrfw1kMbJXqSBb0 yQte9GEV1HtG8UcNscozElNCJ11IrYB0Hm5TJq/8kDlmYc7r0xcbUmHb5lF1gXYZvpAD 8LO/Ueqs0FACGGU1+BSY4weBYi6zM9GuesIeWtVGtH7apHw/Q+C0gDhxd0sZfvLSspCH uf83Qjs3b9gXAp2qV/KfCwiaZtxLzAW2HS3tMBGUp5Sm3IQFbH7YTSxWTuSIQRM1VyYD enwXDcawluHQVY5DIo0WaX5QwenSa1xRyg1A6lSKfNkYcUwi0hLpLdB25CkNGRhGakUu 378g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=HWheSECg; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=D9YFE1jm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ca26-20020a056a00419a00b006874ec495c5si5477484pfb.173.2023.08.12.13.47.48; Sat, 12 Aug 2023 13:48:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=HWheSECg; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=D9YFE1jm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbjHLUAQ (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjHLUAI (ORCPT ); Sat, 12 Aug 2023 16:00:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8A501998 for ; Sat, 12 Aug 2023 12:59:47 -0700 (PDT) Message-ID: <20230812195727.660453052@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870320; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=HWheSECgs8fHA0pwSALBVWIHDDQWpxZArpuN8fup5l5Qc2d493d7zgXyDpd+pwVJhAtwpR ZOwSCdWdYoOY3uG7mg+FnwFl/bDDO9gu666ujoKGdzlm1aTB20X2ntzZ82YN+0rDOG2hn0 cXFQh9hXAUEz5DJaD0HRzWRhyyiBANA5zW01GzyE2ltpGB5Cn8G9Ay6flDkW9wgsx1F/IZ 2lUe33U6YWPmDLw9Ng97BAtqYpLmnuprwBwwQBCil7tkXpgMipw04RnySDb2Uk6lS9+IMX etqisTUYbGge31Ilnqcek/ry+RH2Jl7ysnSDqaUsTzdudIduG8pt8BegYvT76Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870320; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=D9YFE1jmwB2zsJ9vCq140UTrDSkeNM1bvbcX0su+/Alb1gBbXolfDE/+Lg0404YH2qVqgL J34xbMVZuoaSEUBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 02/37] x86/microcode: Hide the config knob References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:39 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774057717277705316 X-GMAIL-MSGID: 1774057717277705316 In reality CONFIG_MICROCODE is enabled in any reasonable configuration when Intel or AMD support is enabled. Accomodate to reality. Requested-by: Borislav Petkov Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 38 --------------------------------- arch/x86/include/asm/microcode.h | 6 ++--- arch/x86/include/asm/microcode_amd.h | 2 - arch/x86/include/asm/microcode_intel.h | 2 - arch/x86/kernel/cpu/microcode/Makefile | 4 +-- 5 files changed, 8 insertions(+), 44 deletions(-) --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1308,44 +1308,8 @@ config X86_REBOOTFIXUPS Say N otherwise. config MICROCODE - bool "CPU microcode loading support" - default y + def_bool y depends on CPU_SUP_AMD || CPU_SUP_INTEL - help - If you say Y here, you will be able to update the microcode on - Intel and AMD processors. The Intel support is for the IA32 family, - e.g. Pentium Pro, Pentium II, Pentium III, Pentium 4, Xeon etc. The - AMD support is for families 0x10 and later. You will obviously need - the actual microcode binary data itself which is not shipped with - the Linux kernel. - - The preferred method to load microcode from a detached initrd is described - in Documentation/arch/x86/microcode.rst. For that you need to enable - CONFIG_BLK_DEV_INITRD in order for the loader to be able to scan the - initrd for microcode blobs. - - In addition, you can build the microcode into the kernel. For that you - need to add the vendor-supplied microcode to the CONFIG_EXTRA_FIRMWARE - config option. - -config MICROCODE_INTEL - bool "Intel microcode loading support" - depends on CPU_SUP_INTEL && MICROCODE - default MICROCODE - help - This options enables microcode patch loading support for Intel - processors. - - For the current Intel microcode data package go to - and search for - 'Linux Processor Microcode Data File'. - -config MICROCODE_AMD - bool "AMD microcode loading support" - depends on CPU_SUP_AMD && MICROCODE - help - If you select this option, microcode patch loading support for AMD - processors will be enabled. config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -54,16 +54,16 @@ struct ucode_cpu_info { extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern struct microcode_ops * __init init_intel_microcode(void); #else static inline struct microcode_ops * __init init_intel_microcode(void) { return NULL; } -#endif /* CONFIG_MICROCODE_INTEL */ +#endif /* CONFIG_CPU_SUP_INTEL */ -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern struct microcode_ops * __init init_amd_microcode(void); extern void __exit exit_amd_microcode(void); #else --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -43,7 +43,7 @@ struct microcode_amd { #define PATCH_MAX_SIZE (3 * PAGE_SIZE) -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern void load_ucode_amd_early(unsigned int cpuid_1_eax); extern int __init save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -71,7 +71,7 @@ static inline u32 intel_get_microcode_re return rev; } -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern void __init load_ucode_intel_bsp(void); extern void load_ucode_intel_ap(void); extern void show_ucode_info_early(void); --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only microcode-y := core.o obj-$(CONFIG_MICROCODE) += microcode.o -microcode-$(CONFIG_MICROCODE_INTEL) += intel.o -microcode-$(CONFIG_MICROCODE_AMD) += amd.o +microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o +microcode-$(CONFIG_CPU_SUP_AMD) += amd.o From patchwork Sat Aug 12 19:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134973 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1908406vqi; Sat, 12 Aug 2023 14:45:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHhhWlHysaFzLr3+ZlKDUyfp+wCPxHYFhgKSw/FfWdILNrFLW55XTydcrGdF13tkZ8bVEPC X-Received: by 2002:a05:6a20:158e:b0:13e:7d3:61d1 with SMTP id h14-20020a056a20158e00b0013e07d361d1mr8346766pzj.12.1691876724203; Sat, 12 Aug 2023 14:45:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876724; cv=none; d=google.com; s=arc-20160816; b=Mp5h1JbdbALscbTM+tCwPjbF2LVm39K8WWm1BGOP02VkhUH9CitItvSCslq6dAC2pc R86fpNaQULsTVvg2RWVfTdLT9+rEJVC8b/D5IcTS+uO0y0YJU2PFx2Tn3ZHvSmZlDR4F MT5HKm5DyqIU2y7j5fnC4y6fSL03m7OZRPv4x70J7AFUvVEn30UmlDu72bPG1vBuH0Iw 2GpCz0cbXR9LRPxpELBEK42LJay4vYo3lUX9ZtrgnRRbybPkfmsEHm4enH+Pc4KwrxBg ixaeI88AQxUePi5MaUTzKHJRYguYUucSEnI9NTvfZpITDbOfK+TakDp/I8VNzifz+CQn YxoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ggxYi+OZBvt+3ot3vhQxZ5PJuR5IZeB1koCPjiEIzL0=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=VQsPR2j4cqSW/w/YpJpECnd2zhV3d+nM/QOp4C2uyDhUKJOFOaFbIutl+iywQ5jWEK V0/I5iTh0i09tUMyVxQ6ePyxLM3QwImFyrIy9EiEiz5LMEp0M1altspSLG5IEnGaWk6e JQtlUeV2tQ8mopGtolWhMD4stvMBeYxwyuoVVKnlIvz81M4jthshfKhdxvSrQfr4wir5 2EIc8zOjmOkD0r8a80iuFCNx+HXx55GuhbO864vTRBPrM6cyvhHQUTy/ewh+PcxBU7Ex O2j8WxCy8k1hfXmm9XJsWeuOOvtsZdFGFWjE53vH0B+/XnEMJgVIxEC5Td59clC8ckir kQ6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SabdeBly; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 26-20020a63115a000000b00564d9327829si5353100pgr.871.2023.08.12.14.45.11; Sat, 12 Aug 2023 14:45:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SabdeBly; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230281AbjHLUAN (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230150AbjHLUAH (ORCPT ); Sat, 12 Aug 2023 16:00:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9A8F2D5B for ; Sat, 12 Aug 2023 12:59:45 -0700 (PDT) Message-ID: <20230812195727.719202319@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870321; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ggxYi+OZBvt+3ot3vhQxZ5PJuR5IZeB1koCPjiEIzL0=; b=SabdeBlyiFCniJKKuHlwAfi9r84M8G2kZh3SCHGFPWIjDU0CTpM1PzJmZs/Zp+xlXsn56G Q3zm2indR+18Ui6jdT2w+oAJA3Yv9XxZaV3LF7aOAdckUIQC7+ISB2oUDFzrG9+EQ2Zovk QQKH3dQ/1BjwoL/l/8HwE5p8QWRZ3R8oE3J3RjAPIb6ISxO14896uKIh/EQ+tcs/nRFjFN VWlf3cSDFZaPRbb/wbRlDVeq90fmRItApjmgHgxdFin8YAwag4d3KuyK+UZHBQWmvGlaNC 286q3GsqYZLWdsHDftV1Hij5iCUnnjrQ87RZlcLqojECtOtnH+mpnvk1gPN8aA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870321; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ggxYi+OZBvt+3ot3vhQxZ5PJuR5IZeB1koCPjiEIzL0=; b=ya/M02C6qqyLvjgaAHACXIFm/lGyN7D3E+M0iMUto8N1Vc/5j99SIqJhOAIUKDKfoYdDh3 a1oMPgD+H7NERWCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 03/37] x86/microcode/intel: Move microcode functions out of cpu/intel.c References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:41 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774061327631311083 X-GMAIL-MSGID: 1774061327631311083 There is really no point to have that in the CPUID evaluation code. Move it into the intel specific microcode handling along with the datastructures, defines and helpers required by it. The exports need to stay for IFS. Signed-off-by: Thomas Gleixner --- V2: Move the structs, defines and helpers into intel.c --- arch/x86/include/asm/microcode_intel.h | 28 ---- arch/x86/kernel/cpu/intel.c | 174 ---------------------------- arch/x86/kernel/cpu/microcode/intel.c | 202 +++++++++++++++++++++++++++++++++ 3 files changed, 204 insertions(+), 200 deletions(-) --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -23,39 +23,15 @@ struct microcode_intel { unsigned int bits[]; }; -/* microcode format is extended from prescott processors */ -struct extended_signature { - unsigned int sig; - unsigned int pf; - unsigned int cksum; -}; - -struct extended_sigtable { - unsigned int count; - unsigned int cksum; - unsigned int reserved[3]; - struct extended_signature sigs[]; -}; - -#define DEFAULT_UCODE_DATASIZE (2000) -#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) -#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) -#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) -#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) +#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) #define MC_HEADER_TYPE_MICROCODE 1 #define MC_HEADER_TYPE_IFS 2 - -#define get_totalsize(mc) \ - (((struct microcode_intel *)mc)->hdr.datasize ? \ - ((struct microcode_intel *)mc)->hdr.totalsize : \ - DEFAULT_UCODE_TOTALSIZE) +#define DEFAULT_UCODE_DATASIZE (2000) #define get_datasize(mc) \ (((struct microcode_intel *)mc)->hdr.datasize ? \ ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE) -#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) - static inline u32 intel_get_microcode_revision(void) { u32 rev, dummy; --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -184,180 +184,6 @@ static bool bad_spectre_microcode(struct return false; } -int intel_cpu_collect_info(struct ucode_cpu_info *uci) -{ - unsigned int val[2]; - unsigned int family, model; - struct cpu_signature csig = { 0 }; - unsigned int eax, ebx, ecx, edx; - - memset(uci, 0, sizeof(*uci)); - - eax = 0x00000001; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - csig.sig = eax; - - family = x86_family(eax); - model = x86_model(eax); - - if (model >= 5 || family > 6) { - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig.pf = 1 << ((val[1] >> 18) & 7); - } - - csig.rev = intel_get_microcode_revision(); - - uci->cpu_sig = csig; - - return 0; -} -EXPORT_SYMBOL_GPL(intel_cpu_collect_info); - -/* - * Returns 1 if update has been found, 0 otherwise. - */ -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) -{ - struct microcode_header_intel *mc_hdr = mc; - struct extended_sigtable *ext_hdr; - struct extended_signature *ext_sig; - int i; - - if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) - return 1; - - /* Look for ext. headers: */ - if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) - return 0; - - ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; - ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; - - for (i = 0; i < ext_hdr->count; i++) { - if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) - return 1; - ext_sig++; - } - return 0; -} -EXPORT_SYMBOL_GPL(intel_find_matching_signature); - -/** - * intel_microcode_sanity_check() - Sanity check microcode file. - * @mc: Pointer to the microcode file contents. - * @print_err: Display failure reason if true, silent if false. - * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. - * Validate if the microcode header type matches with the type - * specified here. - * - * Validate certain header fields and verify if computed checksum matches - * with the one specified in the header. - * - * Return: 0 if the file passes all the checks, -EINVAL if any of the checks - * fail. - */ -int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) -{ - unsigned long total_size, data_size, ext_table_size; - struct microcode_header_intel *mc_header = mc; - struct extended_sigtable *ext_header = NULL; - u32 sum, orig_sum, ext_sigcount = 0, i; - struct extended_signature *ext_sig; - - total_size = get_totalsize(mc_header); - data_size = get_datasize(mc_header); - - if (data_size + MC_HEADER_SIZE > total_size) { - if (print_err) - pr_err("Error: bad microcode data file size.\n"); - return -EINVAL; - } - - if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { - if (print_err) - pr_err("Error: invalid/unknown microcode update format. Header type %d\n", - mc_header->hdrver); - return -EINVAL; - } - - ext_table_size = total_size - (MC_HEADER_SIZE + data_size); - if (ext_table_size) { - u32 ext_table_sum = 0; - u32 *ext_tablep; - - if (ext_table_size < EXT_HEADER_SIZE || - ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { - if (print_err) - pr_err("Error: truncated extended signature table.\n"); - return -EINVAL; - } - - ext_header = mc + MC_HEADER_SIZE + data_size; - if (ext_table_size != exttable_size(ext_header)) { - if (print_err) - pr_err("Error: extended signature table size mismatch.\n"); - return -EFAULT; - } - - ext_sigcount = ext_header->count; - - /* - * Check extended table checksum: the sum of all dwords that - * comprise a valid table must be 0. - */ - ext_tablep = (u32 *)ext_header; - - i = ext_table_size / sizeof(u32); - while (i--) - ext_table_sum += ext_tablep[i]; - - if (ext_table_sum) { - if (print_err) - pr_warn("Bad extended signature table checksum, aborting.\n"); - return -EINVAL; - } - } - - /* - * Calculate the checksum of update data and header. The checksum of - * valid update data and header including the extended signature table - * must be 0. - */ - orig_sum = 0; - i = (MC_HEADER_SIZE + data_size) / sizeof(u32); - while (i--) - orig_sum += ((u32 *)mc)[i]; - - if (orig_sum) { - if (print_err) - pr_err("Bad microcode data checksum, aborting.\n"); - return -EINVAL; - } - - if (!ext_table_size) - return 0; - - /* - * Check extended signature checksum: 0 => valid. - */ - for (i = 0; i < ext_sigcount; i++) { - ext_sig = (void *)ext_header + EXT_HEADER_SIZE + - EXT_SIGNATURE_SIZE * i; - - sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - - (ext_sig->sig + ext_sig->pf + ext_sig->cksum); - if (sum) { - if (print_err) - pr_err("Bad extended signature checksum, aborting.\n"); - return -EINVAL; - } - } - return 0; -} -EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); - static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -45,6 +45,208 @@ static struct microcode_intel *intel_uco /* last level cache size per core */ static int llc_size_per_core; +/* microcode format is extended from prescott processors */ +struct extended_signature { + unsigned int sig; + unsigned int pf; + unsigned int cksum; +}; + +struct extended_sigtable { + unsigned int count; + unsigned int cksum; + unsigned int reserved[3]; + struct extended_signature sigs[]; +}; + +#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) +#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) +#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) + +static inline unsigned int get_totalsize(struct microcode_header_intel *hdr) +{ + return hdr->datasize ? : DEFAULT_UCODE_TOTALSIZE; +} + +static inline unsigned int exttable_size(struct extended_sigtable *et) +{ + return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; +} + +int intel_cpu_collect_info(struct ucode_cpu_info *uci) +{ + unsigned int val[2]; + unsigned int family, model; + struct cpu_signature csig = { 0 }; + unsigned int eax, ebx, ecx, edx; + + memset(uci, 0, sizeof(*uci)); + + eax = 0x00000001; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + csig.sig = eax; + + family = x86_family(eax); + model = x86_model(eax); + + if (model >= 5 || family > 6) { + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + csig.pf = 1 << ((val[1] >> 18) & 7); + } + + csig.rev = intel_get_microcode_revision(); + + uci->cpu_sig = csig; + + return 0; +} +EXPORT_SYMBOL_GPL(intel_cpu_collect_info); + +/* + * Returns 1 if update has been found, 0 otherwise. + */ +int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) +{ + struct microcode_header_intel *mc_hdr = mc; + struct extended_sigtable *ext_hdr; + struct extended_signature *ext_sig; + int i; + + if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) + return 1; + + /* Look for ext. headers: */ + if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) + return 0; + + ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; + ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; + + for (i = 0; i < ext_hdr->count; i++) { + if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) + return 1; + ext_sig++; + } + return 0; +} +EXPORT_SYMBOL_GPL(intel_find_matching_signature); + +/** + * intel_microcode_sanity_check() - Sanity check microcode file. + * @mc: Pointer to the microcode file contents. + * @print_err: Display failure reason if true, silent if false. + * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. + * Validate if the microcode header type matches with the type + * specified here. + * + * Validate certain header fields and verify if computed checksum matches + * with the one specified in the header. + * + * Return: 0 if the file passes all the checks, -EINVAL if any of the checks + * fail. + */ +int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) +{ + unsigned long total_size, data_size, ext_table_size; + struct microcode_header_intel *mc_header = mc; + struct extended_sigtable *ext_header = NULL; + u32 sum, orig_sum, ext_sigcount = 0, i; + struct extended_signature *ext_sig; + + total_size = get_totalsize(mc_header); + data_size = get_datasize(mc_header); + + if (data_size + MC_HEADER_SIZE > total_size) { + if (print_err) + pr_err("Error: bad microcode data file size.\n"); + return -EINVAL; + } + + if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { + if (print_err) + pr_err("Error: invalid/unknown microcode update format. Header type %d\n", + mc_header->hdrver); + return -EINVAL; + } + + ext_table_size = total_size - (MC_HEADER_SIZE + data_size); + if (ext_table_size) { + u32 ext_table_sum = 0; + u32 *ext_tablep; + + if (ext_table_size < EXT_HEADER_SIZE || + ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { + if (print_err) + pr_err("Error: truncated extended signature table.\n"); + return -EINVAL; + } + + ext_header = mc + MC_HEADER_SIZE + data_size; + if (ext_table_size != exttable_size(ext_header)) { + if (print_err) + pr_err("Error: extended signature table size mismatch.\n"); + return -EFAULT; + } + + ext_sigcount = ext_header->count; + + /* + * Check extended table checksum: the sum of all dwords that + * comprise a valid table must be 0. + */ + ext_tablep = (u32 *)ext_header; + + i = ext_table_size / sizeof(u32); + while (i--) + ext_table_sum += ext_tablep[i]; + + if (ext_table_sum) { + if (print_err) + pr_warn("Bad extended signature table checksum, aborting.\n"); + return -EINVAL; + } + } + + /* + * Calculate the checksum of update data and header. The checksum of + * valid update data and header including the extended signature table + * must be 0. + */ + orig_sum = 0; + i = (MC_HEADER_SIZE + data_size) / sizeof(u32); + while (i--) + orig_sum += ((u32 *)mc)[i]; + + if (orig_sum) { + if (print_err) + pr_err("Bad microcode data checksum, aborting.\n"); + return -EINVAL; + } + + if (!ext_table_size) + return 0; + + /* + * Check extended signature checksum: 0 => valid. + */ + for (i = 0; i < ext_sigcount; i++) { + ext_sig = (void *)ext_header + EXT_HEADER_SIZE + + EXT_SIGNATURE_SIZE * i; + + sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - + (ext_sig->sig + ext_sig->pf + ext_sig->cksum); + if (sum) { + if (print_err) + pr_err("Bad extended signature checksum, aborting.\n"); + return -EINVAL; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); + /* * Returns 1 if update has been found, 0 otherwise. */ From patchwork Sat Aug 12 19:58:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134934 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1880433vqi; Sat, 12 Aug 2023 13:16:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+EAW97XjKqkks2ZG8n02UwxYjJ3XbWU2bQpQ1djCYLyZi/GUcHmqnrEKuU2nNdMD2xvib X-Received: by 2002:a17:907:6095:b0:974:fb94:8067 with SMTP id ht21-20020a170907609500b00974fb948067mr11433237ejc.23.1691871378733; Sat, 12 Aug 2023 13:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691871378; cv=none; d=google.com; s=arc-20160816; b=I83T9e25VNfKoFlw0KSQxRi92JLgiorigzUBQB4AoUiut/VLQUs6JqwPyJl3ecPHrD khtblDwR8S0wXnz8iVHFREo0Vd2cMMeqXhsTzZACv15pMg35BdlVwAGCLWJwV41yhs8v fv4pm685CpM8W7i0nQc5F+2rOH/rcM5zcDAjTwuSx5fbHrnq+i4TtCVUnBU+x6i5hox4 i7/r+jlt4CyIfqnE9/bKRd4iX0HIupY3qQ50ekXJ/7T0zz4czVf2o9iggRJhOTzX4pfe YCRn7GW2nfhIlx9hJGbLbqSuYYkHzuhHqUj9iBrwRO+vUb0ioahFkQoeKdZY6KoIdqsT rTig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=xWepluyiaqfIY/tanS5Ndfk5WwU6Id4g+TqNpVND6ps=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=xZBFnwubfB5caQR9I9yTmb8acTkFoYFktXylnN8mMMItYvDFqvgIVEtb59w/nHtoeQ CbMYiABipMtbw71WxwId/JmJWrRI9AwY2KZ7s2aNB8L5pH0CdoxJpfFX1bBqwSPVzGIj XhCOHv0N1OCQ6TyqHClPiusiiGYmY3XtinUq6vOjQOTrS6nK0K07TrsVDm2v2OBXOASl C3naJVUyU+Fi/g03E8aAdBIbActZqFaOYPNgmn2Ccgiu+WCnnVEhciiZnKNB56ewSb+x tW1J2hrGb/AeXZxLQeTmTDfI7x/3hSdyKR5+22YfjVjjZkAQrh60CuespBv2EpzcyrRW rsxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Aahc0HEM; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sb16-20020a170906edd000b00997eac101casi5344705ejb.509.2023.08.12.13.15.55; Sat, 12 Aug 2023 13:16:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Aahc0HEM; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230333AbjHLUAU (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230104AbjHLUAI (ORCPT ); Sat, 12 Aug 2023 16:00:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3186C1BE9 for ; Sat, 12 Aug 2023 12:59:48 -0700 (PDT) Message-ID: <20230812195727.776541545@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870323; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xWepluyiaqfIY/tanS5Ndfk5WwU6Id4g+TqNpVND6ps=; b=Aahc0HEMSZ+5wLZo9GpKM8Iw4g5bzUg1Lb7HiA2tnLTc1U37XqmuTlV4JbL6p8AZ/xzzHf X6tS8KiVekQe//GoZXua1GDA9vwYMo4dz0kX29MNJ4jo44W2+9fuq/LqGHDZVFpatCzfs/ znT5yETlIX2+A0e3oHqgSfrr8ciCi9PRRoZD6fSe8Nz0OUDwN1zuv1VK6NkQbirTolttkQ G1FMO6zCwDFI3GB64z2F5T8gw+a5aQw8LXdgTXrkwWsFc6ozmqaIYUNW3ld7VxcPErrfCr rlDhjix+9FDzpoC9CcnmQGXSBz2q1F4VDJ6QLzJqxN1bPhmxTd6QTB9AX8HhJg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870323; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xWepluyiaqfIY/tanS5Ndfk5WwU6Id4g+TqNpVND6ps=; b=kk93GCk+ApTsihgq5rS36mIo0KTVteSUPOhgvsMH7i1lXzTVTWUFhORdr702Dv7wOqYg5b tVdknO1+vkSy2uBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 04/37] x86/microcode: Include vendor headers into microcode.h References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:42 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774055722764165550 X-GMAIL-MSGID: 1774055722764165550 From: Ashok Raj Currently vendor specific headers are included explicitly when used in common code. Instead, include the vendor specific headers in microcode.h, and include that in all usages. No functional change. Suggested-by: Boris Petkov Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 5 ++++- arch/x86/include/asm/microcode_amd.h | 2 -- arch/x86/include/asm/microcode_intel.h | 2 -- arch/x86/kernel/cpu/common.c | 1 - arch/x86/kernel/cpu/intel.c | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 1 - arch/x86/kernel/cpu/microcode/core.c | 2 -- arch/x86/kernel/cpu/microcode/intel.c | 2 +- drivers/platform/x86/intel/ifs/load.c | 2 +- 9 files changed, 7 insertions(+), 12 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -2,10 +2,13 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H -#include #include #include +#include +#include +#include + struct ucode_patch { struct list_head plist; void *data; /* Intel uses only this one */ --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -2,8 +2,6 @@ #ifndef _ASM_X86_MICROCODE_AMD_H #define _ASM_X86_MICROCODE_AMD_H -#include - #define UCODE_MAGIC 0x00414d44 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 #define UCODE_UCODE_TYPE 0x00000001 --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -2,8 +2,6 @@ #ifndef _ASM_X86_MICROCODE_INTEL_H #define _ASM_X86_MICROCODE_INTEL_H -#include - struct microcode_header_intel { unsigned int hdrver; unsigned int rev; --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -59,7 +59,6 @@ #include #include #include -#include #include #include #include --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -31,9 +31,7 @@ #include #include -#include #include -#include #include #include #include --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -30,9 +30,9 @@ #include #include -#include #include #include +#include #include #include #include --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include "ifs.h" From patchwork Sat Aug 12 19:58:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134929 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1877613vqi; Sat, 12 Aug 2023 13:07:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEV+0y5T/xiPor9T2DGfFud5WvYdzwU0FsiwVXBfJmDMyHL9K/5rjq+KmDIkkfFcdukU1Bw X-Received: by 2002:a05:6a20:394a:b0:13f:3d25:d83 with SMTP id r10-20020a056a20394a00b0013f3d250d83mr5602075pzg.19.1691870859785; Sat, 12 Aug 2023 13:07:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691870859; cv=none; d=google.com; s=arc-20160816; b=H9gklDNigPAeUws49dgVlcBntK7fTP6neuWZyLt13Kj/5V4blyxbUZ/ARmVUfVbLkb mc4ISDN3wenZXg35If10yTPdD0LQp1IFxmxW77MvSAUus3dROAD5qLxSVcHpXDO8ud1w bPdPamEBcKNRqCXXGwKE4DrBENfBEV1k1a+pyr1oxstHZz3tqqk/8n54mWssOGvBD9TM 6ZYOoRBQifSTd+7gizyB+KzuTJQU+ne3WCI519siW0XkLZ3M1nNzJiYeKlo25pj3AZaL 2vAhTlT36VXY5itNmCW9M6gthz90gEGjjj0zWu2XILQnYp2//LB+yS9LObjLhq3LrLnt ZREA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=0JPnaj3cEEDg9kfAdYzRsElPoyj/8+m1dAg/elVKOy0=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=SLSvMiWpV5auw5yAPaKKqmxhNVLw8wjob86eOb5OfBSZjA4f83Y8iGM3hDrWmj64zt fWkFWKjzSKxD96/SqeZYJlzzbOINa2RC1ZDlQ2hIQWPq1FwYllGeXq39GK4DTUVWm3xA /EilIJOjT7VKj/WUab5O8wHXE5FYAjhXxoVppWl93FJbGFS7P6DskR4TuPxiOMzV8PMZ fUv6LOGKyt3CtJeOuB/sxbPV6qYKUuzxVlhGKS5Xaeymsy6+U7r6Rcsi3BH2VwyASHUw ZDMnZNEZ3HouqWHj2R1XuXKRPHEBo+RSuNQ0x9440wlQYfsxYzguRyqMbAelq3lFLbTE n5Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Cpy7aC46; dkim=neutral (no key) header.i=@linutronix.de header.b=tUiD6WHE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k70-20020a638449000000b0053ee9b21820si5305362pgd.72.2023.08.12.13.07.26; Sat, 12 Aug 2023 13:07:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Cpy7aC46; dkim=neutral (no key) header.i=@linutronix.de header.b=tUiD6WHE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjHLUAm (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbjHLUAh (ORCPT ); Sat, 12 Aug 2023 16:00:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A067D19B1 for ; Sat, 12 Aug 2023 13:00:12 -0700 (PDT) Message-ID: <20230812195727.834943153@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870324; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0JPnaj3cEEDg9kfAdYzRsElPoyj/8+m1dAg/elVKOy0=; b=Cpy7aC46miOVTHIsx8AMnGaz4vl9e31PYlTHNUwmUrtp1PL8lAMkPR/xbqeBIlqVH3gyq4 hBfcA96ShVOwRls8eNNGZq9YGHGkCEvsZ4oGkWspXmQBXrhpyaK6eBi/maHZfI73OgSGgp xRO/gole9NdyF3azRYIz63rP4CURwFPhvSYzybuVazmyq1vGPq9jBT6EX4wEPSDcFJvsT7 YePJkwu2RZnPI12/ZAHSxfZBxlJF35vOHKUgUes/4I//FmbmfC6jchc24tnGBVf7dBVJ3N 8BSmfJ1ss7UNiJGg6qglJ3p0YGJH8DVnLBUCmxjDa3BwndKGniMAVPh5VtG7SQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870324; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0JPnaj3cEEDg9kfAdYzRsElPoyj/8+m1dAg/elVKOy0=; b=tUiD6WHEtqk3fwz0Ew5KFRxAVreg9Q8aa84y+XILH30l9uYgqOHKCxaTO9CE5OXQdiwjYX 8RkxvSVw5NpSBfAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 05/37] x86/microcode: Make reload_early_microcode() static References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:44 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774055178407350415 X-GMAIL-MSGID: 1774055178407350415 From: Thomas Gleixner fe055896c040 ("x86/microcode: Merge the early microcode loader") left this needlessly public. Git archaeology provided by Borislav. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 2 -- arch/x86/kernel/cpu/microcode/core.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -128,13 +128,11 @@ static inline unsigned int x86_cpuid_fam #ifdef CONFIG_MICROCODE extern void __init load_ucode_bsp(void); extern void load_ucode_ap(void); -void reload_early_microcode(unsigned int cpu); extern bool initrd_gone; void microcode_bsp_resume(void); #else static inline void __init load_ucode_bsp(void) { } static inline void load_ucode_ap(void) { } -static inline void reload_early_microcode(unsigned int cpu) { } static inline void microcode_bsp_resume(void) { } #endif --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -293,7 +293,7 @@ struct cpio_data find_microcode_in_initr #endif } -void reload_early_microcode(unsigned int cpu) +static void reload_early_microcode(unsigned int cpu) { int vendor, family; From patchwork Sat Aug 12 19:58:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134974 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1908991vqi; Sat, 12 Aug 2023 14:47:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHftNDqbrC9uqA7y6Ls+iTu0QjHGc+OEQ7O3jWrSmDZzo6lWQT2YsslGPPNr4O6h5M0Vd4x X-Received: by 2002:a05:6a00:1a10:b0:666:b254:1c9c with SMTP id g16-20020a056a001a1000b00666b2541c9cmr4913599pfv.27.1691876834110; Sat, 12 Aug 2023 14:47:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876834; cv=none; d=google.com; s=arc-20160816; b=zxf30Z7lXkzezHm6sB443VhRL+m9/YqyAp7JjkBjbLP4kZUpWcj9KEp3nedhf2SCxj +9gIyOeFVu028L+8vwwloeaQPJ8dqZWi/dh5ce0XXzfjCg2yotn9x8YahvP2izTuGX/l OsMNoZnpJmEY3zNyB441WxeVLcQOeI3UVE4XMzoUmb//O8pvWKmUR04TV11GhEIOvHO+ xpCj6nEPPTB1Oxu08t7lBExm0oFiCON3MzZf986gY3IirlN2cwPJOkWNq2HiVbDESkB8 2KBHi+YVyRigrECFP16Xo6qavcvK0ADKXBC0YVfgnBwRYX5t/E3i3yX+4PXbY4ZCKZcW FGkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=HkbGnsalnjpIVBAgAAwk1+ueDGPGU5QUbDMtasgxkkc=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=uOOMX1WgPVVaGdW3XsuOvjJQzqmsTHn4Tht614i7xgRHcOq6tcmZSK15M5k/VzRS6V zl4TZRhtLB9zIOoKB5CMqEUYCcB8wLOZ6OkEK1rDvKRtZfcdaiZtR3kbvnAOa6QWwSFh 2JxxEKoSnQ0mM/CvWPhskPSuAmN32BGP0y9sWuEF4iqrq81N5Z81rId61b4EU5ik0YQk S9VCDjy2V7993x5uj9VwscKQtbinFOPsloeOQoOc8q8C4/qAFDoenqIjVa1TT8K2qtdf ZkBhod0gWLLMRdrV8TSjPbmmX52UuvcGOComtpY1UyKog/uWlqgwNZHdlmCgyKShm8XP ezqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3Wrbsk+v; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="R/VegE7E"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n50-20020a056a000d7200b006785d3c33b6si5380814pfv.285.2023.08.12.14.47.00; Sat, 12 Aug 2023 14:47:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3Wrbsk+v; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="R/VegE7E"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbjHLUAj (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjHLUAh (ORCPT ); Sat, 12 Aug 2023 16:00:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 189892694 for ; Sat, 12 Aug 2023 13:00:12 -0700 (PDT) Message-ID: <20230812195727.894165745@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870326; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HkbGnsalnjpIVBAgAAwk1+ueDGPGU5QUbDMtasgxkkc=; b=3Wrbsk+vFhGxK+LHZPNwp3JtpGi4E+9ETLFpA1iCl8uy2i8oqjyW6//ubHKeOINGVCog/+ 2/jXUKJF8+o2jep/tiZZ+98pdnjx/3OkpsdkXgxr8Rlw/x2S0aUb+McOiaEFWyf/HOqrgC Bkqt9txXusOHpYJEJ+rm3j5BWbgU/QyPohX2UiHn4rZCl1ux6F0MQy5gvokQju4y84LMEh 9kgqm0cvfxu3vT89AugYpsEmmHQJ+n2dA+FyV3P/lxniuZGSZqqYlvJBpuYF1PsWLLED+W AQXqouHDOqE3/sNxiq6TduRLcSTZZU83liNh2DeVXVPLXJwlO5jwc999DHdfjw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870326; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HkbGnsalnjpIVBAgAAwk1+ueDGPGU5QUbDMtasgxkkc=; b=R/VegE7EeRx1Vs4DStGliN0XCw4RTXbqLTxzErhqd2ace1KA8m+VztHHHquEgGYQymDEpL mBE6E7d+Ghy+a+Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 06/37] x86/microcode/intel: Rename get_datasize() since its used externally References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:45 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774061443204841997 X-GMAIL-MSGID: 1774061443204841997 From: Ashok Raj Rename get_datasize() to intel_microcode_get_datasize() and make it an inline. [ tglx: Make the argument typed and fix up the IFS code ] Suggested-by: Boris Petkov Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- V2: Make the argument typed --- arch/x86/include/asm/microcode_intel.h | 7 ++++--- arch/x86/kernel/cpu/microcode/intel.c | 8 ++++---- drivers/platform/x86/intel/ifs/load.c | 5 +++-- 3 files changed, 11 insertions(+), 9 deletions(-) --- --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -26,9 +26,10 @@ struct microcode_intel { #define MC_HEADER_TYPE_IFS 2 #define DEFAULT_UCODE_DATASIZE (2000) -#define get_datasize(mc) \ - (((struct microcode_intel *)mc)->hdr.datasize ? \ - ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE) +static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) +{ + return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; +} static inline u32 intel_get_microcode_revision(void) { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -118,10 +118,10 @@ int intel_find_matching_signature(void * return 1; /* Look for ext. headers: */ - if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) + if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) return 0; - ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; + ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { @@ -156,7 +156,7 @@ int intel_microcode_sanity_check(void *m struct extended_signature *ext_sig; total_size = get_totalsize(mc_header); - data_size = get_datasize(mc_header); + data_size = intel_microcode_get_datasize(mc_header); if (data_size + MC_HEADER_SIZE > total_size) { if (print_err) @@ -438,7 +438,7 @@ static void show_saved_mc(void) date = mc_saved_header->date; total_size = get_totalsize(mc_saved_header); - data_size = get_datasize(mc_saved_header); + data_size = intel_microcode_get_datasize(mc_saved_header); pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", i++, sig, pf, rev, total_size, --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -56,12 +56,13 @@ struct metadata_header { static struct metadata_header *find_meta_data(void *ucode, unsigned int meta_type) { + struct microcode_header_intel *hdr = &((struct microcode_intel *)ucode)->hdr; struct metadata_header *meta_header; unsigned long data_size, total_meta; unsigned long meta_size = 0; - data_size = get_datasize(ucode); - total_meta = ((struct microcode_intel *)ucode)->hdr.metasize; + data_size = intel_microcode_get_datasize(hdr); + total_meta = hdr->metasize; if (!total_meta) return NULL; From patchwork Sat Aug 12 19:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134933 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1880403vqi; Sat, 12 Aug 2023 13:16:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHBfWtlTrQsSSgMsNmtDTDzuU/0f/RFV1j41EvOJWDmtm8t3lvIimGygOyE650AQbx/kqji X-Received: by 2002:a17:907:7858:b0:99b:ed8f:551d with SMTP id lb24-20020a170907785800b0099bed8f551dmr4547989ejc.55.1691871372971; Sat, 12 Aug 2023 13:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691871372; cv=none; d=google.com; s=arc-20160816; b=D7qEGsK+aFahl/nO0AyAFeD0BRRwZEJmA/2BpWy79oMpa7H4WBJEF4L9OF79UKLJXR hEbDd6bdcJZS5uvymDGYJLKFaESMUBcWpbcqc+U9fNPCAVHFcP/OGARNDsfrjhTin59Y LM18/MAA/EY+sr/2gQmqHH6JkLh3F7RGHuMJM5MYTXzXz9y9snYQ95WRSxeP41fxGhZ5 rDgZvclT+nl+L74CjZayzyImp+M8MA0Yk0CaRZrjCRr7XT8Z7mPAxUzkkvyJBeanM4Dr VTTa+WZAkNLlk9DAGPGRaTCovmGz+phrDuC0PPDlal/+XkVGNl1flPvGw7NPxyMHVMXG mrUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=yYdvJbFBJMtBe7EkUJVaLHYZDga0nEQHMFXoGEBX1ko=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=J4pkeFWjJmf1IFu11c1NlIMBlbElHU3Kh0oZjMscjxDixDaeL4+kOoLvC+BBAVmlBC LZ9bgH6sFhYT7cUmv7ALKSe31mMhGgIIeCdAmyEeKKOM9faswgv0VG+jphIaSgRjOKRc FdRZ+rJLBSMuD+f2P0tC/ez7XQF1XsgHIjFRqxIYs9a4lWp+6bK8YKnE0JCkwj79ojOP 6/4eumbGf5gDt+suuq/MK1rbDM10utRNBiYFXQ1GzIbr49XWwZjKYVbQ0BYIPC/qmFBw ZGMxgGfXOkp5nROIoOp4zNLNLDMbRRs3le6gemzmhXGXv7g+kkl5bnPNCURcgviTjgM3 ya1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ynVBnrCv; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j17-20020a170906051100b00991f1e4b044si4979242eja.336.2023.08.12.13.15.49; Sat, 12 Aug 2023 13:16:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ynVBnrCv; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230395AbjHLUBK (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230291AbjHLUA5 (ORCPT ); Sat, 12 Aug 2023 16:00:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D322684 for ; Sat, 12 Aug 2023 13:00:43 -0700 (PDT) Message-ID: <20230812195727.952876381@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870327; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yYdvJbFBJMtBe7EkUJVaLHYZDga0nEQHMFXoGEBX1ko=; b=ynVBnrCvfBZWyEG466/VVakbBB0NkDkQeKQAtthUK0njPewNOcu1vRMi6f8yVvKkiEXQZ6 7rtFYgTPc6F3iNqPHBPV/8X3urdeyqL09QQVZ/oJhRWH2218/y//uPMHa5PM8j7CfCmoOG tF7daufw93Njz7pesZO+bppBguOtnUWgccyZFM2DkiA0SG85kHiCoSmnVWh2/vND88KdzB t9IjxH0WnJJQwrrKaXsq/S3aMY8/ticmHYnXjyMIO7gDw8lWxOh4Xa+dBSK4oM8TdTyApY qLAvPcnFD+h22kdsky4FJeX+hJTirSly5eT6Jt8KjSwwojS/ibaQe/LF057NPQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870327; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yYdvJbFBJMtBe7EkUJVaLHYZDga0nEQHMFXoGEBX1ko=; b=IA2a7hdG13nxx/CSPqwT4E6QRQnT+uLMDYxiVVqYBKIqGMWkaPHBZFqrcNmtJEentNww3g PF33LswfGqBL8fAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 07/37] x86/microcode: Move core specific defines to local header References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:47 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774055716632804884 X-GMAIL-MSGID: 1774055716632804884 From: Thomas Gleixner There is no reason to expose all of this globally. Move everything which is not required outside of the microcode specific code to local header files and into the respective source files. No functional change. Signed-off-by: Thomas Gleixner --- V2: Move AMD specific structs and defines into the AMD code. --- arch/x86/include/asm/microcode.h | 155 +++++++++---------------------- arch/x86/include/asm/microcode_amd.h | 54 ---------- arch/x86/include/asm/microcode_intel.h | 63 ------------ arch/x86/kernel/cpu/microcode/amd.c | 41 ++++++++ arch/x86/kernel/cpu/microcode/core.c | 3 arch/x86/kernel/cpu/microcode/intel.c | 3 arch/x86/kernel/cpu/microcode/internal.h | 131 ++++++++++++++++++++++++++ 7 files changed, 223 insertions(+), 227 deletions(-) --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -2,138 +2,77 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H -#include -#include - -#include -#include -#include - -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct cpu_signature { unsigned int sig; unsigned int pf; unsigned int rev; }; -struct device; - -enum ucode_state { - UCODE_OK = 0, - UCODE_NEW, - UCODE_UPDATED, - UCODE_NFOUND, - UCODE_ERROR, +struct ucode_cpu_info { + struct cpu_signature cpu_sig; + void *mc; }; -struct microcode_ops { - enum ucode_state (*request_microcode_fw) (int cpu, struct device *); - - void (*microcode_fini_cpu) (int cpu); +#ifdef CONFIG_MICROCODE +void load_ucode_bsp(void); +void load_ucode_ap(void); +void microcode_bsp_resume(void); +#else +static inline void load_ucode_bsp(void) { } +static inline void load_ucode_ap(void) { } +static inline void microcode_bsp_resume(void) { } +#endif - /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. - * See also the "Synchronization" section in microcode_core.c. - */ - enum ucode_state (*apply_microcode) (int cpu); - int (*collect_cpu_info) (int cpu, struct cpu_signature *csig); +#ifdef CONFIG_CPU_SUP_INTEL +/* Intel specific microcode defines. Public for IFS */ +struct microcode_header_intel { + unsigned int hdrver; + unsigned int rev; + unsigned int date; + unsigned int sig; + unsigned int cksum; + unsigned int ldrver; + unsigned int pf; + unsigned int datasize; + unsigned int totalsize; + unsigned int metasize; + unsigned int reserved[2]; }; -struct ucode_cpu_info { - struct cpu_signature cpu_sig; - void *mc; +struct microcode_intel { + struct microcode_header_intel hdr; + unsigned int bits[]; }; -extern struct ucode_cpu_info ucode_cpu_info[]; -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); -#ifdef CONFIG_CPU_SUP_INTEL -extern struct microcode_ops * __init init_intel_microcode(void); -#else -static inline struct microcode_ops * __init init_intel_microcode(void) -{ - return NULL; -} -#endif /* CONFIG_CPU_SUP_INTEL */ +#define DEFAULT_UCODE_DATASIZE (2000) +#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) +#define MC_HEADER_TYPE_MICROCODE 1 +#define MC_HEADER_TYPE_IFS 2 -#ifdef CONFIG_CPU_SUP_AMD -extern struct microcode_ops * __init init_amd_microcode(void); -extern void __exit exit_amd_microcode(void); -#else -static inline struct microcode_ops * __init init_amd_microcode(void) +static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) { - return NULL; + return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; } -static inline void __exit exit_amd_microcode(void) {} -#endif - -#define MAX_UCODE_COUNT 128 -#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) -#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') -#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') -#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') -#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') -#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') -#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') - -#define CPUID_IS(a, b, c, ebx, ecx, edx) \ - (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c)))) - -/* - * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. - * x86_cpuid_vendor() gets vendor id for BSP. - * - * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify - * coding, we still use x86_cpuid_vendor() to get vendor id for AP. - * - * x86_cpuid_vendor() gets vendor information directly from CPUID. - */ -static inline int x86_cpuid_vendor(void) +static inline u32 intel_get_microcode_revision(void) { - u32 eax = 0x00000000; - u32 ebx, ecx = 0, edx; + u32 rev, dummy; - native_cpuid(&eax, &ebx, &ecx, &edx); + native_wrmsrl(MSR_IA32_UCODE_REV, 0); - if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) - return X86_VENDOR_INTEL; + /* As documented in the SDM: Do a CPUID 1 here */ + native_cpuid_eax(1); - if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) - return X86_VENDOR_AMD; + /* get the current revision from MSR 0x8B */ + native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); - return X86_VENDOR_UNKNOWN; + return rev; } -static inline unsigned int x86_cpuid_family(void) -{ - u32 eax = 0x00000001; - u32 ebx, ecx = 0, edx; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - return x86_family(eax); -} +void show_ucode_info_early(void); -#ifdef CONFIG_MICROCODE -extern void __init load_ucode_bsp(void); -extern void load_ucode_ap(void); -extern bool initrd_gone; -void microcode_bsp_resume(void); -#else -static inline void __init load_ucode_bsp(void) { } -static inline void load_ucode_ap(void) { } -static inline void microcode_bsp_resume(void) { } -#endif +#else /* CONFIG_CPU_SUP_INTEL */ +static inline void show_ucode_info_early(void) { } +#endif /* !CONFIG_CPU_SUP_INTEL */ #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/include/asm/microcode_amd.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_MICROCODE_AMD_H -#define _ASM_X86_MICROCODE_AMD_H - -#define UCODE_MAGIC 0x00414d44 -#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 -#define UCODE_UCODE_TYPE 0x00000001 - -#define SECTION_HDR_SIZE 8 -#define CONTAINER_HDR_SZ 12 - -struct equiv_cpu_entry { - u32 installed_cpu; - u32 fixed_errata_mask; - u32 fixed_errata_compare; - u16 equiv_cpu; - u16 res; -} __attribute__((packed)); - -struct microcode_header_amd { - u32 data_code; - u32 patch_id; - u16 mc_patch_data_id; - u8 mc_patch_data_len; - u8 init_flag; - u32 mc_patch_data_checksum; - u32 nb_dev_id; - u32 sb_dev_id; - u16 processor_rev_id; - u8 nb_rev_id; - u8 sb_rev_id; - u8 bios_api_rev; - u8 reserved1[3]; - u32 match_reg[8]; -} __attribute__((packed)); - -struct microcode_amd { - struct microcode_header_amd hdr; - unsigned int mpb[]; -}; - -#define PATCH_MAX_SIZE (3 * PAGE_SIZE) - -#ifdef CONFIG_CPU_SUP_AMD -extern void load_ucode_amd_early(unsigned int cpuid_1_eax); -extern int __init save_microcode_in_initrd_amd(unsigned int family); -void reload_ucode_amd(unsigned int cpu); -#else -static inline void load_ucode_amd_early(unsigned int cpuid_1_eax) {} -static inline int __init -save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } -static inline void reload_ucode_amd(unsigned int cpu) {} -#endif -#endif /* _ASM_X86_MICROCODE_AMD_H */ --- a/arch/x86/include/asm/microcode_intel.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_MICROCODE_INTEL_H -#define _ASM_X86_MICROCODE_INTEL_H - -struct microcode_header_intel { - unsigned int hdrver; - unsigned int rev; - unsigned int date; - unsigned int sig; - unsigned int cksum; - unsigned int ldrver; - unsigned int pf; - unsigned int datasize; - unsigned int totalsize; - unsigned int metasize; - unsigned int reserved[2]; -}; - -struct microcode_intel { - struct microcode_header_intel hdr; - unsigned int bits[]; -}; - -#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) -#define MC_HEADER_TYPE_MICROCODE 1 -#define MC_HEADER_TYPE_IFS 2 -#define DEFAULT_UCODE_DATASIZE (2000) - -static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) -{ - return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; -} - -static inline u32 intel_get_microcode_revision(void) -{ - u32 rev, dummy; - - native_wrmsrl(MSR_IA32_UCODE_REV, 0); - - /* As documented in the SDM: Do a CPUID 1 here */ - native_cpuid_eax(1); - - /* get the current revision from MSR 0x8B */ - native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); - - return rev; -} - -#ifdef CONFIG_CPU_SUP_INTEL -extern void __init load_ucode_intel_bsp(void); -extern void load_ucode_intel_ap(void); -extern void show_ucode_info_early(void); -extern int __init save_microcode_in_initrd_intel(void); -void reload_ucode_intel(void); -#else -static inline __init void load_ucode_intel_bsp(void) {} -static inline void load_ucode_intel_ap(void) {} -static inline void show_ucode_info_early(void) {} -static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; } -static inline void reload_ucode_intel(void) {} -#endif - -#endif /* _ASM_X86_MICROCODE_INTEL_H */ --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -35,6 +35,47 @@ #include #include +#include "internal.h" + +#define UCODE_MAGIC 0x00414d44 +#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 +#define UCODE_UCODE_TYPE 0x00000001 + +#define SECTION_HDR_SIZE 8 +#define CONTAINER_HDR_SZ 12 + +struct equiv_cpu_entry { + u32 installed_cpu; + u32 fixed_errata_mask; + u32 fixed_errata_compare; + u16 equiv_cpu; + u16 res; +} __packed; + +struct microcode_header_amd { + u32 data_code; + u32 patch_id; + u16 mc_patch_data_id; + u8 mc_patch_data_len; + u8 init_flag; + u32 mc_patch_data_checksum; + u32 nb_dev_id; + u32 sb_dev_id; + u16 processor_rev_id; + u8 nb_rev_id; + u8 sb_rev_id; + u8 bios_api_rev; + u8 reserved1[3]; + u32 match_reg[8]; +} __packed; + +struct microcode_amd { + struct microcode_header_amd hdr; + unsigned int mpb[]; +}; + +#define PATCH_MAX_SIZE (3 * PAGE_SIZE) + static struct equiv_cpu_table { unsigned int num_entries; struct equiv_cpu_entry *entry; --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -33,11 +33,12 @@ #include #include -#include #include #include #include +#include "internal.h" + #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -32,11 +32,12 @@ #include #include -#include #include #include #include +#include "internal.h" + static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ --- /dev/null +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _X86_MICROCODE_INTERNAL_H +#define _X86_MICROCODE_INTERNAL_H + +#include +#include + +#include +#include + +struct ucode_patch { + struct list_head plist; + void *data; /* Intel uses only this one */ + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +extern struct list_head microcode_cache; + +struct device; + +enum ucode_state { + UCODE_OK = 0, + UCODE_NEW, + UCODE_UPDATED, + UCODE_NFOUND, + UCODE_ERROR, +}; + +struct microcode_ops { + enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); + + void (*microcode_fini_cpu)(int cpu); + + /* + * The generic 'microcode_core' part guarantees that + * the callbacks below run on a target cpu when they + * are being called. + * See also the "Synchronization" section in microcode_core.c. + */ + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); +}; + +extern struct ucode_cpu_info ucode_cpu_info[]; +struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); + +#define MAX_UCODE_COUNT 128 + +#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) +#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') +#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') +#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') +#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') +#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') +#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') + +#define CPUID_IS(a, b, c, ebx, ecx, edx) \ + (!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c)))) + +/* + * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. + * x86_cpuid_vendor() gets vendor id for BSP. + * + * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify + * coding, we still use x86_cpuid_vendor() to get vendor id for AP. + * + * x86_cpuid_vendor() gets vendor information directly from CPUID. + */ +static inline int x86_cpuid_vendor(void) +{ + u32 eax = 0x00000000; + u32 ebx, ecx = 0, edx; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) + return X86_VENDOR_INTEL; + + if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) + return X86_VENDOR_AMD; + + return X86_VENDOR_UNKNOWN; +} + +static inline unsigned int x86_cpuid_family(void) +{ + u32 eax = 0x00000001; + u32 ebx, ecx = 0, edx; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + return x86_family(eax); +} + +extern bool initrd_gone; + +#ifdef CONFIG_CPU_SUP_AMD +void load_ucode_amd_bsp(unsigned int family); +void load_ucode_amd_ap(unsigned int family); +void load_ucode_amd_early(unsigned int cpuid_1_eax); +int save_microcode_in_initrd_amd(unsigned int family); +void reload_ucode_amd(unsigned int cpu); +struct microcode_ops *init_amd_microcode(void); +void exit_amd_microcode(void); +#else /* CONFIG_MICROCODE_AMD */ +static inline void load_ucode_amd_bsp(unsigned int family) { } +static inline void load_ucode_amd_ap(unsigned int family) { } +static inline void load_ucode_amd_early(unsigned int family) { } +static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } +static inline void reload_ucode_amd(unsigned int cpu) { } +static inline struct microcode_ops *init_amd_microcode(void) { return NULL; } +static inline void exit_amd_microcode(void) { } +#endif /* !CONFIG_MICROCODE_AMD */ + +#ifdef CONFIG_CPU_SUP_INTEL +void load_ucode_intel_bsp(void); +void load_ucode_intel_ap(void); +int save_microcode_in_initrd_intel(void); +void reload_ucode_intel(void); +struct microcode_ops *init_intel_microcode(void); +#else /* CONFIG_CPU_SUP_INTEL */ +static inline void load_ucode_intel_bsp(void) { } +static inline void load_ucode_intel_ap(void) { } +static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } +static inline void reload_ucode_intel(void) { } +static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } +#endif /* !CONFIG_CPU_SUP_INTEL */ + +#endif /* _X86_MICROCODE_INTERNAL_H */ From patchwork Sat Aug 12 19:58:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134926 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1875591vqi; Sat, 12 Aug 2023 13:02:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEfN69SD0ajnoMF2OmYDm81B+ekWiNT1qOZHAlhXybrZSH3MPaL503RqFwuhTJUkbbkEm9+ X-Received: by 2002:aa7:d448:0:b0:523:1004:1ca0 with SMTP id q8-20020aa7d448000000b0052310041ca0mr4227497edr.5.1691870556018; Sat, 12 Aug 2023 13:02:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691870556; cv=none; d=google.com; s=arc-20160816; b=zCahePrdPEjdzHAp0MqnnF/ltLH/VDt2gZ8gEAIRfmzunA9SrTOACF3LmetIB4pNNW 0ZAJugEUh4yychojt1DfGSZ1DjV9Y8fWWqXLsZaUaQWK483Fq+hmNTKPfVHguL51/OcH WZPWpnX4qZo4Q72c/DMCKRemARPt4mfyJ578W5U8KZcDvrliKBH4jMMAhOwtNr9M7EF2 Mzn8slfmeaTn6lF4kHzJWejwzMXnnU4Up+MxhpGm8UTvzpeXM8le4MMK1oGS4aC48Mwi VdioUCWN4ffuGNsyDi/zT58WT/Pe3uGiCQgXm2ucAdBVd7rAX4NCLAnXKsMkjj21S7j6 CZGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=YMAsfYDkN/xyrOxScaRWZ72+V8OIVPbdwOmS7O9PF88=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=GzV9+YmpGxBKB/+ORKDmoFqfgRYIGyWYzCrQM9znxopBrInYnzAJasjT/6olJG3sRl UiClYRpwejlzRwMLbZRVsQIfE5ahTgu1UNGZtA3tDT1CMZPRrihQ8f2kDRvqOLzTUUe3 gS2r2K2vUK684n0PlQhTwKNxtCP+R1EkZ7Pb+03GLd5xDSuTJD+OU0zIBX0Vjj8h/ipe JY2i+4bm5KSUxz3sFKmQaO6lXuYvrj/9Qqh6RZp4/JEFQEkr/s6n9YCBlzFntWgjF0NW VJz6l9+RIeHZggFyBpCRs80NHaMdhI6e9chT+5p5BKRgsDkd/jf73Lk2egEouVrzjc4z TodA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FnwPzHlD; dkim=neutral (no key) header.i=@linutronix.de header.b=m+3BwOa4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u9-20020a1709064ac900b0099bc8f0358asi5231693ejt.918.2023.08.12.13.02.11; Sat, 12 Aug 2023 13:02:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FnwPzHlD; dkim=neutral (no key) header.i=@linutronix.de header.b=m+3BwOa4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230306AbjHLUAp (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230189AbjHLUAi (ORCPT ); Sat, 12 Aug 2023 16:00:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ED321998 for ; Sat, 12 Aug 2023 13:00:13 -0700 (PDT) Message-ID: <20230812195728.010895747@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870329; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YMAsfYDkN/xyrOxScaRWZ72+V8OIVPbdwOmS7O9PF88=; b=FnwPzHlDjX8J6q6NC1rBCx2LHxi8MVSsf34AGjtxF7M4h0ndwkVseyWcRAzSejqzV+RsDM C1mbUZFE6+2JU9EDF4mtmkjDW595bjZR1YydQXUc3yQkN1HaINg1oNqZSyzTgUVM2b1xpR ldWED9X7LhnRFK5nokgtjYjre0JRLSdpFIUnLKnlJsbJX1G8T8VA9faqBtx9qIRMrEnYtn LT0zsD9ice8CdIYB1TKP3H6CCE5h133tWX/XmgCIj2twzCH50ce3gEUq2RCWFk+FTtlSHH 4EnohddD19W0KrT8VYBn78OTtE79dtARbiz1Xa4SHXVtj7LX9kpVQPJ28we/1w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870329; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YMAsfYDkN/xyrOxScaRWZ72+V8OIVPbdwOmS7O9PF88=; b=m+3BwOa4D7AR1iptyHgfLAv/RkhXWwj3E+UBhzbBF/Zrw8VMbv7SAGxq5vH2XvomhSIjTR QGa4zVjeiMatZjBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 08/37] x86/microcode/intel: Remove debug code References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:49 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774054860058259707 X-GMAIL-MSGID: 1774054860058259707 From: Thomas Gleixner This is really of dubious value. Signed-off-by: Thomas Gleixner --- V2: Reordered in the series - Nikolay --- arch/x86/kernel/cpu/microcode/intel.c | 75 ---------------------------------- 1 file changed, 75 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -10,15 +10,7 @@ * Copyright (C) 2012 Fenghua Yu * H Peter Anvin" */ - -/* - * This needs to be before all headers so that pr_debug in printk.h doesn't turn - * printk calls into no_printk(). - * - *#define DEBUG - */ #define pr_fmt(fmt) "microcode: " fmt - #include #include #include @@ -405,69 +397,6 @@ scan_microcode(void *data, size_t size, return patch; } -static void show_saved_mc(void) -{ -#ifdef DEBUG - int i = 0, j; - unsigned int sig, pf, rev, total_size, data_size, date; - struct ucode_cpu_info uci; - struct ucode_patch *p; - - if (list_empty(µcode_cache)) { - pr_debug("no microcode data saved.\n"); - return; - } - - intel_cpu_collect_info(&uci); - - sig = uci.cpu_sig.sig; - pf = uci.cpu_sig.pf; - rev = uci.cpu_sig.rev; - pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); - - list_for_each_entry(p, µcode_cache, plist) { - struct microcode_header_intel *mc_saved_header; - struct extended_sigtable *ext_header; - struct extended_signature *ext_sig; - int ext_sigcount; - - mc_saved_header = (struct microcode_header_intel *)p->data; - - sig = mc_saved_header->sig; - pf = mc_saved_header->pf; - rev = mc_saved_header->rev; - date = mc_saved_header->date; - - total_size = get_totalsize(mc_saved_header); - data_size = intel_microcode_get_datasize(mc_saved_header); - - pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", - i++, sig, pf, rev, total_size, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); - - /* Look for ext. headers: */ - if (total_size <= data_size + MC_HEADER_SIZE) - continue; - - ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE; - ext_sigcount = ext_header->count; - ext_sig = (void *)ext_header + EXT_HEADER_SIZE; - - for (j = 0; j < ext_sigcount; j++) { - sig = ext_sig->sig; - pf = ext_sig->pf; - - pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", - j, sig, pf); - - ext_sig++; - } - } -#endif -} - /* * Save this microcode patch. It will be loaded early when a CPU is * hot-added or resumes. @@ -480,7 +409,6 @@ static void save_mc_for_early(struct uco mutex_lock(&x86_cpu_microcode_mutex); save_microcode_patch(uci, mc, size); - show_saved_mc(); mutex_unlock(&x86_cpu_microcode_mutex); } @@ -631,9 +559,6 @@ int __init save_microcode_in_initrd_inte intel_cpu_collect_info(&uci); scan_microcode(cp.data, cp.size, &uci, true); - - show_saved_mc(); - return 0; } From patchwork Sat Aug 12 19:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134931 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1880209vqi; Sat, 12 Aug 2023 13:15:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+QG7d40IB04A4QoxW3j/F2X9IXtpgg7y2iyPSyyTnfYPL9mX9SdqSRUSI5SkF7eYd5Tmf X-Received: by 2002:a2e:8814:0:b0:2b5:89a6:c12b with SMTP id x20-20020a2e8814000000b002b589a6c12bmr3938207ljh.10.1691871337270; Sat, 12 Aug 2023 13:15:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691871337; cv=none; d=google.com; s=arc-20160816; b=EsohaDZvZJQ72WsoHoGIHMXMM42DhmEoDU4xMpMedjhzvFy5T6drzqr0U29MkHw6Mx xqsxKvpyzF+TniiFm6HvDYfY81dsWUwUieOoo/wM6nT61qVIcN97zPd7bjtN3NhJgVia n0CzvSQ9n0fVPD3yQc1ayBrlgEOjtitd0JaddOTPN09++7XUM3Zr+MKhbbyxaJG57m6H vJN7SJBnXSGtE4chlqM0pe1k0pt1YI+jOE2KJONP4GHq34hTghXu9F3lhUC2p6ht5n/D ExDxEQ8K2/Z0I7fwi+0ny3ymxYklY4E7hLHYmq1Q4yroORQ1LxRqx8eG095vTZQnk/pr lB7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=+LnxIbJSjtZlbYPhhRKT8XWYvPxcIXTNXgcJ6FnPbbM=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=SfpLQDBkkrNjd6eaYiPqR0Yg4Ch9cqiIF5UHPQ2EOdheoKLyuT4j67OpZp+0IgEslP jl7joZEV8vNeC4CMdGFZG1kS8QH1xthui7aOgNqd5fDBhZxufHY4vbN+bCt5C6JKY2xa MP8MYYirSTI28FrX9ofLIY+1sos9bNSvCUyu5D+pV6BVa18W+qTjU+KbUsytz49L27Rm glmrYj8IbuzVyyBpnmaQmf06n5LhNUH5Orufws70y5QS65mL6ijU30v/cZLY2C38tx8O lsm98WOGWHdwPp28VVDU+o6uVUBaXLL2SnrvGWPxxUI77STr19uHJl82KNHH6Mpw5PSc W1Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wImgZvYW; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m23-20020a170906235700b0099ceec0a4aesi5303566eja.969.2023.08.12.13.15.11; Sat, 12 Aug 2023 13:15:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wImgZvYW; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230474AbjHLUBV (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjHLUBI (ORCPT ); Sat, 12 Aug 2023 16:01:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E39382D79 for ; Sat, 12 Aug 2023 13:00:49 -0700 (PDT) Message-ID: <20230812195728.069849788@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870331; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+LnxIbJSjtZlbYPhhRKT8XWYvPxcIXTNXgcJ6FnPbbM=; b=wImgZvYW+RCR1dnDUO7eZWHE2DLP4cQhfOnF7k0UMmMN/5wuwfkhSIZcWVuB/hn6CIKQDx 930XvbU4zTvV4Jk6bZc8eJKHs74AfAEfvN6g1sAxhH5uaFviw6EdFCmQW3VRgxFV1u9mor BDR8A2H+qridCSGYHobKBaIuycn+Oss4y7mYhdfrO1v8FrvE0ynZ6B10g0uEODVzqiKy08 e23cRolTDf61hOxBFL3JamTHLtJIXP5stDE57kSBR3KZCCblLJFBbOEzkS3Aopcv1kGJDA gClGO9sOPG0SeBTYWHvqckTsQjFX7BbjUcHVGP9vaFXvwp3D2N7JRhn8kBDo0g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870331; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+LnxIbJSjtZlbYPhhRKT8XWYvPxcIXTNXgcJ6FnPbbM=; b=LskouPJt7WBGAIH/Jb4BEbcZtUi5KSNOgpZ4VmG84w4Yaaw9EX4xYIwpW7f23WDCWlcHb+ 1Rhx/7DZA39X2SAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 09/37] x86/microcode/intel: Remove pointless mutex References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:50 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774055679386866341 X-GMAIL-MSGID: 1774055679386866341 From: Thomas Gleixner There is no concurreny. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -397,22 +397,6 @@ scan_microcode(void *data, size_t size, return patch; } -/* - * Save this microcode patch. It will be loaded early when a CPU is - * hot-added or resumes. - */ -static void save_mc_for_early(struct ucode_cpu_info *uci, u8 *mc, unsigned int size) -{ - /* Synchronization during CPU hotplug. */ - static DEFINE_MUTEX(x86_cpu_microcode_mutex); - - mutex_lock(&x86_cpu_microcode_mutex); - - save_microcode_patch(uci, mc, size); - - mutex_unlock(&x86_cpu_microcode_mutex); -} - static bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; @@ -829,12 +813,8 @@ static enum ucode_state generic_load_mic vfree(uci->mc); uci->mc = (struct microcode_intel *)new_mc; - /* - * If early loading microcode is supported, save this mc into - * permanent memory. So it will be loaded early when a CPU is hot added - * or resumes. - */ - save_mc_for_early(uci, new_mc, new_mc_size); + /* Save for CPU hotplug */ + save_microcode_patch(uci, new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, new_rev, uci->cpu_sig.rev); From patchwork Sat Aug 12 19:58:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134987 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1930476vqi; Sat, 12 Aug 2023 15:58:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGVN9YI9yEbd6glF1xvnNL1IIiiGDHJ3GppWea/MZQoj33vkm9QfKzQLqIZ1EC1mCCf2Dxg X-Received: by 2002:a17:903:22c9:b0:1b8:a936:1915 with SMTP id y9-20020a17090322c900b001b8a9361915mr8126782plg.22.1691881102006; Sat, 12 Aug 2023 15:58:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691881101; cv=none; d=google.com; s=arc-20160816; b=PsXTk5MsN5x1sgTRKxGhInmUBt+nOMVB93Jdfhy6c4GEvk8am5HdsIHxpZWwuO8CBe SrDQ7sHzAv8SKWU5wpuB+8RV7xH2bCc/Yb81j0jkJmspaHZMaHLuHeJJIC8pxahhZn1/ 4ptZVL1sPfjbUu6cmcRJr+L5hzUB2M8ilnK6tvIjbOOuunTjQYKSqTZc9CtFjWwds/UC ZQ8F99RHQ2v6Wb4SOeh1BQ+aoPgZQ4jOBht37w9OI++sjg0sejAo/ZMSO8/+N1C8vZ4r hTq1ogXBH3vEiDs2EbizLbGXfv1UxUEAfiH5JbmvXErti8cvU/0mz7Zid5QuRCkdg7Qt 1QhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=x7sZwm16k+DN6jvZS+REQb/YogoEg78SbOG09l90uXo=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=XTxTeJAGC3t28LVm8FEAqVXEL31sDQTrkHHxO5Q44urXrQ2NMJccTBCpdxM0xC6+YE 6bgeJe2OVXYFn+nIRI3BwDDhaJ3KmRWdAxpO8TzxydNDxejeoH2VC1tKLWkwV4MRtk5p nl55njlsSVwh+KN5f39f2uSgRxmJmdcgUhoGU0vxlhAqpxSAvoxa/bvGjE/KEhXBtfaj jfDL12jNtLmn3/fvp6umFjaA+/jDzDFZCgwdrS2FAdbRF8ANsejZmJYvMtwIWzaff2rY q2EKctc/PpJIZQEXd/uLtC+gkH2GC/49yK6Gofji11J85HdN9fB45gf6Ogd01LE4s78r /Xkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Jub2LnNQ; dkim=neutral (no key) header.i=@linutronix.de header.b=FQhqhw+u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n6-20020a170903110600b001b8847d973fsi5698753plh.219.2023.08.12.15.57.59; Sat, 12 Aug 2023 15:58:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Jub2LnNQ; dkim=neutral (no key) header.i=@linutronix.de header.b=FQhqhw+u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230440AbjHLUBP (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230474AbjHLUBD (ORCPT ); Sat, 12 Aug 2023 16:01:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D25F62D6D for ; Sat, 12 Aug 2023 13:00:48 -0700 (PDT) Message-ID: <20230812195728.129971794@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870332; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x7sZwm16k+DN6jvZS+REQb/YogoEg78SbOG09l90uXo=; b=Jub2LnNQCFeUdkcJhVF8CCjgRCpx1V8iqI2glFd+W3WvFCfRP3txvfDUsA0pL9R1Q4eLOK ELBqHs9of2l4RWvnCu7GwyefD30gYYAilT2I7FcdWMGPY8z7Y22PPB6o0+qRLE7TFrsjOV Xgq1eeP1Q/KZ0tEP5/ywl57BjtYUaHoCpwwhBvHweJBnt4wEaXUeGiMKEC9Fm3PFulr3IY N4uoFYB5P5hG2LUIRIczC0uiCKs+p0ov8whXxbFD0m8d70M5p9P3Ay3hR7UKwaaWXcmEc8 kqWDkN02XwVSoscXgdcwOZvhWULPolUQRtVK85TpWNCHVzKCwAbalCz91DE0Hw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870332; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=x7sZwm16k+DN6jvZS+REQb/YogoEg78SbOG09l90uXo=; b=FQhqhw+uBk1ashXZbLaxl3LfpwdTAMaSphcPRKNS1qUYn6rLed5hs61pkyUpMqMFa8fipY DjSRzhiQH7fOInAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 10/37] x86/microcode/intel: Rip out mixed stepping support for Intel CPUs References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:52 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774065918364114856 X-GMAIL-MSGID: 1774065918364114856 From: Ashok Raj Mixed steppings aren't supported on Intel CPUs. Only one patch is required for the entire system. The caching of micro code blobs which match the family and model is therefore pointless and in fact it is disfunctional as CPU hotplug updates use only a single microcode blob, i.e. the one where *intel_ucode_patch points to. Remove the microcode cache and make it an AMD local feature. [ tglx: Save only at the end. Otherwise random microcode ends up in the pointer for early loading ] Originally-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- V2: Fix the bogus condition - Borislav --- arch/x86/kernel/cpu/microcode/amd.c | 10 ++ arch/x86/kernel/cpu/microcode/core.c | 2 arch/x86/kernel/cpu/microcode/intel.c | 135 +++++-------------------------- arch/x86/kernel/cpu/microcode/internal.h | 10 -- 4 files changed, 36 insertions(+), 121 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -37,6 +37,16 @@ #include "internal.h" +struct ucode_patch { + struct list_head plist; + void *data; + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +static LIST_HEAD(microcode_cache); + #define UCODE_MAGIC 0x00414d44 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 #define UCODE_UCODE_TYPE 0x00000001 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,8 +46,6 @@ static bool dis_ucode_ldr = true; bool initrd_gone; -LIST_HEAD(microcode_cache); - /* * Synchronization. * --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,10 +33,10 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch; +static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core; +static int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -253,81 +253,26 @@ static int has_newer_microcode(void *mc, return intel_find_matching_signature(mc, csig, cpf); } -static struct ucode_patch *memdup_patch(void *data, unsigned int size) +static void save_microcode_patch(void *data, unsigned int size) { - struct ucode_patch *p; + struct microcode_header_intel *p; - p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL); - if (!p) - return NULL; - - p->data = kmemdup(data, size, GFP_KERNEL); - if (!p->data) { - kfree(p); - return NULL; - } - - return p; -} - -static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigned int size) -{ - struct microcode_header_intel *mc_hdr, *mc_saved_hdr; - struct ucode_patch *iter, *tmp, *p = NULL; - bool prev_found = false; - unsigned int sig, pf; - - mc_hdr = (struct microcode_header_intel *)data; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - mc_saved_hdr = (struct microcode_header_intel *)iter->data; - sig = mc_saved_hdr->sig; - pf = mc_saved_hdr->pf; - - if (intel_find_matching_signature(data, sig, pf)) { - prev_found = true; - - if (mc_hdr->rev <= mc_saved_hdr->rev) - continue; - - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer %p\n", data); - else { - list_replace(&iter->plist, &p->plist); - kfree(iter->data); - kfree(iter); - } - } - } - - /* - * There weren't any previous patches found in the list cache; save the - * newly found. - */ - if (!prev_found) { - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer for %p\n", data); - else - list_add_tail(&p->plist, µcode_cache); - } + kfree(intel_ucode_patch); + intel_ucode_patch = NULL; + p = kmemdup(data, size, GFP_KERNEL); if (!p) return; - if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) - return; - /* * Save for early loading. On 32-bit, that needs to be a physical * address as the APs are running from physical addresses, before * paging has been enabled. */ if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); + intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p); else - intel_ucode_patch = p->data; + intel_ucode_patch = (struct microcode_intel *)p; } /* @@ -339,6 +284,7 @@ scan_microcode(void *data, size_t size, { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; + u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; while (size) { @@ -348,8 +294,7 @@ scan_microcode(void *data, size_t size, mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); - if (!mc_size || - mc_size > size || + if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; @@ -361,31 +306,16 @@ scan_microcode(void *data, size_t size, continue; } - if (save) { - save_microcode_patch(uci, data, mc_size); + /* BSP scan: Check whether there is newer microcode */ + if (!save && cur_rev >= mc_header->rev) goto next; - } - - if (!patch) { - if (!has_newer_microcode(data, - uci->cpu_sig.sig, - uci->cpu_sig.pf, - uci->cpu_sig.rev)) - goto next; - - } else { - struct microcode_header_intel *phdr = &patch->hdr; - - if (!has_newer_microcode(data, - phdr->sig, - phdr->pf, - phdr->rev)) - goto next; - } + /* Save scan: Check whether there is newer or matching microcode */ + if (save && cur_rev != mc_header->rev) + goto next; - /* We have a newer patch, save it. */ patch = data; + cur_rev = mc_header->rev; next: data += mc_size; @@ -394,6 +324,9 @@ scan_microcode(void *data, size_t size, if (size) return NULL; + if (save && patch) + save_microcode_patch(patch, mc_size); + return patch; } @@ -612,26 +545,10 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci, true); } -static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) +/* Accessor for microcode pointer */ +static struct microcode_intel *ucode_get_patch(void) { - struct microcode_header_intel *phdr; - struct ucode_patch *iter, *tmp; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - - phdr = (struct microcode_header_intel *)iter->data; - - if (phdr->rev <= uci->cpu_sig.rev) - continue; - - if (!intel_find_matching_signature(phdr, - uci->cpu_sig.sig, - uci->cpu_sig.pf)) - continue; - - return iter->data; - } - return NULL; + return intel_ucode_patch; } void reload_ucode_intel(void) @@ -641,7 +558,7 @@ void reload_ucode_intel(void) intel_cpu_collect_info(&uci); - p = find_patch(&uci); + p = ucode_get_patch(); if (!p) return; @@ -685,7 +602,7 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; /* Look for a newer patch in our cache: */ - mc = find_patch(uci); + mc = ucode_get_patch(); if (!mc) { mc = uci->mc; if (!mc) @@ -814,7 +731,7 @@ static enum ucode_state generic_load_mic uci->mc = (struct microcode_intel *)new_mc; /* Save for CPU hotplug */ - save_microcode_patch(uci, new_mc, new_mc_size); + save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, new_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -8,16 +8,6 @@ #include #include -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct device; enum ucode_state { From patchwork Sat Aug 12 19:58:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134939 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1887448vqi; Sat, 12 Aug 2023 13:39:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH6b/i735fj9Gd7nRVKbLzlF9r/ik2b3RDaQwjKjivJh9kYh5o7NVsZeCDnLSd0LLWnerjM X-Received: by 2002:a17:90a:e542:b0:263:eb0e:5681 with SMTP id ei2-20020a17090ae54200b00263eb0e5681mr6868160pjb.3.1691872748157; Sat, 12 Aug 2023 13:39:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691872748; cv=none; d=google.com; s=arc-20160816; b=MrrfTcb5I86K1mDX1l+Sa5zXezKRv9sEoLYImSwFJpll2DotEt8Ysu1nQesy5JVKcV QxB+SX/Me7oZ1F4Uwt3xo0fy90oi2lWaJ/30B/bDx5x2l1Wp9aSwbu/vj/bXZyx4ess5 trY1p1f+dGidoA6I3N8a9EVO6Dmm98woMKTjSL5kD3iQygw0ATykA+7bsNjA3Zo3UGtl vRG8c0iEaRebPHE5yw1oNx88qqy2i2O1jAPdFRCG/TN+5FnOeKTlQ3qlal7sK0IPh8lk OSMzFqKovxMEVc8Pb0V5FBCsbuBnBEUy9E5A/WaK893uWJb1iuRpThPrFZ5DcxWNow42 LpCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=UL/mdoYp2YOPutZME2dSUHU8tUoO072JwJbw3jCdJRc=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=h1yfHz4eb3AjlwfUw/fjtr7O+O7M3xVwBoi0ObtBOZENvAHYGGcXSeo9WTVOqr2kOl F6w7DjUi/+ZUwrIWit2cJe2Wond1vOzzNuCc0rPgbE0jOY8XhQ3SQemKqgt7GOYknDej oeRq6dnKDX/7alOIZ+5qU4uXs40ByMrFK8f0nnsTdCFGh9WFNmASE61/zTwtom5OCao6 Gt5wsxH/+Mv5a9go5TWTlq/eg8eFjTdCaAdUufUiJYp+z04tHBz+qjztuhlCvM37ODfN jV/WWm8Li4Yb32ZqNSgtZprspQTeVfURFyEekrDkBUDorvGOyTRYgHsFnvE0J97fNiK+ +bFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=k196Gikc; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id co20-20020a17090afe9400b002534f4ce2b6si7358364pjb.125.2023.08.12.13.38.52; Sat, 12 Aug 2023 13:39:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=k196Gikc; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230415AbjHLUAw (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230349AbjHLUAs (ORCPT ); Sat, 12 Aug 2023 16:00:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C5641FE6 for ; Sat, 12 Aug 2023 13:00:18 -0700 (PDT) Message-ID: <20230812195728.188483733@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870334; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UL/mdoYp2YOPutZME2dSUHU8tUoO072JwJbw3jCdJRc=; b=k196Gikce4bNi5roHHck82eFjbXLl9qvTM21pyAwgSV1PGVZpP68bSXUquAaTlo45GKi3b 0D5+H5Upb40rc6ezn73UIpYOgu/M/gDP4JoYj0G4dN81V0dc6mwuIAG0uy6VYsvE4PRWok YtU2rUe4OA5EcN5lBn4YpodKCU6WWgxKUcMggfWKFjyPwAGQHd72WZlgJp2eOvIecTOBzi xET5TmbObUsnQlOd8HDXhVC8UlDymZm8Yy8I4rEjAnpqGMC8HUuXsGjOFuYokLWvIzRQmN KvbMjTNo4ijiWVxIkHFJ3Ac2egSkCcSnT5jW/UI4H2clluMxBvqF2oc+XcXIBA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870334; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UL/mdoYp2YOPutZME2dSUHU8tUoO072JwJbw3jCdJRc=; b=wYMXV8LdRz0zsOeaxUoMbnhf8qyYqy8Dpx2tC+1KmIkxAQI2AvQetjwn2uLa0ioUSVfAtW IxKPuVssEC4/bBCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 11/37] x86/microcode/intel: Simplify scan_microcode() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:53 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774057158778258014 X-GMAIL-MSGID: 1774057158778258014 Make it readable and comprehensible. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -275,22 +275,16 @@ static void save_microcode_patch(void *d intel_ucode_patch = (struct microcode_intel *)p; } -/* - * Get microcode matching with BSP's model. Only CPUs with the same model as - * BSP can stay in the platform. - */ -static struct microcode_intel * -scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) +/* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ +static struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; - while (size) { - if (size < sizeof(struct microcode_header_intel)) - break; - + for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); @@ -298,27 +292,19 @@ scan_microcode(void *data, size_t size, intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - size -= mc_size; - - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, - uci->cpu_sig.pf)) { - data += mc_size; + if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - } /* BSP scan: Check whether there is newer microcode */ if (!save && cur_rev >= mc_header->rev) - goto next; + continue; /* Save scan: Check whether there is newer or matching microcode */ if (save && cur_rev != mc_header->rev) - goto next; + continue; patch = data; cur_rev = mc_header->rev; - -next: - data += mc_size; } if (size) From patchwork Sat Aug 12 19:58:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134972 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1908323vqi; Sat, 12 Aug 2023 14:45:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE9GMxXoiqVWbo5ZdIKjZrHnEIxSykvGhn0GaSaNqcmLdBYnUwCExpLxioUNPhuo+UuwyLz X-Received: by 2002:a05:6a00:3919:b0:681:6169:e403 with SMTP id fh25-20020a056a00391900b006816169e403mr5005367pfb.8.1691876710112; Sat, 12 Aug 2023 14:45:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876710; cv=none; d=google.com; s=arc-20160816; b=HYJDdNiQiau0Fbs4YqsXq9g1ixAvJmaKR0Y+B4kx4piS5+A0SG7Vub9zhZhqDU5r6t HyHHYaX35HWvYVGRitxM3tLWonz+4zhtszED2PdiWkwDyNf3N9wfRcOrowFfcm4lIEM+ chJZDLcTJg2LgqM6Vz9YLeFSgncgdChtHl8+mEkQlnKwh5pxlU7AvzSSEGvtdLnSIVmI plmDUAsh8gkCMS520GfEVakvyCkkNkJ9Wyryb/Dx6eavPq0ik0a30CwY9nCNxLo6DO5Y 1zQN+S3cbUMGx/0thqcju/BtgxoCCW2vN/7XVNPoZyPWm6mJa2a9gMxFCE6RJwhXn3/B o1nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=f+UFwCEFZREA8XDdgjvWrupo4jQM3/zWUCG1oemkcwo=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=ynQUCyg+CJD/O5kpEZk2GZyH9WRLhoVuaHcJOIVCLT0UveRW7EvbkyraMuv2GdtLW0 B8L3UQ+Q+9FF5r8mVxZlcbcCGfOaD2eZrfkHZWCAKkOdfJs1EvwY2onB+Tn1eNEgushq sgvSheDo6g9/uC9396EGWR4xV9Xu3mI+KQh0//hbPdQJVFDOu1TBB//pXVPuIrrC1uKH hF2PGUr5Y8xtUVCx5UB7awycXyvVZ17xCZck87VOKZd9OPQMP9BiYxo95kkkjyfmy5LM a3DQjrEIqkMtc9YPJJQTCq/i2RAwutxiILlc7pej5lO6WWz4iNd7XkDG5HYHpWd9sasT MRDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tBHDKY+t; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n50-20020a056a000d7200b006785d3c33b6si5380814pfv.285.2023.08.12.14.44.55; Sat, 12 Aug 2023 14:45:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tBHDKY+t; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230272AbjHLUAz (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230304AbjHLUAt (ORCPT ); Sat, 12 Aug 2023 16:00:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 175CC199A for ; Sat, 12 Aug 2023 13:00:20 -0700 (PDT) Message-ID: <20230812195728.246048244@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=f+UFwCEFZREA8XDdgjvWrupo4jQM3/zWUCG1oemkcwo=; b=tBHDKY+tOBlIDxBRXfTvn6gRLVPE+1zyPSKMD2HK6zaIDGqQ/UMDTZaUiQtzKoFZyMo7Yi JfzA0W78akWOqNIfyeRP4F+s1NQYbswnEVoJgADs3y/Ecmrm78E75ZLW3Ubqz7QzrOiljy iHVKprQ7RTYebqS5DjifrVzrhISJFUMLFVPJ/JSYg4I7MbjglGgtKglM5hOCZijx3J2dzz vMAG/v+pMgWIbtMAtJClQ5+bJGuwllJgAiTxDdoousGTsee2LkUQg4TrGIXiEnYVNosvlS k0ehEETEeCPoXpdlPHWAqjRddQ3ASW/RnEFtpfCyEJA6YvIp1CRDel8UI7955Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870335; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=f+UFwCEFZREA8XDdgjvWrupo4jQM3/zWUCG1oemkcwo=; b=8ITEq0BJT9vucr6VcxMCsL2vDO7dLp6zXiylsFC202BUMsn2qdTiZemMBuZPqHzp9gLVgp V0c/NdwFDaSoktCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 12/37] x86/microcode/intel: Simplify and rename generic_load_microcode() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:55 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774061313287810161 X-GMAIL-MSGID: 1774061313287810161 so it becomes less obfuscated and rename it because there is nothing generic about it. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 47 ++++++++++++---------------------- 1 file changed, 17 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -240,19 +240,6 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) -{ - struct microcode_header_intel *mc_hdr = mc; - - if (mc_hdr->rev <= new_rev) - return 0; - - return intel_find_matching_signature(mc, csig, cpf); -} - static void save_microcode_patch(void *data, unsigned int size) { struct microcode_header_intel *p; @@ -645,14 +632,12 @@ static enum ucode_state apply_microcode_ return ret; } -static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) +static enum ucode_state read_ucode_intel(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; - enum ucode_state ret = UCODE_OK; - int new_rev = uci->cpu_sig.rev; + int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - unsigned int csig, cpf; while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; @@ -669,6 +654,7 @@ static enum ucode_state generic_load_mic pr_err("error! Bad data in microcode data file (totalsize too small)\n"); break; } + data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); @@ -691,16 +677,17 @@ static enum ucode_state generic_load_mic break; } - csig = uci->cpu_sig.sig; - cpf = uci->cpu_sig.pf; - if (has_newer_microcode(mc, csig, cpf, new_rev)) { - vfree(new_mc); - new_rev = mc_header.rev; - new_mc = mc; - new_mc_size = mc_size; - mc = NULL; /* trigger new vmalloc */ - ret = UCODE_NEW; - } + if (cur_rev >= mc_header.rev) + continue; + + if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + continue; + + vfree(new_mc); + cur_rev = mc_header.rev; + new_mc = mc; + new_mc_size = mc_size; + mc = NULL; } vfree(mc); @@ -720,9 +707,9 @@ static enum ucode_state generic_load_mic save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); + cpu, cur_rev, uci->cpu_sig.rev); - return ret; + return UCODE_NEW; } static bool is_blacklisted(unsigned int cpu) @@ -771,7 +758,7 @@ static enum ucode_state request_microcod kvec.iov_base = (void *)firmware->data; kvec.iov_len = firmware->size; iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size); - ret = generic_load_microcode(cpu, &iter); + ret = read_ucode_intel(cpu, &iter); release_firmware(firmware); From patchwork Sat Aug 12 19:58:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134962 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904612vqi; Sat, 12 Aug 2023 14:32:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHMQ3ZAefVvdkYtN+dZQo60Dyg043lsTaRp2xzi1QuN5Lgjg7IYQFXAxsSLmJmGd2dhUFR9 X-Received: by 2002:a17:902:d2c1:b0:1bb:83cd:ad8b with SMTP id n1-20020a170902d2c100b001bb83cdad8bmr4559504plc.30.1691875961558; Sat, 12 Aug 2023 14:32:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875961; cv=none; d=google.com; s=arc-20160816; b=eZkn5SIili0t/mEe/4t5VJ8Xrf5S6fCRsZi7a3Qe4TlV4qYxPI9WPwFseiURuhMw9T 0a5hm5+7jJG1aE/vtjpljy6eUqytGVEsU6Y4+YhAyY0maW7araTijzSh01T2kC/BgMQH 2mcqgF6S3wfotSGnYCgNFX1kkD3jxQ0qmREuFgG1M7tHtBBhy6loKk/KzU53wduTCaq1 Dul3neWgKKQqFZLAphLctV9D2QQ4jomfYQ06r2nr9vwjBhXxHLj3mTDYR7BP7h0Y3eip YdOkpK/YTOuDq9iBJLiIyKdJtvGSwn0RNNBiG5YcHwDlFMgJh8klvzmCIDLV9OLJPn3v ytJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=GKoAhQM+YL5b11O1A2S3VwOaagu7XrxM1Ya616PWMyI=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=tvJifvqyOGGOWs3NXF4sU8ci2PgNqejrvQ+gp+O+On6Bjaj7BrjoLfMD83m66QdRAf +hBv0p7tH8FxVkhqWn/G/UMbCAkfCKR5ZUc7IE80Nf12QK6qlxc/ASKsa/6+RHW4JdcB /Q+WIGYj8900Bqjjx5EllSsYQ8nXvKXgPTNHC1yZrOp8C0lhUy6qw3jAi2aHNFwlgvvi 1qDBm9XIAFXsdqWlBUXQ88KvmfzHMTwvRjt+PbGLc5O2WsxVClcw9PM1ypyL3TYBoJOM Syvdgg9WJZviLOBkmTEkCULMLKrJM6wcmqufOKc3vKE7hTMOpVrBWuxQk4iagkj4cfMD G7MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YkMAatzw; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i3-20020a170902c94300b001bbd0797a55si5566970pla.359.2023.08.12.14.32.29; Sat, 12 Aug 2023 14:32:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YkMAatzw; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230465AbjHLUBC (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230413AbjHLUAw (ORCPT ); Sat, 12 Aug 2023 16:00:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1D4F1BD2 for ; Sat, 12 Aug 2023 13:00:29 -0700 (PDT) Message-ID: <20230812195728.304366279@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GKoAhQM+YL5b11O1A2S3VwOaagu7XrxM1Ya616PWMyI=; b=YkMAatzwa0AVYdTUBSXVGWuw5IFw3f4GjcpHGTyHJwmcTyzVMtNlF4lQDq5qKzMawU0KeF HbwbcrBZhH/Opf5X9YvVw3HR86zTwa5ZlBK/47cyvTaS3jTYAKXMQTLK3UXslZ0DMUdMHI nYTNa/5DUSJfXXSXDmTM/T087dFkZHQwtQLDK8xk/Zs5zpe+t2lOg1JQ3JDpKF1dXIxVln 5QQ9lvupvJk+Sj+gqS5fki2wKTLcDzqQV3RggV5znu+FnscnJMzbesh9Xi8TNMZA/SNWkb SirZt3OtVpCnuEhWp3CWHjjEy0zwXIOSu6f7pf0LDgsV36WteuHpQBTZGxxk/w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GKoAhQM+YL5b11O1A2S3VwOaagu7XrxM1Ya616PWMyI=; b=4HQXqIMgEzVJkgqGLhuwYjukPcAlUyUYgWdixh3Kamb4uxjv+uU63NMPgbyhMtDDOEskBk cOQScMsSFDctgIBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 13/37] x86/microcode/intel: Cleanup code further References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:56 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060528088866232 X-GMAIL-MSGID: 1774060528088866232 From: Thomas Gleixner Sanitize the microcode scan loop, fixup printks and move the initrd loading function next to the place where it is used and mark it __init. Signed-off-by: Thomas Gleixner --- V2: Fix changelog - Nikolay --- arch/x86/kernel/cpu/microcode/intel.c | 82 +++++++++++++--------------------- 1 file changed, 33 insertions(+), 49 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -36,7 +36,7 @@ static const char ucode_path[] = "kernel static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core __ro_after_init; +static unsigned int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -303,37 +303,10 @@ static struct microcode_intel *scan_micr return patch; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) -{ - unsigned int eax = 1, ebx, ecx = 0, edx; - struct firmware fw; - char name[30]; - - if (IS_ENABLED(CONFIG_X86_32)) - return false; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - sprintf(name, "intel-ucode/%02x-%02x-%02x", - x86_family(eax), x86_model(eax), x86_stepping(eax)); - - if (firmware_request_builtin(&fw, name)) { - cp->size = fw.size; - cp->data = (void *)fw.data; - return true; - } - - return false; -} - static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, - new_rev, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } #ifdef CONFIG_X86_32 @@ -427,6 +400,28 @@ static int apply_microcode_early(struct return 0; } +static bool load_builtin_intel_microcode(struct cpio_data *cp) +{ + unsigned int eax = 1, ebx, ecx = 0, edx; + struct firmware fw; + char name[30]; + + if (IS_ENABLED(CONFIG_X86_32)) + return false; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + sprintf(name, "intel-ucode/%02x-%02x-%02x", + x86_family(eax), x86_model(eax), x86_stepping(eax)); + + if (firmware_request_builtin(&fw, name)) { + cp->size = fw.size; + cp->data = (void *)fw.data; + return true; + } + return false; +} + int __init save_microcode_in_initrd_intel(void) { struct ucode_cpu_info uci; @@ -518,25 +513,16 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci, true); } -/* Accessor for microcode pointer */ -static struct microcode_intel *ucode_get_patch(void) -{ - return intel_ucode_patch; -} - void reload_ucode_intel(void) { - struct microcode_intel *p; struct ucode_cpu_info uci; intel_cpu_collect_info(&uci); - p = ucode_get_patch(); - if (!p) + uci.mc = intel_ucode_patch; + if (!uci.mc) return; - uci.mc = p; - apply_microcode_early(&uci, false); } @@ -574,8 +560,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - /* Look for a newer patch in our cache: */ - mc = ucode_get_patch(); + mc = intel_ucode_patch; if (!mc) { mc = uci->mc; if (!mc) @@ -766,18 +751,17 @@ static enum ucode_state request_microcod } static struct microcode_ops microcode_intel_ops = { - .request_microcode_fw = request_microcode_fw, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .request_microcode_fw = request_microcode_fw, + .collect_cpu_info = collect_cpu_info, + .apply_microcode = apply_microcode_intel, }; -static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) +static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) { u64 llc_size = c->x86_cache_size * 1024ULL; do_div(llc_size, c->x86_max_cores); - - return (int)llc_size; + llc_size_per_core = (unsigned int)llc_size; } struct microcode_ops * __init init_intel_microcode(void) @@ -790,7 +774,7 @@ struct microcode_ops * __init init_intel return NULL; } - llc_size_per_core = calc_llc_size_per_core(c); + calc_llc_size_per_core(c); return µcode_intel_ops; } From patchwork Sat Aug 12 19:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134980 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1916592vqi; Sat, 12 Aug 2023 15:08:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH7ILgea73/ejZK/CWD38ewqDMkdtXpkpJy1Fja4ZtSpXQdCLG65OAzSMG1nS/2QZOArQIL X-Received: by 2002:a05:6a21:6d92:b0:13c:ca8b:7e29 with SMTP id wl18-20020a056a216d9200b0013cca8b7e29mr8412452pzb.12.1691878135558; Sat, 12 Aug 2023 15:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691878135; cv=none; d=google.com; s=arc-20160816; b=ouEjWUpT1gtiIQYKNps0k7GlUm2ZtkT1qnkv1SERl8EMM7nKSU4OWPBQMzSwTvdLaO ZuUQBjOzuinoE21lBLxUpqc2P+lLC2V9X1lqigwHYOTemt6y1pcjQ8x8NLbVVq+nNcVc Amv3SwF9NBcw2V9msLewV87J6Cx3rx5i6Rmc17itkjffH3sHbJ8IUBjIZG8hqn5QiLSu b6i6QrEp/Jj+y4Clkn1t5IKu/1BAetBjtVPSvb3D/hL+FXz+0+NL8olYdbywiAF1ATsQ mWrVusMVt2Uy0PdFIAsrJq7CVr8T5xfcJCNxoAyXTjWeIheQRgm9Bkf+vrkC3HjcYble D+1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=bPS0cgHUesN2Rv+0Fkfjz+I6MM2LDsw2pyVoNrGm9hw=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=mLuyQHUVRvjayIly3VqZJb868/LLwbVP/2Ob+JyD8mdTe1PVr5c1vEFl5eWSniYTlj CK/zGL6PzG43kGVbyXjb7cj1Ulx3ji7hYG4wf1fEcZWBajGyCsaqBfnIR181Lja8gaMM rTnaU6AUEwLRcAjx07W/04v4xQsVaPqLyNKVX1uU+nPRf7If8BzI5CU1RHhybUefLonP C1OuKN8S2kzPkedvsuumUY1PKaLGNhxYjhyv7SXSbu4qaTFY64K1ImFteJhr0knDEIKA AkrzHZHMOutzfXjlomk50SsbLXt7YwYBQoCifgdZBqoRA0sEn0VtjGmBG/8/24lQ1U5O tMuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DMjAKttu; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r32-20020a632060000000b00563e93dfc8dsi5369160pgm.375.2023.08.12.15.08.41; Sat, 12 Aug 2023 15:08:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DMjAKttu; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230425AbjHLUA6 (ORCPT + 99 others); Sat, 12 Aug 2023 16:00:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230393AbjHLUAw (ORCPT ); Sat, 12 Aug 2023 16:00:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F4FC30F5 for ; Sat, 12 Aug 2023 13:00:26 -0700 (PDT) Message-ID: <20230812195728.361431946@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870338; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bPS0cgHUesN2Rv+0Fkfjz+I6MM2LDsw2pyVoNrGm9hw=; b=DMjAKttuZ4msxTMvpwMJ8PGu/17mXaAgZqsRuzDOPAqwJ+PN5Fu8tWnGmpsg2nmdIqQsI5 wpOBEyI8K6tL6Zi9ezzYMqyC7LBn3JB+Kmm428p0lvum+H+kjnGA0XY12XYevL4hdayFrZ 3hmNL2BT/EmciJkrtLHqmlMwlnUI28OYYwYKrsisrkGz+MoIQJYatRUqKZC+rAAxda1eWI 5hquNQRALDtImr9K1qdePghd5cPgo8PP0Lz1naYggVOtzF6VoxPpHrttQ2+KlL/S0Kxc/1 Qfbi9il00aqtQhnLtE+eO7RZlj4DJfhom4ItngBsDkJHlhj+HUV2Jio2Hhj08Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870338; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bPS0cgHUesN2Rv+0Fkfjz+I6MM2LDsw2pyVoNrGm9hw=; b=4hYO+P2fw+YY34dJC2gk74zzduaFZkCOXVIfnF2wxlLz46jQ01Tzoup70vtw0fd0hpoMAZ VWaaf/8Rr6sgxwBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 14/37] x86/microcode/intel: Simplify early loading References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:58 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062807974696068 X-GMAIL-MSGID: 1774062807974696068 From: Thomas Gleixner The early loading code is overly complicated: - It scans the builtin/initrd for microcode not only on the BSP, but also on all APs during early boot and then later in the boot process it scans again to duplicate and save the microcode before initrd goes away. That's a pointless exercise because this can be simply done before bringing up the APs when the memory allocator is up and running. - Saving the microcode from within the scan loop is completely non-obvious and a left over of the microcode cache. This can be done at the call site now which makes it obvious. Rework the code so that only the BSP scans the builtin/initrd microcode once during early boot and save it away in an early initcall for later use. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 arch/x86/kernel/cpu/microcode/intel.c | 191 +++++++++++++------------------ arch/x86/kernel/cpu/microcode/internal.h | 2 3 files changed, 86 insertions(+), 111 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -207,10 +207,6 @@ static int __init save_microcode_in_init int ret = -EINVAL; switch (c->x86_vendor) { - case X86_VENDOR_INTEL: - if (c->x86 >= 6) - ret = save_microcode_in_initrd_intel(); - break; case X86_VENDOR_AMD: if (c->x86 >= 0x10) ret = save_microcode_in_initrd_amd(cpuid_eax(1)); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,7 +33,7 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch __read_mostly; +static struct microcode_intel *ucode_patch_va __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -240,31 +240,34 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -static void save_microcode_patch(void *data, unsigned int size) +static void update_ucode_pointer(struct microcode_intel *mc) { - struct microcode_header_intel *p; - - kfree(intel_ucode_patch); - intel_ucode_patch = NULL; - - p = kmemdup(data, size, GFP_KERNEL); - if (!p) - return; + kfree(ucode_patch_va); /* - * Save for early loading. On 32-bit, that needs to be a physical - * address as the APs are running from physical addresses, before - * paging has been enabled. + * Save the virtual address for early loading on 64bit + * and for eventual free on late loading. + * + * On 32-bit, that needs to store the physical address too as the + * APs are loading before paging has been enabled. */ - if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p); + ucode_patch_va = mc; +} + +static void save_microcode_patch(struct microcode_intel *patch) +{ + struct microcode_intel *mc; + + mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + if (mc) + update_ucode_pointer(mc); else - intel_ucode_patch = (struct microcode_intel *)p; + pr_err("Unable to allocate microcode memory\n"); } /* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ -static struct microcode_intel *scan_microcode(void *data, size_t size, - struct ucode_cpu_info *uci, bool save) +static __init struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; @@ -282,25 +285,15 @@ static struct microcode_intel *scan_micr if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - /* BSP scan: Check whether there is newer microcode */ - if (!save && cur_rev >= mc_header->rev) - continue; - - /* Save scan: Check whether there is newer or matching microcode */ - if (save && cur_rev != mc_header->rev) + /* Check whether there is newer microcode */ + if (cur_rev >= mc_header->rev) continue; patch = data; cur_rev = mc_header->rev; } - if (size) - return NULL; - - if (save && patch) - save_microcode_patch(patch, mc_size); - - return patch; + return size ? NULL : patch; } static void print_ucode_info(int old_rev, int new_rev, unsigned int date) @@ -355,14 +348,14 @@ static inline void print_ucode(int old_r } #endif -static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; mc = uci->mc; if (!mc) - return 0; + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -388,7 +381,7 @@ static int apply_microcode_early(struct rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + return UCODE_ERROR; uci->cpu_sig.rev = rev; @@ -397,10 +390,10 @@ static int apply_microcode_early(struct else print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); - return 0; + return UCODE_UPDATED; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) +static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; struct firmware fw; @@ -422,108 +415,96 @@ static bool load_builtin_intel_microcode return false; } -int __init save_microcode_in_initrd_intel(void) +static __init struct microcode_intel *get_ucode_from_cpio(struct ucode_cpu_info *uci) { - struct ucode_cpu_info uci; + bool use_pa = IS_ENABLED(CONFIG_X86_32); + const char *path = ucode_path; struct cpio_data cp; - /* - * initrd is going away, clear patch ptr. We will scan the microcode one - * last time before jettisoning and save a patch, if found. Then we will - * update that pointer too, with a stable patch address to use when - * resuming the cores. - */ - intel_ucode_patch = NULL; + /* Paging is not yet enabled on 32bit! */ + if (IS_ENABLED(CONFIG_X86_32)) + path = (const char *)__pa_nodebug(ucode_path); + /* Try built-in microcode first */ if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(path, use_pa); if (!(cp.data && cp.size)) - return 0; + return NULL; - intel_cpu_collect_info(&uci); + intel_cpu_collect_info(uci); - scan_microcode(cp.data, cp.size, &uci, true); - return 0; + return scan_microcode(cp.data, cp.size, uci); } +static struct microcode_intel *ucode_early_pa __initdata; + /* - * @res_patch, output: a pointer to the patch we found. + * Invoked from an early init call to save the microcode blob which was + * selected during early boot when mm was not usable. The microcode must be + * saved because initrd is going away. It's an early init call so the APs + * just can use the pointer and do not have to scan initrd/builtin firmware + * again. */ -static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) +static int __init save_microcode_from_cpio(void) { - static const char *path; - struct cpio_data cp; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - path = ucode_path; - use_pa = false; - } - - /* try built-in microcode first */ - if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(path, use_pa); - - if (!(cp.data && cp.size)) - return NULL; + struct microcode_intel *mc; - intel_cpu_collect_info(uci); + if (!ucode_early_pa) + return 0; - return scan_microcode(cp.data, cp.size, uci, false); + mc = __va((void *)ucode_early_pa); + save_microcode_patch(mc); + return 0; } +early_initcall(save_microcode_from_cpio); +/* Load microcode on BSP from CPIO */ void __init load_ucode_intel_bsp(void) { - struct microcode_intel *patch; struct ucode_cpu_info uci; - patch = __load_ucode_intel(&uci); - if (!patch) + uci.mc = get_ucode_from_cpio(&uci); + if (!uci.mc) return; - uci.mc = patch; + if (apply_microcode_early(&uci, true) != UCODE_UPDATED) + return; - apply_microcode_early(&uci, true); + if (IS_ENABLED(CONFIG_X86_64)) { + /* Store the physical address as KASLR happens after this. */ + ucode_early_pa = (struct microcode_intel *)__pa_nodebug(uci.mc); + } else { + struct microcode_intel **uce; + + /* Physical address pointer required for 32-bit */ + uce = (struct microcode_intel **)__pa_nodebug(&ucode_early_pa); + /* uci.mc is the physical address of the microcode blob */ + *uce = uci.mc; + } } +/* Load microcode on AP bringup */ void load_ucode_intel_ap(void) { - struct microcode_intel *patch, **iup; struct ucode_cpu_info uci; + /* Must use physical address on 32bit as paging is not yet enabled */ + uci.mc = ucode_patch_va; if (IS_ENABLED(CONFIG_X86_32)) - iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); - else - iup = &intel_ucode_patch; - - if (!*iup) { - patch = __load_ucode_intel(&uci); - if (!patch) - return; - - *iup = patch; - } - - uci.mc = *iup; + uci.mc = (struct microcode_intel *)__pa_nodebug(uci.mc); - apply_microcode_early(&uci, true); + if (uci.mc) + apply_microcode_early(&uci, true); } +/* Reload microcode on resume */ void reload_ucode_intel(void) { - struct ucode_cpu_info uci; - - intel_cpu_collect_info(&uci); + struct ucode_cpu_info uci = { .mc = ucode_patch_va, }; - uci.mc = intel_ucode_patch; - if (!uci.mc) - return; - - apply_microcode_early(&uci, false); + if (uci.mc) + apply_microcode_early(&uci, false); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) @@ -560,7 +541,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = intel_ucode_patch; + mc = ucode_patch_va; if (!mc) { mc = uci->mc; if (!mc) @@ -685,11 +666,11 @@ static enum ucode_state read_ucode_intel if (!new_mc) return UCODE_NFOUND; - vfree(uci->mc); - uci->mc = (struct microcode_intel *)new_mc; - /* Save for CPU hotplug */ - save_microcode_patch(new_mc, new_mc_size); + save_microcode_patch((struct microcode_intel *)new_mc); + uci->mc = ucode_patch_va; + + vfree(new_mc); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, cur_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -107,13 +107,11 @@ static inline void exit_amd_microcode(vo #ifdef CONFIG_CPU_SUP_INTEL void load_ucode_intel_bsp(void); void load_ucode_intel_ap(void); -int save_microcode_in_initrd_intel(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(void) { } static inline void load_ucode_intel_ap(void) { } -static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } static inline void reload_ucode_intel(void) { } static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } #endif /* !CONFIG_CPU_SUP_INTEL */ From patchwork Sat Aug 12 19:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134994 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1965798vqi; Sat, 12 Aug 2023 18:00:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGmAC4x7V5tFGJYfopsL7ZB9oleeXjdGaDQR83oXpXcnrXV4UYNwDjM1JoSmlryqF/y5hGp X-Received: by 2002:aa7:d84e:0:b0:523:c6fa:871d with SMTP id f14-20020aa7d84e000000b00523c6fa871dmr5553616eds.19.1691888414243; Sat, 12 Aug 2023 18:00:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691888414; cv=none; d=google.com; s=arc-20160816; b=k9PjcgCpjeaJrYeRfmNFTQ05xsZgXaLJfNcS65cF7LAEyxVImnZPD3mvI+gET7C/1Z VC3pkxRZ6p2T8dfiagM3t77x3ONXEjCjv6rncIf0irQ9En5NAcr7MQqtOqmVFja/SI1w 0rxVUBQw7bVouoOnUWdwET5HGDs5awjeUn8NEX2KTTn1TYrB3MvbMI1r7ArK26rgen6K JhiFChHes8tzThDkcflc6DuJIl0IkIQpBkkH5gA4IIS6kwhTNhYK2StZVb/oAhwq/ixI F3PoUFIuT4U00ho2XJrZgnopkSGCkq4ZIBOGgNYS9hJjAFZnO1HrxOHT76gdERo/PuuB 1uuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=+y22VMR8WT7f2YLl6Of8CzpgJMFOpBS1tGm9UJbVhvM=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=W9mwu0lgkxPyh/R4CSMAA7cyXy8hhw+lxvWYWyMFGO+ja5AP399UuB2i2G0BuSWjAd /OeNC2EvqvXN+MVsm8de+1UTMTBItvazSctbYIjplCX90CU49Kq0j1tospaQhsYzNxqN x/f58P2M5Kgbea/wpSEFD/jV6V6xQk0/3jj4Lrsfu4jp2D1zWvFvUrmyOn7hLOyQSZuD 0WZmfueE/xqH51dd9i5gIBIOca2cQq3ENhu3OBK4XrSDAgNCvLf+/u0HitZTaFR8oq2a TwrJd88LSwf2JD0x65kmLJsfz6i+AI5QDNl5JzLnb5eDL/2lcLbWdcvvQ9/2rw6soJQI vESA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3qkG7O9d; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=SAu5UDCd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c4-20020aa7df04000000b005254ea3a370si1171333edy.463.2023.08.12.17.59.50; Sat, 12 Aug 2023 18:00:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3qkG7O9d; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=SAu5UDCd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230314AbjHLUBf (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230449AbjHLUBQ (ORCPT ); Sat, 12 Aug 2023 16:01:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22AF035A0 for ; Sat, 12 Aug 2023 13:00:54 -0700 (PDT) Message-ID: <20230812195728.418426203@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870340; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+y22VMR8WT7f2YLl6Of8CzpgJMFOpBS1tGm9UJbVhvM=; b=3qkG7O9du49WCwiZWAE/U8r2Ob044whhIMYDue7i2qa1KaxhYg5JsWiA4nLTAcd92GcYyV TLQ89bLg+s8bYLIi0sixWqTcd3An2plDXov7FQ2LNIfzOakTb+DPa/k+a26vFJOAPOGKFK uWiaofo37Jujvjvh6u+RytfjYH2yWIFBDHiJklgbBqlgVta/m5PZzzBozDsFnNvdsg7FdN aF4Q6b553bYSP0ZnoChZPBRxy6vyO4jS4uNQnSP+ud75AHBC8Op4YWYctok3T/fo2vw+G4 fEh4X/Q505XEA651BQKu/WWucfUeKZwsxIYRncYhdYBR3MGP1QGu8fWEh7B2fQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870340; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+y22VMR8WT7f2YLl6Of8CzpgJMFOpBS1tGm9UJbVhvM=; b=SAu5UDCd3BfMexoasNfhtAHe1JuqVk2/ZLkMGc5RHxk3Rnx4fa+1QtmoZ981iQDkao+mGH G/OHdGSF9uceRxDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 15/37] x86/microcode/intel: Save the microcode only after a successful late-load References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:59 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774073585853487641 X-GMAIL-MSGID: 1774073585853487641 From: Thomas Gleixner There are situations where the late microcode is loaded into memory, but is not applied: 1) The rendevouz fails 2) The microcode is rejected by the CPUs If any of this happens then the pointer which was updated at firmware load time is stale and subsequent CPU hotplug operations either fail to update or create inconsistent microcode state. Save the loaded microcode in a separate pointer from with the late load is attempted and when successful, update the hotplug pointer accordingly via a new micrcode_ops callback. Remove the pointless fallback in the loader to a microcode pointer which is never populated. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 ++++ arch/x86/kernel/cpu/microcode/intel.c | 30 +++++++++++++++--------------- arch/x86/kernel/cpu/microcode/internal.h | 1 + 3 files changed, 20 insertions(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -443,6 +443,10 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + + if (microcode_ops->finalize_late_load) + microcode_ops->finalize_late_load(ret); + if (!ret) { pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -34,6 +34,7 @@ static const char ucode_path[] = "kernel /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; +static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -541,12 +542,9 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = ucode_patch_va; - if (!mc) { - mc = uci->mc; - if (!mc) - return UCODE_NFOUND; - } + mc = ucode_patch_late; + if (!mc) + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -666,15 +664,7 @@ static enum ucode_state read_ucode_intel if (!new_mc) return UCODE_NFOUND; - /* Save for CPU hotplug */ - save_microcode_patch((struct microcode_intel *)new_mc); - uci->mc = ucode_patch_va; - - vfree(new_mc); - - pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, cur_rev, uci->cpu_sig.rev); - + ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; } @@ -731,10 +721,20 @@ static enum ucode_state request_microcod return ret; } +static void finalize_late_load(int result) +{ + if (!result) + save_microcode_patch(ucode_patch_late); + + vfree(ucode_patch_late); + ucode_patch_late = NULL; +} + static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_intel, + .finalize_late_load = finalize_late_load, }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,6 +31,7 @@ struct microcode_ops { */ enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Sat Aug 12 19:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134937 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1883001vqi; Sat, 12 Aug 2023 13:25:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE34mL70GpMaE0xZxoJ6VctmOUO+k2HCJYJS+a+pOewYGom3FufY583aBfOBLvKVAfgAkGZ X-Received: by 2002:aa7:d8d8:0:b0:525:46b7:40f2 with SMTP id k24-20020aa7d8d8000000b0052546b740f2mr1474171eds.21.1691871915721; Sat, 12 Aug 2023 13:25:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691871915; cv=none; d=google.com; s=arc-20160816; b=K+M0SodVarFAksEqr311xq8BM2zeZLrDTNrYHJ2BGWAuq9T1DMVCKr2XCC6+aNy7ul PB5IYk1iNT9OcgRLfR9Kxm2gOViwUB+GHE0KqilIKlc7Vl/YuiFLTiS5dnGgxpuziS7N 6AvzweC6tjTq1/B+QJ92ihciRpU6HgaBG8Fuq91PSpYyub+CYu7fAoHhBdwtXwJGJxaM RDku4e52ocH6F7UtnPOtq96ctZv7PRjnAa+a3VOd05X7uFnk8Buhb1WS4mWN0Qlw0Rtf qAwRBtyI9AXZs1j1/UVchQwx92MsxMXWxoJ/OxCrDStqmsiI9+nDvFKz/F5tG4Vk01XH JcEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=hIX18dJsViRnFjmjnZoQ/63urhaUc4z36vhR8c6ivo4=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=egaFR7bxkDWrFaWMDDBfUvaDSPoJRMiG5eqhp48utLd2jT4akN92rhhao7n0YpKkaz Km0g4GC3Y4EQ1+BiDT0xWBE4XA2Po7MUqN59TlFN0N43beHjxJfOwJ0jrFPEpq4hJo+m 8pHn1DG0tCAYDAChxRcG42TUozEKJGjFIJChX/E3/jZV/ELdGk7YulAodLUe3VN0rjUU LY6xyA+E8oII8ab4wyLG73UP8LFEYLN44xviGoXxepJxHhIWAMHsOmZSWpJnKx8xdcEN JSnfOD0uCA60fZdUPVM1yftDsYfdqIwPRZNR8DOy43PPNEL4KtcS/6BQuVzmPbiyzOCA dq/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WQV3Bgtd; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d23-20020aa7d5d7000000b005234da35264si5399452eds.125.2023.08.12.13.24.51; Sat, 12 Aug 2023 13:25:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WQV3Bgtd; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbjHLUBi (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230452AbjHLUBQ (ORCPT ); Sat, 12 Aug 2023 16:01:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18615359D for ; Sat, 12 Aug 2023 13:00:54 -0700 (PDT) Message-ID: <20230812195728.475622148@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hIX18dJsViRnFjmjnZoQ/63urhaUc4z36vhR8c6ivo4=; b=WQV3BgtdOkoLTVcAG/nDZKVh7Rx9IKoBhWvB5SfAS+bJch1XpGSqKX6nrZJAv/AOfWz9Go 4w73Z9sqG3PoQPpL5u0PJ7vYB2QYfNYM8WIY3Vt3o88ojfgfbbJQ3J1+ezaxPqSReKCxsy 4IJRT7tKYzt9hTyWpMLYIwNIlGAHe9sTqN6Rp8Flt9wm9/DMNhhNT4KjCoUceYVTDgYSyz m7yScmc344zxgL/AJSmClNeRMETwyhJt1vs0sPXSHNOXrisXLBR+cazHu7YpgevXubRo+Q 84W8KGgzK7MrKzRyOXbDh7FbjewlWMzxJoV5FN+LYG7UNEibLfDe5afalMnLHQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hIX18dJsViRnFjmjnZoQ/63urhaUc4z36vhR8c6ivo4=; b=9jBVKS1KlN1sHwjGgPp/P84e8xNLLGKKkkAlRI1uRJRkyBQMAZl1xFrDLtOeSkmRMo9Qjs nea+YAmye3C8LhDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 16/37] x86/microcode/intel: Switch to kvmalloc() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:01 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774056285708693052 X-GMAIL-MSGID: 1774056285708693052 From: Thomas Gleixner Microcode blobs are getting larger and might soon reach the kmalloc() limit. Switch over kvmalloc(). 32-bit has to stay with kmalloc() as it needs physically contiguous memory because the early loading runs before paging is enabled, so there is a sanity check added to ensure that. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 55 +++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 23 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -243,7 +242,7 @@ EXPORT_SYMBOL_GPL(intel_microcode_sanity static void update_ucode_pointer(struct microcode_intel *mc) { - kfree(ucode_patch_va); + kvfree(ucode_patch_va); /* * Save the virtual address for early loading on 64bit @@ -257,13 +256,18 @@ static void update_ucode_pointer(struct static void save_microcode_patch(struct microcode_intel *patch) { - struct microcode_intel *mc; + unsigned int size = get_totalsize(&patch->hdr); + struct microcode_intel *mc = NULL; + + if (IS_ENABLED(CONFIG_X86_64)) + mc = kvmemdup(patch, size, GFP_KERNEL); + else + mc = kmemdup(patch, size, GFP_KERNEL); - mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); if (mc) update_ucode_pointer(mc); else - pr_err("Unable to allocate microcode memory\n"); + pr_err("Unable to allocate microcode memory size: %u\n", size); } /* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ @@ -610,36 +614,34 @@ static enum ucode_state read_ucode_intel if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) { pr_err("error! Truncated or inaccessible header in microcode data file\n"); - break; + goto fail; } mc_size = get_totalsize(&mc_header); if (mc_size < sizeof(mc_header)) { pr_err("error! Bad data in microcode data file (totalsize too small)\n"); - break; + goto fail; } - data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); - break; + goto fail; } /* For performance reasons, reuse mc area when possible */ if (!mc || mc_size > curr_mc_size) { - vfree(mc); - mc = vmalloc(mc_size); + kvfree(mc); + mc = kvmalloc(mc_size, GFP_KERNEL); if (!mc) - break; + goto fail; curr_mc_size = mc_size; } memcpy(mc, &mc_header, sizeof(mc_header)); data = mc + sizeof(mc_header); if (!copy_from_iter_full(data, data_size, iter) || - intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) { - break; - } + intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) + goto fail; if (cur_rev >= mc_header.rev) continue; @@ -647,25 +649,32 @@ static enum ucode_state read_ucode_intel if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - vfree(new_mc); + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; new_mc_size = mc_size; mc = NULL; } - vfree(mc); + if (iov_iter_count(iter)) + goto fail; - if (iov_iter_count(iter)) { - vfree(new_mc); - return UCODE_ERROR; + if (IS_ENABLED(CONFIG_X86_32) && new_mc && is_vmalloc_addr(new_mc)) { + pr_err("Microcode too large for 32-bit mode\n"); + goto fail; } + kvfree(mc); if (!new_mc) return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; + +fail: + kvfree(mc); + kvfree(new_mc); + return UCODE_ERROR; } static bool is_blacklisted(unsigned int cpu) @@ -724,9 +733,9 @@ static enum ucode_state request_microcod static void finalize_late_load(int result) { if (!result) - save_microcode_patch(ucode_patch_late); - - vfree(ucode_patch_late); + update_ucode_pointer(ucode_patch_late); + else + kvfree(ucode_patch_late); ucode_patch_late = NULL; } From patchwork Sat Aug 12 19:59:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134975 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1915377vqi; Sat, 12 Aug 2023 15:05:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHOE1Qo0ksyWVT1YA0yFoje5AJlGEaX0odzvybe7BV8hFEEock5Po3EYGgnXjuRf2TkYmzX X-Received: by 2002:a17:90a:5a01:b0:25d:d224:9fb9 with SMTP id b1-20020a17090a5a0100b0025dd2249fb9mr10132967pjd.24.1691877940020; Sat, 12 Aug 2023 15:05:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691877940; cv=none; d=google.com; s=arc-20160816; b=aIKg4cx53iGyk/ZLbln/Uk99SHw+e9rABy5ikYWwkt4eiVWZvNnqRm6GTyJAxm3bw8 anLn8fkA/GEBA5lQrgUJhiorhHBaz7KOX3+9j52I9kSuB0XxRkxH1pLZmv/anymRdKhU xfQUWBSmXKut31++mYqS4qW9BZiW3LDT+QKwsyQd4QCrgEmLQ2Ow2dpin/npuhCo85QX SdCyb75I1DljdZuJaRC8nOVRc09zL29ZoLJqRZhkPzWI8lkEwzQ94WP/UVEG48EnyVLU FeTu5RXAZOIDeEqD/wRd9l5d9Yr+w8sgLAH1R8dVJQMyTfC6EidtTgNHxxo9pTobqLf/ d19w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Qr4AlmFeVzuCfitdDfmm4zZT/Jw8jMZI8/qi5AcNsUA=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=qa0k8jZYO7ywgHb6RVOt327h6Wlxoasvf7p1EcEEY1oupslyZPziplRzurPHBhlCH9 hyx5dYU5eI7TkipfOoLyKzdOu7rj89FhywkyzR8nOz6xWI4f3vS51msbCdLvSZVuEdjm iVz3CE2B+zCpMuu5d6bYqicawvDabxVncHn2grZgBE85COOdCYcyjeHjP5ze6scOkzyW kPNdbBY8leLSM44egwyQzLQzrzfaVa5m3TqKZdhFJga22FOSIgxaTKuZzmDmW6OGKDmp LhCP0AJPqwqvL5aM1Jfs3bIN2o67iS79V3Z9FMlRkX+96+1pvoJMdNQx+oSQWSM0oTfz zeWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=D3X5bNrP; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ip4-20020a17090b314400b002639fe8ff6bsi7963184pjb.44.2023.08.12.15.05.21; Sat, 12 Aug 2023 15:05:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=D3X5bNrP; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231162AbjHLUBl (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230468AbjHLUBU (ORCPT ); Sat, 12 Aug 2023 16:01:20 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D9FC199A for ; Sat, 12 Aug 2023 13:00:57 -0700 (PDT) Message-ID: <20230812195728.533966298@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Qr4AlmFeVzuCfitdDfmm4zZT/Jw8jMZI8/qi5AcNsUA=; b=D3X5bNrP2YB3LcxBfXKEs4lfrbjgP1QPdxNsQGYohjGSxfB6JEjbWa/NvQZZP/MZ4BleF+ bAX31f/Vg4zyWQlvY44qJYyvIncdS2KLlUlAFN6UZk4MTKDQjyRfI2a2eMN6FYXKO0sJoW h/JiSVIWy3GyTKXRzc0lnw80G/3LKdmR8eLjkFBrMDHDGMlXJ6vkGqIvTkI/VzUIM4SOfB iqI68j4m/CCzZZYqccNIDyL160aS8qCUTpeySkGfBBb/RsWRKgEYJW5pQ16fuivClSRygJ 1aLv5oD62uagvdChEfaRyxQhtw68SiDGjOkUPQjgbrE4li9sP+I8SYyeeuZeNQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Qr4AlmFeVzuCfitdDfmm4zZT/Jw8jMZI8/qi5AcNsUA=; b=C7U9GR0+bssJUJTAReizej2oqUWnPXWAT1XKZjFv7/pIR67xHsk7EyIdszqPiXFr27iNgN 9Su4eZY5nUp7DyAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 17/37] x86/microcode/intel: Unify microcode apply() functions References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:02 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_PDS_OTHER_BAD_TLD,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062602613673552 X-GMAIL-MSGID: 1774062602613673552 Deduplicate the early and late apply() functions. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 106 +++++++++++----------------------- 1 file changed, 36 insertions(+), 70 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -353,12 +353,11 @@ static inline void print_ucode(int old_r } #endif -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static enum ucode_state apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev; + u32 rev; - mc = uci->mc; if (!mc) return UCODE_NFOUND; @@ -367,14 +366,12 @@ static enum ucode_state apply_microcode_ * operation - when the other hyperthread has updated the microcode * already. */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - uci->cpu_sig.rev = rev; + *cur_rev = intel_get_microcode_revision(); + if (*cur_rev >= mc->hdr.rev) { + uci->cpu_sig.rev = *cur_rev; return UCODE_OK; } - old_rev = rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -389,13 +386,23 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; uci->cpu_sig.rev = rev; + return UCODE_UPDATED; +} - if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); - else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) +{ + struct microcode_intel *mc = uci->mc; + enum ucode_state ret; + u32 cur_rev; - return UCODE_UPDATED; + ret = apply_microcode(uci, mc, &cur_rev); + if (ret == UCODE_UPDATED) { + if (early) + print_ucode(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + else + print_ucode_info(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + } + return ret; } static __init bool load_builtin_intel_microcode(struct cpio_data *cp) @@ -532,70 +539,29 @@ static int collect_cpu_info(int cpu_num, return 0; } -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc = ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; - - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() != cpu)) - return UCODE_ERROR; - - mc = ucode_patch_late; - if (!mc) - return UCODE_NFOUND; + u32 cur_rev; - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - ret = UCODE_OK; - goto out; - } - - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev = intel_get_microcode_revision(); - - if (rev != mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); + if (WARN_ON_ONCE(smp_processor_id() != cpu)) return UCODE_ERROR; - } - if (bsp && rev != prev_rev) { - pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + ret = apply_microcode(uci, mc, &cur_rev); + if (ret != UCODE_UPDATED && ret != UCODE_OK) + return ret; + + if (!cpu && uci->cpu_sig.rev != cur_rev) { + pr_info("Updated to revision 0x%x, date = %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev = rev; } - ret = UCODE_UPDATED; - -out: - uci->cpu_sig.rev = rev; - c->microcode = rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode = rev; + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; return ret; } @@ -742,7 +708,7 @@ static void finalize_late_load(int resul static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, }; From patchwork Sat Aug 12 19:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134942 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1889302vqi; Sat, 12 Aug 2023 13:46:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4nQFpYEtgPDblNA+Ge/IeIfCdl1+6sw+mrCxyBQvp6IzTboVUuVQJycIrWdcuVbIbZneO X-Received: by 2002:a05:6a00:1950:b0:687:42be:a240 with SMTP id s16-20020a056a00195000b0068742bea240mr5365381pfk.32.1691873172294; Sat, 12 Aug 2023 13:46:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691873172; cv=none; d=google.com; s=arc-20160816; b=qECoBYWTQuE12CPkH5Ix2pJE9ncPAnVxBWi/kHzzoBAXC5OfaZNRiG7IaKaKM9dDyj RZzj1x9boiYUVy3WtD23mJLP54mdaB6EV+fbckGzHjyFJLz2b/v+/NgVdRmY8s82bWR7 lSDXirzgCmJmBd86+hq1G6fh/bi2QH4Tw3vjiBdMcXfA3mnROEro2cAnzvchvhvUb0TA qSG0um+jb0uqSnmCDr3mm+sD8gj/25Wy/PFAFkzDc9Xw5PC81mELyQ3Ao6vmcFnYwkSv +FYBZZK1awsfevG4PLDzBul2QndrVe51o19UBwgLxNkO7Mc5CfJyaOXFTGzhwwAj/Uni Jzig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=bxbFiQ3H3oFNpJ5dbBKZzcn3JgdwiLcWWFsQ9BnK0wE=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=by6B42IivAWB6KRhy8OceJ18D+VHiAQ3eLsis5J2HgKdrXJ9uPym7sdGhgizFeoUJr wI8veWxdRKiO/Km/SAQybWmi8GWgdzS8kloSiTJyUBda9jQGm9YADZmYXEleHsLc7mxc Y22yaUmwHIkfHWXQM7xgh3Aap18edR8o9WIeQVgHnyOvb81AAMGNEa+ttRULTyPxqQ2y wwNoa4F0pwRh5psrjV4yAOyIJXKMs/sIySy3Wz37RZGN5jGiy9CQHjRPpMZfuqb7KITB DLLeJAtVygPnmR0xXC1xVWe6vztquawHEYmppFCwgpd1HeRj5Bf5SPOMgs2BCjYT2GG4 YmdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JMHfJV1P; dkim=neutral (no key) header.i=@linutronix.de header.b=4N7XRWpV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ck14-20020a056a00328e00b00687546abaf6si5332176pfb.195.2023.08.12.13.45.59; Sat, 12 Aug 2023 13:46:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JMHfJV1P; dkim=neutral (no key) header.i=@linutronix.de header.b=4N7XRWpV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230405AbjHLUBr (ORCPT + 99 others); Sat, 12 Aug 2023 16:01:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbjHLUBW (ORCPT ); Sat, 12 Aug 2023 16:01:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 294032106 for ; Sat, 12 Aug 2023 13:00:59 -0700 (PDT) Message-ID: <20230812195728.592367910@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870345; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bxbFiQ3H3oFNpJ5dbBKZzcn3JgdwiLcWWFsQ9BnK0wE=; b=JMHfJV1Piw2S4Z5oLeyTooqyb016gvTSzRtHZT3aDKqty3SWzrjZf2giLB6sQiF0egE5PT Tnb1fYeK3HMHDubMXeR6zR7MDRq3xo7lbTAXUKw8dyV0tBsYp2VwN/QEdI9IEceLqoOvMv w5IncR7MkXV1vzTNIhu4RS7WRnf2zU/PY8BYnG+dNwBxJtRdmwaBF9nF1XBHsrWLC0Pv8Q O4OeFs6EFgAl01QrzVvzmR083negnCxil0mB+YwhcsTyzY0TDYJK1CG6CkiWFqgaDCKaKE UUdHPhMmoPCd/CFqofLz535Aq+kPhohsTX8m3x8zKw7JddIa0Ib4fH8sHEjEYg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870345; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bxbFiQ3H3oFNpJ5dbBKZzcn3JgdwiLcWWFsQ9BnK0wE=; b=4N7XRWpVIiWiwbJW1wg0FLwp1DK+gbjcJiNUWIKheJramm+eXDZDu4mPqiQEa6InbhxVoJ PZns9WI18LXxXCDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 18/37] x86/microcode/intel: Rework intel_cpu_collect_info() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:04 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774057603385886894 X-GMAIL-MSGID: 1774057603385886894 Nothing needs struct ucode_cpu_info. Make it take struct cpu_signature, let it return a boolean and simplify the implementation. Rename it now that the silly name clash with collect_cpu_info() is gone. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/include/asm/cpu.h | 4 +-- arch/x86/kernel/cpu/microcode/intel.c | 39 ++++++++++------------------------ drivers/platform/x86/intel/ifs/load.c | 8 ++---- 3 files changed, 17 insertions(+), 34 deletions(-) --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -73,9 +73,9 @@ static inline void init_ia32_feat_ctl(st extern __noendbr void cet_disable(void); -struct ucode_cpu_info; +struct cpu_signature; -int intel_cpu_collect_info(struct ucode_cpu_info *uci); +void intel_collect_cpu_info(struct cpu_signature *sig); static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, unsigned int s2, unsigned int p2) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -66,36 +66,21 @@ static inline unsigned int exttable_size return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } -int intel_cpu_collect_info(struct ucode_cpu_info *uci) +void intel_collect_cpu_info(struct cpu_signature *sig) { - unsigned int val[2]; - unsigned int family, model; - struct cpu_signature csig = { 0 }; - unsigned int eax, ebx, ecx, edx; + sig->sig = cpuid_eax(1); + sig->pf = 0; + sig->rev = intel_get_microcode_revision(); - memset(uci, 0, sizeof(*uci)); + if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + unsigned int val[2]; - eax = 0x00000001; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - csig.sig = eax; - - family = x86_family(eax); - model = x86_model(eax); - - if (model >= 5 || family > 6) { /* get processor flags from MSR 0x17 */ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig.pf = 1 << ((val[1] >> 18) & 7); + sig->pf = 1 << ((val[1] >> 18) & 7); } - - csig.rev = intel_get_microcode_revision(); - - uci->cpu_sig = csig; - - return 0; } -EXPORT_SYMBOL_GPL(intel_cpu_collect_info); +EXPORT_SYMBOL_GPL(intel_collect_cpu_info); /* * Returns 1 if update has been found, 0 otherwise. @@ -318,11 +303,11 @@ static int early_old_rev; */ void show_ucode_info_early(void) { - struct ucode_cpu_info uci; + struct cpu_signature sig; if (delay_ucode_info) { - intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + intel_collect_cpu_info(&sig); + print_ucode_info(early_old_rev, sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -444,7 +429,7 @@ static __init struct microcode_intel *ge if (!(cp.data && cp.size)) return NULL; - intel_cpu_collect_info(uci); + intel_collect_cpu_info(&uci->cpu_sig); return scan_microcode(cp.data, cp.size, uci); } --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -227,7 +227,7 @@ static int scan_chunks_sanity_check(stru static int image_sanity_check(struct device *dev, const struct microcode_header_intel *data) { - struct ucode_cpu_info uci; + struct cpu_signature sig; /* Provide a specific error message when loading an older/unsupported image */ if (data->hdrver != MC_HEADER_TYPE_IFS) { @@ -240,11 +240,9 @@ static int image_sanity_check(struct dev return -EINVAL; } - intel_cpu_collect_info(&uci); + intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, - uci.cpu_sig.sig, - uci.cpu_sig.pf)) { + if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Sat Aug 12 19:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134953 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1898927vqi; Sat, 12 Aug 2023 14:15:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFqGsxmeRyY6aWU0UrvlrZbZ/LhLXCBFhci8Q4ziDsKUTEmhEL0i9uSw/3gGSoKUX+HQCJm X-Received: by 2002:a05:6a20:1447:b0:12f:eb74:72b6 with SMTP id a7-20020a056a20144700b0012feb7472b6mr5085706pzi.60.1691874901570; Sat, 12 Aug 2023 14:15:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691874901; cv=none; d=google.com; s=arc-20160816; b=t+SFsPC0px8VlqjJUyMgIxeM/vWWXiLUIXlUfFOVbeEvmaqqxu73xi17rOgLzuT3Y/ RJS4JQ5P2009l6ulby1kIhWFp5QWbBEQZkjNPIGEkWujAQ+mzXucUeqmyuOqMFoPoafo ewTdCZIB9jbsXHNxAUgMb0A9hBMTtKFtW0tSF+RZA23DAG6LHSAmMW6Cewps76dLldMT gMZ9X3nl38RLL5UmxxV6THstr24cOJgbvcbTANV8LsbNUMk1oi385cTf00lOmIwJWUiZ firWLQDKPH7WD/BN0RL/bd5YNyWkhGeTcrp0/plSfziemMA2k2ccwmYd8RwDULk1ZMFp 0uBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=GDewIFngkCI+5WnVcXevrKcgDXFsMW2Rc1mq3io3ymU=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=r3+sbM+yM2b4Y5SqEnaR5EmMxGLItaeFvc0aITK8IJ0egjOhRVnAf25MA9a95ri0Er yWW3QXk9NFMlngA+3DjVcH5UY82Tp37C8Y5zmy/mpdsUbDWww1kcft5AYjlYOaNb/kBH O6IfZv6F1qvG4xz5tMqcyIcms7RNijkGblwZfRV5zXtF16SYRI4PWalC0GzUlb0+i06s Oq59F0me9UxVin/1JRz0WGX3z2CA16kEAQobKtOfeCYw1SnToyUueoP6u4KsXQqwY5R8 GBXd6J6VsXw/JUoTZzIIVCx4QPCefzqFlYNdDrkjnOpGJ6Vttdd1owUlNUDrGfNVe+o/ 2AbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="SzDZ/hMv"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=ADY0IDxh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 81-20020a630154000000b0055b12581c75si5294958pgb.675.2023.08.12.14.14.49; Sat, 12 Aug 2023 14:15:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="SzDZ/hMv"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=ADY0IDxh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231167AbjHLUG2 (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbjHLUG0 (ORCPT ); Sat, 12 Aug 2023 16:06:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57EBB1BD8 for ; Sat, 12 Aug 2023 13:05:59 -0700 (PDT) Message-ID: <20230812195728.649375687@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GDewIFngkCI+5WnVcXevrKcgDXFsMW2Rc1mq3io3ymU=; b=SzDZ/hMvJh/0Z3hzYNfiQofVDznOJ5EAz6wODCsS0ZcL/xbh6IACQFM76wJCpxEnFQ5UyQ KTH+DdnzGOJwklFpJP65q1JGtdf46PYLUpIht4rT4dpfyayX7zEHSsicsN6mUzQS0XJuk+ HqCDXjtUnAk+9xvIsbcPLlvXlj9aqTrLudUH+wecGyS5Sg306WPEJqlYLPO24J3kr7d3ug HhT8IEokz3ovZAefQ5hdSk4LvVoVED7CC0XyrcUr1ofkQjnbb7ZQzxbExkxD5p/AJMO6ee YEaWIUPQmvEjv6SQbQZkc9eF3EWjbNDTkfHfqDWbm3ddTaCKaElfDMF9v9EJ4A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GDewIFngkCI+5WnVcXevrKcgDXFsMW2Rc1mq3io3ymU=; b=ADY0IDxh4OJy63obIP9ZvEn7D3GClq2W+0PU7mXfrmB4c1RyipkAOEEk9C/ysDaeDchW+1 OdSJmMPhi432vgCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 19/37] x86/microcode/intel: Reuse intel_cpu_collect_info() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:06 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774059416863578717 X-GMAIL-MSGID: 1774059416863578717 No point for an almost duplicate function. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/intel.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -506,21 +506,7 @@ void reload_ucode_intel(void) static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { - struct cpuinfo_x86 *c = &cpu_data(cpu_num); - unsigned int val[2]; - - memset(csig, 0, sizeof(*csig)); - - csig->sig = cpuid_eax(0x00000001); - - if ((c->x86_model >= 5) || (c->x86 > 6)) { - /* get processor flags from MSR 0x17 */ - rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig->pf = 1 << ((val[1] >> 18) & 7); - } - - csig->rev = c->microcode; - + intel_collect_cpu_info(csig); return 0; } From patchwork Sat Aug 12 19:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134968 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904950vqi; Sat, 12 Aug 2023 14:33:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEdWWpqpRJTaN4C0TFL28GDyDRMTLVLeASGMrqY3exohC0Elr5t8FOqucrV0krcR1w4DKMJ X-Received: by 2002:a05:6a00:1996:b0:687:9909:3c78 with SMTP id d22-20020a056a00199600b0068799093c78mr6861253pfl.0.1691876012304; Sat, 12 Aug 2023 14:33:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876012; cv=none; d=google.com; s=arc-20160816; b=o14ZDjjmJzGA8768Esqg/77pEywZhm9QIUPAw2VwJZEuDwZMWKaPkV/ZapmxbtAToJ 3ZoYTGVeD2B9XRne/UJEEYnS9iqezJymszMjOq8/lYqsphru1+/xodYGh/S7aw7cGqFc tRz8QAGNPMZmksfQTXQRr8xoS6Y93MN1C+ACRw9HVRLaBjnohB+QZs3ziMPCJ0MEFqy7 lEyZbBANpl5lxhYzb/j6Dqt63c92OrWrlDeZr7wu0hOVj4BGcELqEFOhlYJwKRhlfMGK FLAEo0A5zMhmHCsmn9GW75pla1AkGE2kq2yZbG0CNGQSIotJ2fXUwKU9g4Kjs/fCqeZS 0pWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=rDI1ykgeaxeUMJlpq0aKo/7WMXntCc7/NJHkM9TFISc=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=byBWULI3wHY5naYPy+hNAZNOSecYULR3aB89YYS8s+8uBg2WQm+h8cMpQoyI+m7wbF rNqbroHK3oXtqqmfdWyyhxXsr3YCjnwz6tLQcX3xONQ+qQIF6UDOsZ/3ugK7z56U9Xgz 5S4r5hw/MJRZ/mJzVet+3x2PquSsZrA5mdbKhYiywfhQSuo9d8z9ZjIe2/9a6HVwonlU k7EO3iLyiGNlcqXB00cn2WuXQgSygywx/VuaWTRO9iyF7ukyNW50It62BzHYMjTjWrUP 2p837YAPuP0ZGpXzgrARRhD425RfigTReYfa6OYvLCK0akaWMB2WYdlTdmXWWsyXBvtB Gt9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ESEHMgas; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=LWFB0AQX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id fj11-20020a056a003a0b00b006875cd0ce87si5544426pfb.396.2023.08.12.14.33.19; Sat, 12 Aug 2023 14:33:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ESEHMgas; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=LWFB0AQX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231161AbjHLUGa (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230523AbjHLUG1 (ORCPT ); Sat, 12 Aug 2023 16:06:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D92291BD1 for ; Sat, 12 Aug 2023 13:05:59 -0700 (PDT) Message-ID: <20230812195728.708313227@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870348; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rDI1ykgeaxeUMJlpq0aKo/7WMXntCc7/NJHkM9TFISc=; b=ESEHMgas6zDqDY1Q70SV3AEf1kfnaElwEZ7nZVWCQ2jwa+IUQMfl1AJmpWBsKVA/CAO3qx +65QuC0aPiePqdwsKp0Nje52wp+8XJ/VGyPc3LtxBUyMzicyAP/5m95if+ww2FIWkuhT7A ALJFmn3HgVT2vB+cBUCTSrBChYCMFIHxxJVSgPnMgsukOgcg1gRDHo+SwUI6sj1Bhoca06 +JAGWDQCmwLhOxPcgr9HCUOMP5tNxL4Pgli+NStl99Ub8hnrycayEMfBAnktVhjILQ95I/ +7ZTQ2V5mJ427wOes8RFCm86u+u3g2uLwRv9BvIq7ILg/c4LhDabHu8eHOW1OQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870348; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rDI1ykgeaxeUMJlpq0aKo/7WMXntCc7/NJHkM9TFISc=; b=LWFB0AQXcLWH4U6txqX5zCIBRJOxtLsNjIsAHcf0vltZm1PZBY/VM3UFXL8zJ0sPOpmZEM e9vD35QS7SIJkyBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 20/37] x86/microcode/intel: Rework intel_find_matching_signature() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:07 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060581280116344 X-GMAIL-MSGID: 1774060581280116344 Take a cpu_signature argument and work from there. Move the match() helper next to the callsite as there is no point for having it in a header. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/include/asm/cpu.h | 16 +--------------- arch/x86/kernel/cpu/microcode/intel.c | 31 +++++++++++++++++++------------ drivers/platform/x86/intel/ifs/load.c | 2 +- 3 files changed, 21 insertions(+), 28 deletions(-) --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -77,22 +77,8 @@ struct cpu_signature; void intel_collect_cpu_info(struct cpu_signature *sig); -static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, - unsigned int s2, unsigned int p2) -{ - if (s1 != s2) - return false; - - /* Processor flags are either both 0 ... */ - if (!p1 && !p2) - return true; - - /* ... or they intersect. */ - return p1 & p2; -} - extern u64 x86_read_arch_cap_msr(void); -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf); +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig); int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type); extern struct cpumask cpus_stop_mask; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -82,29 +82,36 @@ void intel_collect_cpu_info(struct cpu_s } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) +static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2, + unsigned int pf2) +{ + if (s1->sig != sig2) + return false; + + /* Processor flags are either both 0 or they intersect. */ + return ((!s1->pf && !pf2) || (s1->pf & pf2)); +} + +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig) { struct microcode_header_intel *mc_hdr = mc; - struct extended_sigtable *ext_hdr; struct extended_signature *ext_sig; + struct extended_sigtable *ext_hdr; int i; - if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) - return 1; + if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf)) + return true; /* Look for ext. headers: */ if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) - return 0; + return false; ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { - if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) - return 1; + if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf)) + return true; ext_sig++; } return 0; @@ -272,7 +279,7 @@ static __init struct microcode_intel *sc intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(data, &uci->cpu_sig)) continue; /* Check whether there is newer microcode */ @@ -583,7 +590,7 @@ static enum ucode_state read_ucode_intel if (cur_rev >= mc_header.rev) continue; - if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; kvfree(new_mc); --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -242,7 +242,7 @@ static int image_sanity_check(struct dev intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { + if (!intel_find_matching_signature((void *)data, &sig)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Sat Aug 12 19:59:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134979 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1915994vqi; Sat, 12 Aug 2023 15:07:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENSq5ALwPOY7+N+H+kfqrDk77Ur0mla4DlwsoEOiAXEdVUNWgv4jlOfN0dyUNfH1/o3akZ X-Received: by 2002:a05:6a20:6a2c:b0:134:6839:c497 with SMTP id p44-20020a056a206a2c00b001346839c497mr5503468pzk.11.1691878033840; Sat, 12 Aug 2023 15:07:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691878033; cv=none; d=google.com; s=arc-20160816; b=oti1gfivPCRzs2loHBSPK7ti63Mx3WQUVDkRbg/i1wf1hZAZZhU8EhDyYIi6SVV/nq stO7jqqthaVYhzXI9Bhd5AOJ4jV//u3Qupw08BD6v5bL6pYjVNJc/9HL7QqcJiDGWqwy fOR2sBDtlZeOEHLFvGiVkPzyE3nDUzaDDLaEhgMT1RythvX5ZuRZ274JSgavNzq3UL/C bgGq2Q8AoZQATMv0k9ju8E4VudcM5uJ+BqT9nqx/v3J83c+mqJJ/njxbDXOxOawnnVQn AyozLUXZ8rF/Z62+MFf0gb33i+38nq9Nd6rMPAVWkvVeheJYlcWb1t9Rx8DWqxQvXvwD MTXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=kkIW+v+zNIk9lQpoyroVUgRr0ogOwnyVqvNr/VLjf7s=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=fdsKXmNlkflBWf84VYeW09y70GSWdpVfAj6gg1+nDEzASCofUOQPX0tjrxVPeRAfRF C4FlxaWUbEKGxvGUXbj++ZruuDqVSZjm5CwM0il5D63GYyGV89koEaqkii0NlixCs9qS XNCwh3HaTaqWK5lA2MEW7ou+YkwMLjSH61ELxvNEX9iuYYysF4HKkQNmjQcGTQRNCJUI nozJ6dGL+s9YFzBvSH2E2FFv7km2rJ5J5FoRUQXNRy0YgH92rXZzf4sXa3Qz1nY7bnCu 9aVrr/Tx+LV3xpGyo8pSY6cVsYOpTRsVjWd4bHV+F1pnrwNqiNjVoOC6UpZqENh/dT3Y FbHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=zuNXQTul; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t184-20020a6381c1000000b0055fdd303743si5398875pgd.719.2023.08.12.15.07.00; Sat, 12 Aug 2023 15:07:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=zuNXQTul; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230499AbjHLUCa (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbjHLUCX (ORCPT ); Sat, 12 Aug 2023 16:02:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A37E63584 for ; Sat, 12 Aug 2023 13:01:57 -0700 (PDT) Message-ID: <20230812195728.767559362@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kkIW+v+zNIk9lQpoyroVUgRr0ogOwnyVqvNr/VLjf7s=; b=zuNXQTulA8DtnMFk1kcH3noS0gOIC12+/0PSST/h+Rmc2YczU2Q5O471jiL/xl4AJqkClu OXONrmERT89Cs94ZdPx8qdBeNSAM4uzjLa3oetmdG0wLpCxONwYB9G/+Utwe2VaFFTfLDf 2PN0kIxBtnhoKAEaKQrPNktdHGrgdN53W2tjtf8P/6TRfBLV7RU+GS0LK3hpkYtW4cjPaq peX8HMUcixXza48s/EyCMDDk1QLkaHfi831eir3+XHJOsMwiQGsAklS4BTkEvjdny9rRXt 9Z21iRJNiEs6qEJVIcKWakKhE4makNymmMGuDwxG+M8ogV/xVZI21a9+XKFGDQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kkIW+v+zNIk9lQpoyroVUgRr0ogOwnyVqvNr/VLjf7s=; b=oKOr19vBE0Rbk5OMlHnMPH7YRqTr0xsB63QVZRC/CVdLuXJZT5ZU9VnFkNr04H9EWJ+bcW aV2fjO0J8UNvNkCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 21/37] x86/microcode/amd: Read revision from hardware in collect_cpu_info_amd() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:09 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062700967263412 X-GMAIL-MSGID: 1774062700967263412 Prepare to decrapify the core initialization logic which invokes microcode_ops::apply_microcode() several times just to set cpu_data::microcode. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -673,12 +673,12 @@ void reload_ucode_amd(unsigned int cpu) static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { - struct cpuinfo_x86 *c = &cpu_data(cpu); struct ucode_cpu_info *uci = ucode_cpu_info + cpu; + u32 dummy __always_unused; struct ucode_patch *p; csig->sig = cpuid_eax(0x00000001); - csig->rev = c->microcode; + rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); /* * a patch could have been loaded early, set uci->mc so that From patchwork Sat Aug 12 19:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134969 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1905175vqi; Sat, 12 Aug 2023 14:34:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHK9UqzpOwwyoEJ2MU1KRViKMXdVo2T0EmA32IckWml2OyV5B++FYS5HtiEn6GvNXdXLaTI X-Received: by 2002:a17:902:d4c3:b0:1b6:b703:36f8 with SMTP id o3-20020a170902d4c300b001b6b70336f8mr7191042plg.25.1691876062281; Sat, 12 Aug 2023 14:34:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876062; cv=none; d=google.com; s=arc-20160816; b=AnBzs4vTFtMwEN0k/umk8d0px5vnHjuuzntOrwFVd81eLOthHommf3EQTSt8Usb1m5 SGBZsIiTikq9E/7Yi74G9xD6BjxlecqdIL1x6ELImEgowoj7Ow0RFTTEXRYNmfQaSFBj 6S9/LhR7EQNJx1VgM7Vitw9vMYuq2WZ83lFkPWZEXaLQKd0Hzcupl5QQTHCUMT7S0n/E 3+3Rm865qf9kqjBrR7nJgS1EBqYZAotwitNLmlSf4TbgKy/xG7GlnzrbsPe7pxkywnB6 aQ2NNEq8oXtRyajOIMkPmt2ajCaTET/wUYZvglVduwswB0L/z19a2hHAcw1BMIZagRzm q+wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=D7ZrdA6sXE8GlpN8vSC6yf/zxBb4RukOrJuRRxzbufg=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=yDd2Y4pB7E5VAMza2S+FNwwesrEu/rh0gDz1mnq71+DCg9u2aB16oSaT8ThMNfdpev s1WpjX+r4T2OBhxXhdjCX/eux3DvVg0PMKgf0lYNOn6Fk762pLSfQpBuLq5VbtDiv3y+ MnYUsEPKXXwgq6GHVVUbFmbIqEfPTTiix1BPCi0VZAA3Ih4lbmLCAOVPZikUZCPyUnHw f+a1Nq9XO8Ez6xjlL6+me8FvkI1wPwWEfd9iRbMqm0uhzHhsXRRXpQtlzsygIAW4fqZy rHmnad+WrzlNI6enwgw7WoW08+jKsrtX9VdeYGaCKdiTM4OIYNWKCnAMSdWQlqyr9+VC O/lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=jBFj0txS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="G/gQKPU1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n16-20020a170902f61000b001baff05d890si5467252plg.313.2023.08.12.14.34.09; Sat, 12 Aug 2023 14:34:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=jBFj0txS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="G/gQKPU1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230417AbjHLUCE (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230452AbjHLUBw (ORCPT ); Sat, 12 Aug 2023 16:01:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D42A02729 for ; Sat, 12 Aug 2023 13:01:24 -0700 (PDT) Message-ID: <20230812195728.824553325@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870351; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=D7ZrdA6sXE8GlpN8vSC6yf/zxBb4RukOrJuRRxzbufg=; b=jBFj0txSmp09zpQTI0doP2s65siBwVk5RGfmdK0e4lZY9ag4awjSXqUx66UTzbqPCixHLz 1xv6XkN2AE0dIXQoNiiXqg9sdkZFtFxqnlnwquIRv91Nie0ExsSef+KTF9wtd4WZIRNyIu 6/yMI6KIidZTXkjG4fQ2kU2p4A3TEXy6ufVM4UwMuDxXL5oZHX8/e6NCL+4O2Sfj+0SJIn jdbd7kx1+yZ47YOh9xras2MfwVBq4aaipc3lrtewdt7bLxi7r3LBTKyiHGNOWyF69igx/E 2Nzr2ks+QbQ2AB6pdyxkNywSgV+TQ/YeviciJllVd5ydwOE7/hKwZP5xRhDmNQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870351; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=D7ZrdA6sXE8GlpN8vSC6yf/zxBb4RukOrJuRRxzbufg=; b=G/gQKPU1/fqDFtGqYTVAv7UTEjNS0OhfNuBqYI6UT9i3429kIx28CIqn9bRfAztlGC/1Lp SUijy4Ly3SiAePDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 22/37] x86/microcode: Remove pointless apply() invocation References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:10 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060634232103986 X-GMAIL-MSGID: 1774060634232103986 Microcode is applied on the APs during early bringup. There is no point in trying to apply the microcode again during the hotplug operations and neither at the point where the microcode device is initialized. Collect CPU info and microcode revision in setup_online_cpu() for now. This will move to the CPU hotplug callback in the next step. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 34 ++++++---------------------------- include/linux/cpuhotplug.h | 1 - 2 files changed, 6 insertions(+), 29 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -533,17 +533,6 @@ static void microcode_fini_cpu(int cpu) microcode_ops->microcode_fini_cpu(cpu); } -static enum ucode_state microcode_init_cpu(int cpu) -{ - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - - return microcode_ops->apply_microcode(cpu); -} - /** * microcode_bsp_resume - Update boot CPU microcode during resume. */ @@ -562,15 +551,6 @@ static struct syscore_ops mc_syscore_ops .resume = microcode_bsp_resume, }; -static int mc_cpu_starting(unsigned int cpu) -{ - enum ucode_state err = microcode_ops->apply_microcode(cpu); - - pr_debug("%s: CPU%d, err: %d\n", __func__, cpu, err); - - return err == UCODE_ERROR; -} - static int mc_cpu_online(unsigned int cpu) { struct device *dev = get_cpu_device(cpu); @@ -598,14 +578,14 @@ static int mc_cpu_down_prep(unsigned int static void setup_online_cpu(struct work_struct *work) { int cpu = smp_processor_id(); - enum ucode_state err; + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - err = microcode_init_cpu(cpu); - if (err == UCODE_ERROR) { - pr_err("Error applying microcode on CPU%d\n", cpu); - return; - } + memset(uci, 0, sizeof(*uci)); + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + this_cpu_write(cpu_info.microcode, uci->cpu_sig.rev); + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; mc_cpu_online(cpu); } @@ -658,8 +638,6 @@ static int __init microcode_init(void) schedule_on_each_cpu(setup_online_cpu); register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting", - mc_cpu_starting, NULL); cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -156,7 +156,6 @@ enum cpuhp_state { CPUHP_AP_IRQ_LOONGARCH_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, - CPUHP_AP_MICROCODE_LOADER, CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, CPUHP_AP_PERF_X86_STARTING, CPUHP_AP_PERF_X86_AMD_IBS_STARTING, From patchwork Sat Aug 12 19:59:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134981 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1916859vqi; Sat, 12 Aug 2023 15:09:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGZ/agGhY6uwUkfEApZF1gFynswwswO9H4z27oLLPNzRTeAXl4JhS5Tq4SwHSS4pd8rak5 X-Received: by 2002:a05:6870:9728:b0:1b0:649f:e68a with SMTP id n40-20020a056870972800b001b0649fe68amr6560616oaq.25.1691878193909; Sat, 12 Aug 2023 15:09:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691878193; cv=none; d=google.com; s=arc-20160816; b=wCErLBh70t8jlaND1POLcctcMJHbR/yAFsdjY2blRrrP4BCpgUaET/08q/by+vUzSM rvBt9tJSsp1WBAUFw0bzSVHonlXlNL4WLcTfukxGhQcDMMshkxNtngqymixdpJqdOdZ+ /4LSYySKR0gg2gmRi0wVT+NbAjF+JGBabhAmnK2+Joj3M+jzxf3dO4EFdJet8xpGWyoc KOXCxR/gbClJduU++pg+CITnpnn9ltLnWKvNCRSeSVWfO0knfX800dGvzJo1BD7NUJUa 9zDEp3VSmhzatqMIRGrfzKPxapu7FWLUSqW6nVc3vfnv8gOrq3xOctAh8vfZkb1tt5xM gMbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=l6wRx6fDuLz7AVhgf50kqWA5bfrKXDckgGTayzMQhXA=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=Lp83Dfj9ZUiqPYWaEfzDi4sxHg3LPjU642GgaSqm686rbvxkXc/fUJMehhCl2TXrEf sqOAjbVoFC2d4jmXhJw70Ik8AGC2B/jq63iZDbA4oqUBJ1MAKxL28UO/1pgGtThCXi60 durI+5ACw8tOOjCUCgB3E2T4M9TvJJrMVQg9Qd+abCyE3vzvKmBV30GJe/dY9I7y1gsU Anb9oclbcYE9IhMZFijFZD0DXOXTBias4qNt96v38GwbqCVVVyvPXbt7UFwNdZKbps3Q qE2isoR2E8yruUbifynrm9kO0PnSa5344sVkHdB31duquuvIGDeKoZod/yQ9ak6CgpTi 9jfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=h1xfnmqD; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=B1Qz+4iK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e10-20020a170902f10a00b001bbcb3d9265si5196787plb.68.2023.08.12.15.09.40; Sat, 12 Aug 2023 15:09:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=h1xfnmqD; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=B1Qz+4iK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231197AbjHLUGc (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231175AbjHLUG2 (ORCPT ); Sat, 12 Aug 2023 16:06:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D23521993 for ; Sat, 12 Aug 2023 13:06:02 -0700 (PDT) Message-ID: <20230812195728.881571946@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=l6wRx6fDuLz7AVhgf50kqWA5bfrKXDckgGTayzMQhXA=; b=h1xfnmqDfKHIVcm23sIPOdlKRTiWnkdP52LkPZek4v4EkEUdPRh4K+UHkrYiVpj1Oyfk+9 7lTaH6Y7akEzB2X0a6cYazkCCfnqhxgfxd8iSyO936UU2m6/0Xrin1bWp460AiRuTJkqmt EOxu660RTkGpaMF4LfQUwCkcNEszuUiWzqqNsT7SVHMdNGIDFvWrmP3fb2+1i5EbMUy+BH jfEgJ1DQDtqx1se/2UGw0cc6NsArcXLEN1x5536up9WMdlmIdmq6Tg/nNII3Uph9ap3PzF wcrA2SlFYlnuZr0pdnHBvwg2nUoq9JDh8PsOTb34eWDU2TEXrx3wLfgAh3B5NA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=l6wRx6fDuLz7AVhgf50kqWA5bfrKXDckgGTayzMQhXA=; b=B1Qz+4iKBvJZiGkp3POPTyyo0xidh1HdSmIC41F5pPyf5C6ho4QsmpRwYtzI2+LQo7LRZq CKVisDdsTlaqi8CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 23/37] x86/microcode: Get rid of the schedule work indirection References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:12 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062869142676180 X-GMAIL-MSGID: 1774062869142676180 Scheduling work on all CPUs to collect the microcode information is just another extra step for no value. Let the CPU hotplug callback registration do it. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -553,8 +553,15 @@ static struct syscore_ops mc_syscore_ops static int mc_cpu_online(unsigned int cpu) { + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; struct device *dev = get_cpu_device(cpu); + memset(uci, 0, sizeof(*uci)); + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + this_cpu_write(cpu_info.microcode, uci->cpu_sig.rev); + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; + if (sysfs_create_group(&dev->kobj, &mc_attr_group)) pr_err("Failed to create group for CPU%d\n", cpu); return 0; @@ -575,20 +582,6 @@ static int mc_cpu_down_prep(unsigned int return 0; } -static void setup_online_cpu(struct work_struct *work) -{ - int cpu = smp_processor_id(); - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - this_cpu_write(cpu_info.microcode, uci->cpu_sig.rev); - if (!cpu) - boot_cpu_data.microcode = uci->cpu_sig.rev; - mc_cpu_online(cpu); -} - static struct attribute *cpu_root_microcode_attrs[] = { #ifdef CONFIG_MICROCODE_LATE_LOADING &dev_attr_reload.attr, @@ -634,12 +627,9 @@ static int __init microcode_init(void) } } - /* Do per-CPU setup */ - schedule_on_each_cpu(setup_online_cpu); - register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", - mc_cpu_online, mc_cpu_down_prep); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", + mc_cpu_online, mc_cpu_down_prep); pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); From patchwork Sat Aug 12 19:59:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134950 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1896751vqi; Sat, 12 Aug 2023 14:09:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEA2Xh1jIvEeP5862gQWywU6aRyX7JlvCaydvqOEWeahAdNHnROn+TQ1+iOAFpmNnnawVUb X-Received: by 2002:a17:902:e809:b0:1bc:8fca:9d59 with SMTP id u9-20020a170902e80900b001bc8fca9d59mr5673004plg.29.1691874543712; Sat, 12 Aug 2023 14:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691874543; cv=none; d=google.com; s=arc-20160816; b=AI1Qn7BjJvLjHy1OcGduydbpMN1FEB0NDUKEurhkVwPZiVFPMViaDp1l8J/xJgp4bD Y1hpVSPJT+KBMStffPAf32sUBysXsoQZWfaTanv33YkG/wEmfchGioSIeDdCyXqR/h4M K3GVSep5NflzfAB4xJ0t2WbCkQvZsNtP2wOH/yMTO8kVlfAQp7w2f4UvrgaWl8f7fK2Q VivrdRTTXpt/m0i7mS7sDleZ8zc5yRuAI3MCuE37rPPrkjWLn6mbAC9mWiy154fxJcE3 Qs9MamqugmSQo0YFYqs+ads3QpPdniF8kf63CmL6LUCe29wSdUIPphRp8xhUNwPDWGXL EAIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=29AYhkI+1B+aP2ulSjBZYvwAxHR9z6zN13x7VQxgXac=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=S1N3IXeF8wVkqMphCNHYGQmv8gYexC9f7pwWF18l2kbPQmxWbOsRUWDlRDwAVI2umT ttFtuS5wXXPeF9le3YguA/LFVkidGBR3uvsOIue1P9W6DLQwDVtJjsT1sLMUAjoWiE9Z +xJYO7cJ7CNCEaMOqGHiwRsT9v47JCikb4YkVdfevxcBWfeO68Z+qKDW+g84OUqdQ7U3 egncHv/wODuGQI0v+ywQrRla5qGIMBe34Gnovx4JyetKTcN7wssjMXRh55jWAJvO7mw4 W2XGXaS2YZWORnEJSUjmDfX9X5sSI3WgddxLPTWLZWSUTxCWWgeSD5LIGMNremuzsMpw BF9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KoZ1ybHn; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4ZhZweDj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h17-20020a170902f7d100b001bb9375b349si5308607plw.536.2023.08.12.14.08.50; Sat, 12 Aug 2023 14:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KoZ1ybHn; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4ZhZweDj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbjHLUGf (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbjHLUG3 (ORCPT ); Sat, 12 Aug 2023 16:06:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC1911BD5 for ; Sat, 12 Aug 2023 13:06:02 -0700 (PDT) Message-ID: <20230812195728.939405357@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870354; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=29AYhkI+1B+aP2ulSjBZYvwAxHR9z6zN13x7VQxgXac=; b=KoZ1ybHnOOGe2zWwq2N/AO8QzTIPNoxSiE04VegirbMVBzppota03EXRPs+zlqOfC+Y4iV mQ5tzz6bOoSTyJMsos6t9XinrRtWes/iOMQ78XsvyUqvXowU8iB9eJSM4Dv2nULqKOOMtT zNXoOetuSz2pq2NSUrsrtw0X2mMqmaQT9eveACdtT8gLqn2LycxbE82y1/Y9wQYVEAWGW3 JYf39p5C+yGSQRZXaJEu9Xqn0xHwoNVWbKTFosp0IVv4/GkbsgH8aro9qp0P+a/irOqeDj ViUJb8aRClX2WeEqoEI+a90k0tGIPaF9Xdi1UMLHw/329kh8gortRCNF20DaBQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870354; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=29AYhkI+1B+aP2ulSjBZYvwAxHR9z6zN13x7VQxgXac=; b=4ZhZweDjvFpyoC8DV+cd8XYhXs8IDmR6TVjaAgLPr4uZPP7HKldEsPyxif8cPYO00rwb9q ++u2PpZFUiNUafBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 24/37] x86/microcode: Clean up mc_cpu_down_prep() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:13 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774059041835284343 X-GMAIL-MSGID: 1774059041835284343 This function has nothing to do with suspend. It's a hotplug callback. Remove the bogus comment. Drop the pointless debug printk. The hotplug core provides tracepoints which track the invocation of those callbacks. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -569,16 +569,10 @@ static int mc_cpu_online(unsigned int cp static int mc_cpu_down_prep(unsigned int cpu) { - struct device *dev; - - dev = get_cpu_device(cpu); + struct device *dev = get_cpu_device(cpu); microcode_fini_cpu(cpu); - - /* Suspend is in progress, only remove the interface */ sysfs_remove_group(&dev->kobj, &mc_attr_group); - pr_debug("%s: CPU%d\n", __func__, cpu); - return 0; } From patchwork Sat Aug 12 19:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134956 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904254vqi; Sat, 12 Aug 2023 14:31:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMaqly603lTKBA49pE6K6mgFszoiAxMmScAoaBn1HQ7p78BofpPp6OqBdX1QLXuIlSv/6o X-Received: by 2002:a05:6a00:1942:b0:682:2fea:39f0 with SMTP id s2-20020a056a00194200b006822fea39f0mr7797404pfk.5.1691875900151; Sat, 12 Aug 2023 14:31:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875900; cv=none; d=google.com; s=arc-20160816; b=ypqezWDUMLVSqmRL+WkyMMFqQeLEvdrJH14tkuX5Ci9iIpPsXRgdNEfMmjxivqOntj PyWqmctOWgfqzP0tm/w/C9ZHlSHPKhI/YWPt5wh/7nYM3RTkuwSSCGlIWZzeR0mHrrMh 1xXBAQFAxEcZ+lOizhXCC0bfulPWmLbaZ8S5a3mgbN2JlIlAOJVZI1t92CX198L64egI +m1ElgD8N8KdorS/+no81+8dth5aEpbLWFbDQAh+QbChcxkY3lwOSd3YwXkZjSShPfzu NKewkXRAk3ZQrFp8iMKj0DPAhd+OTE9bnE6Cf8Ozf+a+3XGjB4KDHxhFcJ/SwDCEEh3q ZSVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=rMx81Ly7UHIBsqzKkOcI8TMo6pk6EDlMHkuqB/1BYAYg5wgoBS/R0opEDTWVXg+OHu 3iWwrvVu2AtepZ9EcDy+odwLiColh3Bm5gwwyPMdFEzDe2aJ2gdJqIM4JlRqD0vreqzl QVnYiP5hG8RelBq+Z7ZLv5xRcu8dcsSA6yq/1tNE0RAM9G/7EezdG03qD7RoUz5sOdDl bbwrAXI0NyDv2qDnKhwrh+ldlOKnwjiV//wAH7Qe+vbF8PEhZ3M7B7eznfzxlTAeTgES fy8dPoLUUUbaI48WPtJtlXRAYNwJzRwMoONQNu5GOuFH4spp23J7jUENpXb/mzj5Dvqf tVmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=g8wqhFz1; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cj12-20020a056a00298c00b0068302ab63e4si5412634pfb.273.2023.08.12.14.31.27; Sat, 12 Aug 2023 14:31:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=g8wqhFz1; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230381AbjHLUCL (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbjHLUCC (ORCPT ); Sat, 12 Aug 2023 16:02:02 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F4E230D7 for ; Sat, 12 Aug 2023 13:01:36 -0700 (PDT) Message-ID: <20230812195728.992461937@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; b=g8wqhFz16u/bxD/KdJVv7xGcI3IuXOJFFJ2R2yi4mks6Qo3ISIYeiu8BrugMN5I4iRm0r3 FlICq/KdXke7agPaJ1qpLFNaE0wZ/sDDMgv3oTvpff9NaYUmT7EmUIY4vOkDnoxU1Y0Vfz mPUwi/eN0qgOwN1ccowpSmVwqYL+BX2q47szfqLAiIKOPDxJTypb3NLPlOoleIS3II2BMk +y6YUZdQ/NwgYUD4Mxs2laBCSRAu61DcrUliaPu3Uap5zoRBbmVW9Er+i24FIM8ovIGBy2 323cZqBaRPPRtmoC2pY6HuXFtAmdx3oaJWgUFPibSwekJRO+0IeVJvx/Jw0m0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; b=qGeCLME5xdMgvmONjFqr/uFiFkmWK3EV7ltpB7b5rpgZCG9yZRxUgsiROknoX+no7yNb+Z etBwBEuuNXQ6SuBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 25/37] x86/microcode: Handle "nosmt" correctly References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:15 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060463646159837 X-GMAIL-MSGID: 1774060463646159837 From: Thomas Gleixner On CPUs where microcode loading is not NMI safe the SMT sibling which is parked in one of the play_dead() variants, these parked CPUs still react on NMIs. So if a NMI hits while the primary thread updates the microcode the resulting behaviour is undefined. The default play_dead() implementation on modern CPUs is using MWAIT, which is not guaranteed to be safe against an microcode update which affects MWAIT. Take the cpus_booted_once_mask into account to detect this case and refuse to load late if the vendor specific driver does not advertise that late loading is NMI safe. AMD stated that this is safe, so mark the AMD driver accordingly. This requirement will be partially lifted in later changes. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 2 - arch/x86/kernel/cpu/microcode/amd.c | 9 +++-- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------ arch/x86/kernel/cpu/microcode/internal.h | 13 +++---- 4 files changed, 44 insertions(+), 31 deletions(-) --- --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1314,7 +1314,7 @@ config MICROCODE config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n - depends on MICROCODE + depends on MICROCODE && SMP help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -948,10 +948,11 @@ static void microcode_fini_cpu_amd(int c } static struct microcode_ops microcode_amd_ops = { - .request_microcode_fw = request_microcode_amd, - .collect_cpu_info = collect_cpu_info_amd, - .apply_microcode = apply_microcode_amd, - .microcode_fini_cpu = microcode_fini_cpu_amd, + .request_microcode_fw = request_microcode_amd, + .collect_cpu_info = collect_cpu_info_amd, + .apply_microcode = apply_microcode_amd, + .microcode_fini_cpu = microcode_fini_cpu_amd, + .nmi_safe = true, }; struct microcode_ops * __init init_amd_microcode(void) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -326,23 +326,6 @@ static struct platform_device *microcode */ #define SPINUNIT 100 /* 100 nsec */ -static int check_online_cpus(void) -{ - unsigned int cpu; - - /* - * Make sure all CPUs are online. It's fine for SMT to be disabled if - * all the primary threads are still online. - */ - for_each_present_cpu(cpu) { - if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { - pr_err("Not all CPUs online, aborting microcode update.\n"); - return -EINVAL; - } - } - - return 0; -} static atomic_t late_cpus_in; static atomic_t late_cpus_out; @@ -459,6 +442,35 @@ static int microcode_reload_late(void) return ret; } +/* + * Ensure that all required CPUs which are present and have been booted + * once are online. + * + * To pass this check, all primary threads must be online. + * + * If the microcode load is not safe against NMI then all SMT threads + * must be online as well because they still react on NMI when they are + * soft-offlined and parked in one of the play_dead() variants. So if a + * NMI hits while the primary thread updates the microcode the resulting + * behaviour is undefined. The default play_dead() implementation on + * modern CPUs is using MWAIT, which is also not guaranteed to be safe + * against a microcode update which affects MWAIT. + */ +static bool ensure_cpus_are_online(void) +{ + unsigned int cpu; + + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + if (!cpu_online(cpu)) { + if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { + pr_err("CPU %u not online\n", cpu); + return false; + } + } + } + return true; +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) @@ -474,9 +486,10 @@ static ssize_t reload_store(struct devic cpus_read_lock(); - ret = check_online_cpus(); - if (ret) + if (!ensure_cpus_are_online()) { + ret = -EBUSY; goto put; + } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -20,18 +20,17 @@ enum ucode_state { struct microcode_ops { enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); - void (*microcode_fini_cpu)(int cpu); /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. + * The generic 'microcode_core' part guarantees that the callbacks + * below run on a target cpu when they are being called. * See also the "Synchronization" section in microcode_core.c. */ - enum ucode_state (*apply_microcode)(int cpu); - int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); - void (*finalize_late_load)(int result); + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); + unsigned int nmi_safe : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Sat Aug 12 19:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134977 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1915736vqi; Sat, 12 Aug 2023 15:06:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFEldmyxSEge4/st04w4fGHnRW3EGam0HpcizlWH+PVWZhuGrNSZlfUAd3GCtoPTATMsT2D X-Received: by 2002:a17:90a:9501:b0:269:32d2:5ac4 with SMTP id t1-20020a17090a950100b0026932d25ac4mr5051830pjo.25.1691877992823; Sat, 12 Aug 2023 15:06:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691877992; cv=none; d=google.com; s=arc-20160816; b=DaeSdJg19/qqm+uHRWRoBxYgUYo3msN1o/FEDK7ocQO9MslPLJMIeAtxCx9x0TJwzp n9yx0dIl0vnMXssEPZ8VjExB8j6agVGkqV/lVXlBvMqvK0YSMCMH3waKRvy6Ri+bFm3a YeaU/hLWA8bc7p75qf84ehL7dIUsXN7dEwPc6mcS7/iH9siiqt2BD8GU67Lso/K6FEiI asG6ivg9gd1hU7ZBjXkdR+5gDv+KOm0DzniQ9fRs9S8ER/Ho3yDjCLeDTR/Q4oFsro+k fyPw58OBLBHzpYNBoGakAtyNOq/DT6i1hnOu51sG7yBB4K/is99Pw2MImKvMjObQM7Kq VJYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=nkSM9LI1mYjs7Zis+dUWAoMqjxrmesQXTsx7IkbSNrxoLlW228ZapJ0b/W+oiEB4oO BFRYRuU8Kja3zZGhsMgqACNNGV4H5siAgSnPxhVsbbToVr9+ddGCSOY1ZnX6nZ++yOLu EtVkO3xMOGH3Vrnpc8OT1qOMTfdR9LNX3uUnijQIBmwWnSkXxmb4soFzpgkCcCBe7gaJ J4U3aP+gm2x6Bcz+59O4a3sX0iJURnxta+jnhYEkaC3an9uYiYhCn+CoT25vlLsz+5D5 gSnijQysoa12xDz137FWJITs+xd0dGpBmEYamEO7XKlnT/PBm62wJ3/RBW3bmWwaXFhn 81Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WUbmRsjM; dkim=neutral (no key) header.i=@linutronix.de header.b=mzhA71ca; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oc2-20020a17090b1c0200b0026841a42bfdsi8097940pjb.159.2023.08.12.15.06.17; Sat, 12 Aug 2023 15:06:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WUbmRsjM; dkim=neutral (no key) header.i=@linutronix.de header.b=mzhA71ca; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230511AbjHLUCO (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230291AbjHLUCC (ORCPT ); Sat, 12 Aug 2023 16:02:02 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2C8230DA for ; Sat, 12 Aug 2023 13:01:36 -0700 (PDT) Message-ID: <20230812195729.045205660@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870357; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; b=WUbmRsjME0IAcJ4TLm5gjoy8Ty3xcaF6PxdgNtVB880OoxTkVwhgxR2q+4zjxyk/QbaAPR 0tf3jBHmptrq0GUk6cZgKiCv8kyIEZro9zYLPkP6ViRUgvsU2l8bhMD9o/ZzrziLekICTR 4VQifYJca2l8ayroOa1Vmr5vmXF/q2/Fx6LgSzEaS7lyWe6ege4JDuAkdG9K7n1cBA52ab 5ZwZ/F1eSWizadFafq5kiy2kKNmqvZPE0LE7xTgcuBTlmPE+DYPboW4b33XqcVHvAyf2zk p/hDR4ir5KydRARjipJ+3vfaL+FLtwx9AGLwnRgCHnbUyWqZk3uPzzktpbY5PQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870357; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; b=mzhA71ca6pVqzUGne+D9zbgGgsVnXwpF596CShNBBizkycEUD6pPZen/+ymh6Hmye4LeKC sr9RHbNTRtKqfGBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 26/37] x86/microcode: Clarify the late load logic References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:16 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062658187517725 X-GMAIL-MSGID: 1774062658187517725 From: Thomas Gleixner reload_store() is way too complicated. Split the inner workings out and make the following enhancements: - Taint the kernel only when the microcode was actually updated. If. e.g. the rendevouz fails, then nothing happened and there is no reason for tainting. - Return useful error codes Signed-off-by: Thomas Gleixner Reviewed-by: Nikolay Borisov --- arch/x86/kernel/cpu/microcode/core.c | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -434,11 +434,11 @@ static int microcode_reload_late(void) pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); microcode_check(&prev_info); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); } else { pr_info("Reload failed, current microcode revision: 0x%x\n", boot_cpu_data.microcode); } - return ret; } @@ -471,40 +471,35 @@ static bool ensure_cpus_are_online(void) return true; } +static int ucode_load_late_locked(void) +{ + int ret; + + if (!ensure_cpus_are_online()) + return -EBUSY; + + ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); + if (ret != UCODE_NEW) + return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; + return microcode_reload_late(); +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { - enum ucode_state tmp_ret = UCODE_OK; - int bsp = boot_cpu_data.cpu_index; unsigned long val; - ssize_t ret = 0; + ssize_t ret; ret = kstrtoul(buf, 0, &val); if (ret || val != 1) return -EINVAL; cpus_read_lock(); - - if (!ensure_cpus_are_online()) { - ret = -EBUSY; - goto put; - } - - tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); - if (tmp_ret != UCODE_NEW) - goto put; - - ret = microcode_reload_late(); -put: + ret = ucode_load_late_locked(); cpus_read_unlock(); - if (ret == 0) - ret = size; - - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - - return ret; + return ret ? : size; } static DEVICE_ATTR_WO(reload); From patchwork Sat Aug 12 19:59:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1917334vqi; Sat, 12 Aug 2023 15:11:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkIYa9qho1sPibGUwRPnLxyziS0gVj3PEUGjs3/dKo9OhEaKEmHQnFnFN4NBs7cMbi3o02 X-Received: by 2002:a05:6a21:7787:b0:142:aced:c643 with SMTP id bd7-20020a056a21778700b00142acedc643mr4726170pzc.31.1691878265957; Sat, 12 Aug 2023 15:11:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691878265; cv=none; d=google.com; s=arc-20160816; b=S2Dj3xOA83yereBDYeEceAWssonFPPTou57XuwirbHdaxbdjy+Lm/4T0nhVpNmNFgw qOd1dwltLG6w0ybPrvyV1CbkvD8lGf9Sv8+hqKL7FvzUrbJTZXVMdOdcJKz51C/1+Mgm XeQMjJzDHPJgmkoXx6WJR2r79dkhOMJldSWf/bftCDgqV3gxhqIU8Zcqd9ARPzVH2U77 VK4nZbqoCpZaeFKUF95ed1Pyw1YbToboADA76WjxMTf25zQO8vbvIcM2CQVHmegIIS9k 0Bk1LjGWR1FlJEPSWFy6ty4Ao6RuG0X8u0OceD/y9Jb8PJ6Y0tOxf5B/+BU1sM6ZTo5D 8h2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=nSqixBlDLGU/s6MHoVkgUjRU2LSzIb8BbWWaDf1US2BY9ueqTTBv1MxANTIrrE24+B a4Q61TdYeWskW+Dt99u/aHcwvaWGATalp3vY8Stwx6GfFIcNupAKd7XtkjHe5sy1lLM9 sAmALBEJTaltoeJRSSW/+Fccjl0xbGKDg0mGcsW/YGdGphl8I+fhQRl9dQyHXrjuUauK e+OIXg8jUHS/aRi/iNTQ4lqRQFTkrkQzt5GdvMcKSfLmG9pJGWwONJAU7Sb9LHFNqCpl WHnlPf/edfqq11IPCN6f1ivFFwDGI0eOOs5uN4nFuoKN0cLywtLNQ8Qn1S0Nsoz3rQrb AkIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ugkIvFOa; dkim=neutral (no key) header.i=@linutronix.de header.b=JKRJwqne; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i193-20020a636dca000000b0053fbe7c8d3dsi5546999pgc.632.2023.08.12.15.10.52; Sat, 12 Aug 2023 15:11:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ugkIvFOa; dkim=neutral (no key) header.i=@linutronix.de header.b=JKRJwqne; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231138AbjHLUCR (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230498AbjHLUCI (ORCPT ); Sat, 12 Aug 2023 16:02:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02F1E1FE7 for ; Sat, 12 Aug 2023 13:01:41 -0700 (PDT) Message-ID: <20230812195729.097937370@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; b=ugkIvFOaucjW/r7xM473OXfvK5pcVN3cknssl6tn+vYvunLZ6W+hSQkCtmIXvfA73xRLSm hPAzDXdozz4dj4vvIDkTPpuRA2ORtFo6x0+kt0gJW3DdiXGWjnHfoH84+kTHGbTObDexwb HPwk3+o2eG0sTkMTDGUU+DbnDGeN7J547WHDVEx/SwgZFL7QvTNt0eF6tcXQ2Il5fPt5tm ZzlxXsZ8f34v8J3lRgVWYidPt2dxJfLPCKmONlVLz/gZwUsOt6xHDuEXTSNjBu1IubYHQm 8cGtHdeLM0eBszebHkIBO6FKYl5mnXjR8m/o8SeZD7V/7n7yW3UV4q57WEmccA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; b=JKRJwqneRt2yMIREkHo8laWhBjmhaaOEaLFiuW5MU6G31/bb3r7ODSBZG7tmt/NPGGFAJ5 daJHOharoQ7aZXAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 27/37] x86/microcode: Sanitize __wait_for_cpus() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:18 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062944536240973 X-GMAIL-MSGID: 1774062944536240973 From: Thomas Gleixner The code is too complicated for no reason: - The return value is pointless as this is a strict boolean. - It's way simpler to count down from num_online_cpus() and check for zero. - The timeout argument is pointless as this is always one second. - Touching the NMI watchdog every 100ns does not make any sense, neither does checking every 100ns. This is really not a hotpath operation. Preload the atomic counter with the number of online CPUs and simplify the whole timeout logic. Delay for one microsecond and touch the NMI watchdog once per millisecond. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 41 ++++++++++++++--------------------- 1 file changed, 17 insertions(+), 24 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,31 +324,24 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ -#define SPINUNIT 100 /* 100 nsec */ +static atomic_t late_cpus_in, late_cpus_out; - -static atomic_t late_cpus_in; -static atomic_t late_cpus_out; - -static int __wait_for_cpus(atomic_t *t, long long timeout) +static bool wait_for_cpus(atomic_t *cnt) { - int all_cpus = num_online_cpus(); - - atomic_inc(t); - - while (atomic_read(t) < all_cpus) { - if (timeout < SPINUNIT) { - pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", - all_cpus - atomic_read(t)); - return 1; - } + unsigned int timeout; - ndelay(SPINUNIT); - timeout -= SPINUNIT; + WARN_ON_ONCE(atomic_dec_return(cnt) < 0); - touch_nmi_watchdog(); + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (!atomic_read(cnt)) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); } - return 0; + /* Prevent the late comers to make progress and let them time out */ + atomic_inc(cnt); + return false; } /* @@ -366,7 +359,7 @@ static int __reload_late(void *info) * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_in)) return -1; /* @@ -389,7 +382,7 @@ static int __reload_late(void *info) } wait_for_siblings: - if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_out)) panic("Timeout during microcode update!\n"); /* @@ -416,8 +409,8 @@ static int microcode_reload_late(void) pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); - atomic_set(&late_cpus_out, 0); + atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Sat Aug 12 19:59:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134944 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1889651vqi; Sat, 12 Aug 2023 13:47:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFz/NT7DPi32dWNdtkWITkqlQvCmfyQOlC3BBYmm253SBM7EgIY1/6stXFVfdj+pFttukIG X-Received: by 2002:a17:902:e5c5:b0:1bd:ca21:c83 with SMTP id u5-20020a170902e5c500b001bdca210c83mr1862834plf.68.1691873255433; Sat, 12 Aug 2023 13:47:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691873255; cv=none; d=google.com; s=arc-20160816; b=sAobCQcbs1wAM60N3pzmy8wyigRdfF2kQywnH/ZcVPPZ+Nnew1wanESTgq5hqwQGjN msGqdSLPhvOkUDYN8yp43C+wcUAUKsIeiKKE73ENNgDZGrthImta+TjHVAm34doDGk8B 9ZlYcQRtDdtD83/lHApJZ1+efHafGDYNXMPITEY/UvdMrT/AVb3YVsfIvw3lB+mTa63X Z8zydQ8abLVpFPAWGLplJBz9+sgDs/6UdST5dejfP3memlqL4gmIH6SzcoAEn+qo9+74 TvD9DRLQ8BPur1FmBJYm2sXvXa5xd5WgU7UEquJA+xEROEprlutGhBvAE2X1gdOmTXRK 3zBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=YM/np7q8p33+Y+dd8ul4jmtRbcXIEbzJ7Z0GRz+W2yNdnAMjOsDwGbxAOyx7VLurNg WLwo4oUo/cIjs0NfkYl6ZIJ0mBXpZ0u3+n15QhRItmmQm1oQ47wGz1QjOCcBiktde9Gm U8E+7AQnb2zAqKEjbT8yPIvtU6xcqgCbTAxNAiFLJR/FCe0/mLcJ1hJkWb20bJHAIS2R YXIMbdJklyUtwInntRTRyIYLxnHg/EV6ScJm9PyShnlOqlhYhvJZ/sT37RqnQaHCrQgB tfekSVE5NQLR1a3SY49fhpfoOsQeC1+waKWxjgNwXt8aB6LXu6K1wHhFX7BISF/v/EIg fUMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1Z1lw9Ww; dkim=neutral (no key) header.i=@linutronix.de header.b=vUrkC1ip; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b4-20020a170902d88400b001b7fa1a9a36si5202237plz.67.2023.08.12.13.47.22; Sat, 12 Aug 2023 13:47:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1Z1lw9Ww; dkim=neutral (no key) header.i=@linutronix.de header.b=vUrkC1ip; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231200AbjHLUGj (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231185AbjHLUGb (ORCPT ); Sat, 12 Aug 2023 16:06:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6527C1BD2 for ; Sat, 12 Aug 2023 13:06:05 -0700 (PDT) Message-ID: <20230812195729.151791844@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; b=1Z1lw9Ww3BM9YXEw1BzRvEWs/3vjeiRnep1e0b18O1h3e7/54fwoOtvgkG7UkaxqpLk/oa sdtYLEYQAAnxcl88ABdTn3eh08lHjNOTCkgECUDsfckza313teaJrKvKbRtsq03o6R9N1k Qz1/R+nARgME7/sOgr4eIpFilkYAybZUfIx2QwVbm1woF+OyhO5Gg0Cz/vTc5kGdE1vthK UXTH0+esHfJY3HQye4REWXVlzjqfVYkKYvbZe/auaxghnBgXoVntspJB7luBNDQoWqWAme 6dkAAP+Ieri1AG39TXW0RxHYwb6jjLnYgyHWWNiA2mDUwB0hLCMI+UKbwVfc/g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; b=vUrkC1ippGLhba5Q8lhTClaptrOpApv0nxztTG+iEF2D0BVUzIBScyVrwverfaFESnoPEp Gw1soY2IdAougYCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 28/37] x86/microcode: Add per CPU result state References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:20 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774057690268118700 X-GMAIL-MSGID: 1774057690268118700 From: Thomas Gleixner The microcode rendevouz is purely acting on global state, which does not allow to analyze fails in a coherent way. Introduce per CPU state where the results are written into, which allows to analyze the return codes of the individual CPUs. Initialize the state when walking the cpu_present_mask in the online check to avoid another for_each_cpu() loop. Enhance the result print out with that. The structure is intentionally named ucode_ctrl as it will gain control fields in subsequent changes. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 108 ++++++++++++++++++------------- arch/x86/kernel/cpu/microcode/internal.h | 1 2 files changed, 65 insertions(+), 44 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,6 +324,11 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +struct ucode_ctrl { + enum ucode_state result; +}; + +static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, late_cpus_out; static bool wait_for_cpus(atomic_t *cnt) @@ -344,23 +349,19 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } -/* - * Returns: - * < 0 - on error - * 0 - success (no update done or microcode was updated) - */ -static int __reload_late(void *info) +static int ucode_load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); - enum ucode_state err; - int ret = 0; + enum ucode_state ret; /* * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (!wait_for_cpus(&late_cpus_in)) - return -1; + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return 0; + } /* * On an SMT system, it suffices to load the microcode on one sibling of @@ -369,17 +370,11 @@ static int __reload_late(void *info) * loading attempts happen on multiple threads of an SMT core. See * below. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - err = microcode_ops->apply_microcode(cpu); - else + if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) goto wait_for_siblings; - if (err >= UCODE_NFOUND) { - if (err == UCODE_ERROR) { - pr_warn("Error reloading microcode on CPU %d\n", cpu); - ret = -1; - } - } + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); wait_for_siblings: if (!wait_for_cpus(&late_cpus_out)) @@ -391,19 +386,18 @@ static int __reload_late(void *info) * per-cpu cpuinfo can be updated with right microcode * revision. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - err = microcode_ops->apply_microcode(cpu); + if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) + return 0; - return ret; + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + return 0; } -/* - * Reload microcode late on all CPUs. Wait for a sec until they - * all gather together. - */ -static int microcode_reload_late(void) +static int ucode_load_late_stop_cpus(void) { - int old = boot_cpu_data.microcode, ret; + unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); @@ -418,26 +412,47 @@ static int microcode_reload_late(void) */ store_cpu_caps(&prev_info); - ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + stop_machine_cpuslocked(ucode_load_cpus_stopped, NULL, cpu_online_mask); + + /* Analyze the results */ + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + switch (per_cpu(ucode_ctrl.result, cpu)) { + case UCODE_UPDATED: updated++; break; + case UCODE_TIMEOUT: timedout++; break; + case UCODE_OK: siblings++; break; + default: failed++; break; + } + } if (microcode_ops->finalize_late_load) - microcode_ops->finalize_late_load(ret); + microcode_ops->finalize_late_load(!updated); - if (!ret) { - pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); - microcode_check(&prev_info); - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - } else { - pr_info("Reload failed, current microcode revision: 0x%x\n", - boot_cpu_data.microcode); + if (!updated) { + /* Nothing changed. */ + if (!failed && !timedout) + return 0; + pr_err("Microcode update failed: %u CPUs failed %u CPUs timed out\n", + failed, timedout); + return -EIO; } - return ret; + + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("Microcode load: updated on %u primary CPUs with %u siblings\n", updated, siblings); + if (failed || timedout) { + pr_err("Microcode load incomplete. %u CPUs timed out or failed\n", + num_online_cpus() - (updated + siblings)); + } + pr_info("Microcode revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); + microcode_check(&prev_info); + + return updated + siblings == num_online_cpus() ? 0 : -EIO; } /* - * Ensure that all required CPUs which are present and have been booted - * once are online. + * This function does two things: + * + * 1) Ensure that all required CPUs which are present and have been booted + * once are online. * * To pass this check, all primary threads must be online. * @@ -448,9 +463,12 @@ static int microcode_reload_late(void) * behaviour is undefined. The default play_dead() implementation on * modern CPUs is using MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. + * + * 2) Initialize the per CPU control structure */ -static bool ensure_cpus_are_online(void) +static bool ucode_setup_cpus(void) { + struct ucode_ctrl ctrl = { .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -460,6 +478,8 @@ static bool ensure_cpus_are_online(void) return false; } } + /* Initialize the per CPU state */ + per_cpu(ucode_ctrl, cpu) = ctrl; } return true; } @@ -468,13 +488,13 @@ static int ucode_load_late_locked(void) { int ret; - if (!ensure_cpus_are_online()) + if (!ucode_setup_cpus()) return -EBUSY; ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); if (ret != UCODE_NEW) return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; - return microcode_reload_late(); + return ucode_load_late_stop_cpus(); } static ssize_t reload_store(struct device *dev, --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -16,6 +16,7 @@ enum ucode_state { UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, + UCODE_TIMEOUT, }; struct microcode_ops { From patchwork Sat Aug 12 19:59:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134964 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904779vqi; Sat, 12 Aug 2023 14:33:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFvDhII1+p5Vbug3vUAgSfXZFMpBLO0oOoM96yMSCsaJdFS7PX/K2NkLyBeJm8HLaX8bF+6 X-Received: by 2002:a17:902:d4c4:b0:1bc:411f:1097 with SMTP id o4-20020a170902d4c400b001bc411f1097mr5978728plg.47.1691875988980; Sat, 12 Aug 2023 14:33:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875988; cv=none; d=google.com; s=arc-20160816; b=XbErRGb63OPrflcczGxtLJrVh2I6XOLQB2EhHOxG/XaDS7gGNmoB82g6f9nNrOZWea Y6YqY9ju2tjTefGgzh3QyP5pygU75b9unCVJNRR+UXd6E0/civn/rV0uuPJAIBAXMTYD 4LSOyKKP5L1EdPwM7MtFuP0941nL5D0KMIn6dyneVaIY9DvTbkAqP2iinZuvHGQ/7Ijj V1B2xwq9Ghe9rdK3O0S7y0vkXcamdo4k2etC/NdcJuVzGjDx09U/15O2dSXgiBtBEigI bWAL9yECnFT1aa34XgjICkuGMZ0By9JlVdAC9NqDVGY2azDkt0zLhQmvqaDFQsvuytWm VGpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=qHU8gg0WtqNO8HV8IC4GCRcAj4hyS54wDIwNb83JWAGdxoaBIDx/fWIaV5uhXTbRmd IzYTO5x5tRup+5q82r0Z+PRCav+nUXd2rtwo3WCT9meDI8ryLx+J/iJsgR0tVc6QRk66 cPEsnvF/yvN1UHYNZVN8/JhEl9XC9mph3Zj/r2YL1X1nJ5pTEPrFA+A399v0MNRKL/nU Ja9OKIFehStZeiNVGAvXALaBYrjRNlrfO8NABQ046GKQxN36B3WOleF28wbNwxpZnMqB 2PX+n+A4WwwzLft4P7+KVd7SVBkP2LQif+Iam1NAq2xM1A4eI+3Ef04pDVScEvx/HVch H8KA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rEREPJTL; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id li14-20020a170903294e00b001b9e970e961si5174260plb.277.2023.08.12.14.32.56; Sat, 12 Aug 2023 14:33:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rEREPJTL; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230512AbjHLUCp (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230523AbjHLUCn (ORCPT ); Sat, 12 Aug 2023 16:02:43 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 774151FF0 for ; Sat, 12 Aug 2023 13:02:22 -0700 (PDT) Message-ID: <20230812195729.208217580@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; b=rEREPJTL2JY65mizGjNaXmxaCdpAVvnHqW94RU4XCS0ICFRcq0oklA7JVOm5yVG4riYAI9 DRYNMbN3huOlj/3PK/SGOyNDP9H71qbal0V1FujKMDSoA2wHm0WS6zFbSP3TuOlvNyVRSQ 68fNNzr2TR9homzZwVyCigO+igRc8igviIlbO9+b1YiadedBxACCBbetuBs7Cmz1bh4SNT 2oGdqo2jS3dLf9FLdwcz6REX/rS9grRnYEhRMDKgpYug+Yn7ICzj7/Ak1uDvTTjn62v/nP VBZ3Aqnw5jK8wxJTzvxKGh6GPFTorXnEiWhPMo6RK+Gd12/cIVjjk30ZDvBRtA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; b=T3qOkHsSABt5D295p3mTi3l39wGkUzJR1z/+oERTRGS2SWiXuM6otvUK0G6uXXT7bXAV1K zAxBV9JB2065CmBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 29/37] x86/microcode: Add per CPU control field References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:21 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060556922640361 X-GMAIL-MSGID: 1774060556922640361 From: Thomas Gleixner Add a per CPU control field to ucode_ctrl and define constants for it: SCTRL_WAIT indicates that the CPU needs to spinwait with timeout SCTRL_APPLY indicates that the CPU needs to invoke the microcode_apply() callback SCTRL_DONE indicates that the CPU can proceed without invoking the microcode_apply() callback. In theory this could be a global control field, but a global control does not cover the following case: 15 primary CPUs load microcode successfully 1 primary CPU fails and returns with an error code With global control the sibling of the failed CPU would either try again or the whole operation would be aborted with the consequence that the 15 siblings do not invoke the apply path and end up with inconsistent software state. The result in dmesg would be inconsistent too. There are two additional fields added and initialized: ctrl_cpu and secondaries. ctrl_cpu is the CPU number of the primary thread for now, but with the upcoming uniform loading at package or system scope this will be one CPU per package or just one CPU. Secondaries hands the control CPU a CPU mask which will be required to release the secondary CPUs out of the wait loop. Preparatory change for implementing a properly split control flow for primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,8 +324,16 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +enum sibling_ctrl { + SCTRL_WAIT, + SCTRL_APPLY, + SCTRL_DONE, +}; + struct ucode_ctrl { + enum sibling_ctrl ctrl; enum ucode_state result; + unsigned int ctrl_cpu; }; static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); @@ -468,7 +476,7 @@ static int ucode_load_late_stop_cpus(voi */ static bool ucode_setup_cpus(void) { - struct ucode_ctrl ctrl = { .result = -1, }; + struct ucode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -478,7 +486,15 @@ static bool ucode_setup_cpus(void) return false; } } - /* Initialize the per CPU state */ + + /* + * Initialize the per CPU state. This is core scope for now, + * but prepared to take package or system scope into account. + */ + if (topology_is_primary_thread(cpu)) + ctrl.ctrl_cpu = cpu; + else + ctrl.ctrl_cpu = cpumask_first(topology_sibling_cpumask(cpu)); per_cpu(ucode_ctrl, cpu) = ctrl; } return true; From patchwork Sat Aug 12 19:59:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134959 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904494vqi; Sat, 12 Aug 2023 14:32:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFTnBn/+VBg7tEElcjEhITBFSoWKMJVhUdm7n1f/pkDn7+OQVLBXzpQQKSxk8YAiHFNy/RL X-Received: by 2002:a17:902:c14d:b0:1bd:c931:8c33 with SMTP id 13-20020a170902c14d00b001bdc9318c33mr2931879plj.22.1691875942778; Sat, 12 Aug 2023 14:32:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875942; cv=none; d=google.com; s=arc-20160816; b=aEB+C0jmhB55aLGeRAfab887ShBoLIrSk8JmUfFLiQG5Uotxs1wMCXNC/3B0aTRATh 02peHgLB2Mj9b8DiyDrLeX19UKGTEk8fxQXVirYAIK1nwHkzxWgIT4WIA0OXQL9nj/zx m5H0IMKBn19qIlMVhkhuB8A7SPy5+yY3Cfgdz2BiMOovkVQFUvLVcJ7rxn+9p4IcO7Ur h/DTHbK2dlWGLD3dnPlS+8i95TQYTouEuEfnXKbZJIzYTNsqYc5i5DJ1O65yoSCDlAB2 hZmw2LuE85HFfMu0x6OUpXGLSTsTkoLqlpZsEBXGR+huT1gVFtaMYaxbp9yM33sSGxJT mctg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=i31mXygOpgAWdUhs73KHtpEmgWnnZsk1q1RzS0uwcIPspxhZdAeOruCLltMamLQQ4x vryyGmobAWU7hqsu44EmXZ0VgB62EAcu2Sj7q4nwl95aae1CKo8gOpryizt116tmoc02 5aOkcAJ4Q6s/wnuEHkRP4sBZ5hea6xkjIgidYlj9C6gn6x+zagwRCY/OBfSGbrK1UFT9 +0GVtZ5rvcWNb2p0fUBCnzPVWljR88BVceSD7tye6n08NfVx7U/nHpxSI31XqAudJ5h5 42XIc4yWjAmPvPbZlUHrIs6xEbENIprqujcYpG+ILQ7216JbDyycAy3NxuJseXnNSxqK P8ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=M3fEcYwR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i3-20020a170902c94300b001bbd0797a55si5566970pla.359.2023.08.12.14.32.10; Sat, 12 Aug 2023 14:32:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=M3fEcYwR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231282AbjHLUG5 (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231267AbjHLUGq (ORCPT ); Sat, 12 Aug 2023 16:06:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 171A5CE for ; Sat, 12 Aug 2023 13:06:23 -0700 (PDT) Message-ID: <20230812195729.272941596@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; b=M3fEcYwRPucTriGvueSLaleqRSg7eLY3gJmW4uomGIVX9WE9SMJfOCwZ2EV678dR9kl8Vl 9L1iNrjD67+ttcDGCabe8/c7B0qkKC/hMZ1WEU+g3ecgVskuSH/xgFZNS99QmcI7sIxWJj ULoAudSVYwobcqzO4gKz+donjp57UHqewUqecssbw2bf+2uoluXxvz95X/0AfjBpbvvigM u7QQFTkpkj4cUijMHkTZbc2UiQjF5BP0z6N86qnuBkrHjEEcKosHzDhxjvQXgawzMXVqVS TRVeT4Dvla/1QdJnyIdQoAPrsgtxHIl7Zqzotpqgrs4/8xWLJoeIPdD2BRmd1w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870363; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; b=pfJSr+h2nyv5sAeYgV/pAzJCqIOGswfWse3ifIJNdUM+3lUeo0OaZmeYXgNWR4BDiMDSXW x1+El5Imrg2oQUAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 30/37] x86/microcode: Provide new control functions References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:23 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060508680536494 X-GMAIL-MSGID: 1774060508680536494 From: Thomas Gleixner The current all in one code is unreadable and really not suited for adding future features like uniform loading with package or system scope. Provide a set of new control functions which split the handling of the primary and secondary CPUs. These will replace the current rendevouz all in one function in the next step. This is intentionally a separate change because diff makes an complete unreadable mess otherwise. So the flow separates the primary and the secondary CPUs into their own functions, which use the control field in the per CPU ucode_ctrl struct. primary() secondary() wait_for_all() wait_for_all() apply_ucode() wait_for_release() release() apply_ucode() Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 86 +++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -357,6 +357,92 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } +static bool wait_for_ctrl(void) +{ + unsigned int timeout; + + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); + } + return false; +} + +static __maybe_unused void ucode_load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + /* Initial rendevouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return; + } + + /* + * Wait for primary threads to complete. If one of them hangs due + * to the update, there is no way out. This is non-recoverable + * because the CPU might hold locks or resources and confuse the + * scheduler, watchdogs etc. There is no way to safely evacuate the + * machine. + */ + if (!wait_for_ctrl()) + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + + /* + * If the primary succeeded then invoke the apply() callback, + * otherwise copy the state from the primary thread. + */ + if (this_cpu_read(ucode_ctrl.ctrl) == SCTRL_APPLY) + ret = microcode_ops->apply_microcode(cpu); + else + ret = per_cpu(ucode_ctrl.result, ctrl_cpu); + + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); +} + +static __maybe_unused void ucode_load_primary(unsigned int cpu) +{ + struct cpumask *secondaries = topology_sibling_cpumask(cpu); + enum sibling_ctrl ctrl; + enum ucode_state ret; + unsigned int sibling; + + /* Initial rendevouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + return; + } + + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + + /* + * If the update was successful, let the siblings run the apply() + * callback. If not, tell them it's done. This also covers the + * case where the CPU has uniform loading at package or system + * scope implemented but does not advertise it. + */ + if (ret == UCODE_UPDATED || ret == UCODE_OK) + ctrl = SCTRL_APPLY; + else + ctrl = SCTRL_DONE; + + for_each_cpu(sibling, secondaries) { + if (sibling != cpu) + per_cpu(ucode_ctrl.ctrl, sibling) = ctrl; + } +} + static int ucode_load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); From patchwork Sat Aug 12 19:59:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134970 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1905478vqi; Sat, 12 Aug 2023 14:35:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFcgR4gk17H5TrpOYYqtjJQJLH5CMQayF4WjpMe1IKNqPQFE7og9U4nKwSqHr190Z7uwkqP X-Received: by 2002:a05:6a20:8f21:b0:133:71e4:c172 with SMTP id b33-20020a056a208f2100b0013371e4c172mr8485167pzk.15.1691876120182; Sat, 12 Aug 2023 14:35:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691876120; cv=none; d=google.com; s=arc-20160816; b=b1lnKsPyeSJLhCGVdZ/WVNEiXHCrMjxsUCAzLMQgQqdImcDIdygzsD3oIsFUHVg1Oc h7uKjEXl8euRHT5V3GdPp+OJh818/pnHnJNdoZe0YK55OStiIDHL79d4NYMTb7FF5hBz eDVkJmEoqcBaCzsntEBEugSkP1VMlz16dHIQCNnYmtMAoO4Gai5/dHwpPbJd37AdBFOB NehCQoQY/TPGSPnBcjATsAs91kljy5WuXeDKdqhPWxnkyY0dAUwRBisB4Pb9jUlS1+j3 i+BiN5EC2OXnyCyRA7YgTty69mIMfpDukqPBn+sTI7OWwMPa4XC2mQHbj70k9BzpCHz+ TLRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=HYSaaAnHgCzGwQbOQSFd6D3SPBKwDJqZ3ov1LZJoj1aeVzk7piKOHBhFMbqo6lKVGJ M92SznvJubsZrTTsOWt5xT4wUVnLMeyayAM5UTKom/6L4KI2UpsXvSlSfQQAE95a6bwO YpDSEPljnnwN2MMa3pmIpb7jzv9jG1NTUZ2FTc7P5q8Mqo4ry+5E2KfU6d6OFsat4Fj+ 69+9uRbkvlVMS4SQ+zLuIcHNGzZouFprMeMTHf8kOB1RGrNLfIBvEfYn1DZh2CO1YO4U mjiUzlgKSxSozPbb31NaB6O/rILVQ8bnQNSSQzhhbI4ChKbS7b2tkZckXcUW/0osIWpC lH+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="S/7ymfOX"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b12-20020a63340c000000b00548e140a1a4si5616525pga.644.2023.08.12.14.35.07; Sat, 12 Aug 2023 14:35:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="S/7ymfOX"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231262AbjHLUGv (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231232AbjHLUGp (ORCPT ); Sat, 12 Aug 2023 16:06:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 919E01716 for ; Sat, 12 Aug 2023 13:06:21 -0700 (PDT) Message-ID: <20230812195729.332293834@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870365; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; b=S/7ymfOX7c/c7lnr1QmYEEJG2IjfdZu+GTKQTRf/1CcBJYkqhXhddmO5vbUb6KcywTn/jf 5qAhhE3qWtHqTb+G2qT+Zs+I+qkqQwb30rljGEv4HK83bxXKnH5zL3r6vYkjf+x/3rC/BW q3fq5gxHFCui7SovpGU2TAx99FcN5hQPQz2Vd1jk/X8AZovvPkeG81MEOAAtVrYXe+TEze 09I7V0BefzWlm/UG9iJ+SbO/Mf/Zrk2reH6QQLZ+Ca20cPkD57l8NN9370tZqjewJTVTRl c6CRTwMQLPrRt553RKFOE8o5uG34r4/ZBiCaA8/SzljpK//iSqYDREvYcQQaVA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870365; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; b=+litjPSpn2DnB8QnsGio+HJVIncflnHvnuiDvl3iEs/0kRg7HBzEIluEZ36eHp7ViEb5Hf W5Jys18PMeT8qfDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 31/37] x86/microcode: Replace the all in one rendevouz handler References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:24 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060694700232243 X-GMAIL-MSGID: 1774060694700232243 From: Thomas Gleixner with a new handler which just separates the control flow of primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 51 ++++++----------------------------- 1 file changed, 9 insertions(+), 42 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -337,7 +337,7 @@ struct ucode_ctrl { }; static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); -static atomic_t late_cpus_in, late_cpus_out; +static atomic_t late_cpus_in; static bool wait_for_cpus(atomic_t *cnt) { @@ -371,7 +371,7 @@ static bool wait_for_ctrl(void) return false; } -static __maybe_unused void ucode_load_secondary(unsigned int cpu) +static void ucode_load_secondary(unsigned int cpu) { unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); enum ucode_state ret; @@ -407,7 +407,7 @@ static __maybe_unused void ucode_load_se this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); } -static __maybe_unused void ucode_load_primary(unsigned int cpu) +static void ucode_load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -445,46 +445,14 @@ static __maybe_unused void ucode_load_pr static int ucode_load_cpus_stopped(void *unused) { - int cpu = smp_processor_id(); - enum ucode_state ret; - - /* - * Wait for all CPUs to arrive. A load will not be attempted unless all - * CPUs show up. - * */ - if (!wait_for_cpus(&late_cpus_in)) { - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return 0; - } - - /* - * On an SMT system, it suffices to load the microcode on one sibling of - * the core because the microcode engine is shared between the threads. - * Synchronization still needs to take place so that no concurrent - * loading attempts happen on multiple threads of an SMT core. See - * below. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - goto wait_for_siblings; + unsigned int cpu = smp_processor_id(); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); - -wait_for_siblings: - if (!wait_for_cpus(&late_cpus_out)) - panic("Timeout during microcode update!\n"); - - /* - * At least one thread has completed update on each core. - * For others, simply call the update to make sure the - * per-cpu cpuinfo can be updated with right microcode - * revision. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - return 0; + if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + ucode_load_primary(cpu); + else + ucode_load_secondary(cpu); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); + /* No point to wait here. The CPUs will all wait in stop_machine(). */ return 0; } @@ -498,7 +466,6 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); - atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Sat Aug 12 19:59:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134978 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1915902vqi; Sat, 12 Aug 2023 15:06:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4vmx61IjAXKpJW1YtQka2RiTkeNey9aJPhJm5zIlsiUFzQOoU1+2PuyEQS9C+famYfcn2 X-Received: by 2002:a17:903:247:b0:1bb:b86e:8d60 with SMTP id j7-20020a170903024700b001bbb86e8d60mr5397071plh.46.1691878018454; Sat, 12 Aug 2023 15:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691878018; cv=none; d=google.com; s=arc-20160816; b=VNVynybDnfetX5wCt003cBta7NW0wT0F0NKzFyCriyvvmuIWV0i7xgTKTjgndpfrf7 zBXJxbQQV0n4gpu8HamFVO0tPCRnrft+w6NE9iED/aszXlLxW4+uw1vo7vmInXU5yR9R 6cH8bbMNiiqQ/T75vNCRCaMkUuwSkRdPgoyyiQQrO/S+36m2a7xk24aIxp/oeQ13zvT2 u/G5wVJGSfqrdoSGotWtp8z1nthXVREOQh0DaEboV3+9VhfJ+XENfjXa/DurrR/rwqTL tBmJ9d1gtnbRzPC9gdHi7MRVDE3G3xXUi+IzPXm301HMv+Qrc48G+cDG8x8pBhnHVpp5 o43Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=jIHJGcyGY0V0aJcaBH+xFPGYAym+5j4xuz0uER+GG98=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=dfknhH9s4xKWIdCyqsWoQ8AKuQ9MVZGM948zrYkSuqrALUFdYI/2w7aQuaFlpwvq8J zGm98qfY6/PrsWl/OUVuIitTf1WNmqNxydc4Ohj8fIkP7syy9dhQOJolaaaW70YPhFRy rPdDrZoeW3f4+pOfu2zP1XdmchBEEW/NxE1rTUXWCi1/TSZDdO7MHbtOzU1yLxYKfm/K Dj75mveJILXugq4Hx8HD4Ui4WQNEGk7QFuPciOBrq7Mo49Z+pJAF6sdeFvD8oc2kgbpr 0X2nAc2n/941MU4m5sH7RJZOk0RBeMQMUi4Sh9VewcFkwQAeKF6+/B4RvGwW7CbJpMht ws0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DqQ3dPW4; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f21-20020a656295000000b00563f8ccc0a1si5502611pgv.576.2023.08.12.15.06.45; Sat, 12 Aug 2023 15:06:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=DqQ3dPW4; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230480AbjHLUCd (ORCPT + 99 others); Sat, 12 Aug 2023 16:02:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230503AbjHLUC1 (ORCPT ); Sat, 12 Aug 2023 16:02:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 119933596 for ; Sat, 12 Aug 2023 13:02:03 -0700 (PDT) Message-ID: <20230812195729.388848949@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jIHJGcyGY0V0aJcaBH+xFPGYAym+5j4xuz0uER+GG98=; b=DqQ3dPW4vR/kyCueRRFx5V/ufBf+tMf8lRFxoKHqDGLDf+a1iSJ7EQYWbdoBHDggzDkTpq bEojKksXggvMMgAha7xGBtPzKnrx7NJWbBQQB2M558gp86Yh7SxKsNUecsQNCAF+HpuMbm 2lboB9CstC03A3PdLFAfoJqQl2bVfpnl/Rui74ucjqJw2jMohfQ6W4hdm1UDDHSqforTjy JdqQEB2wvDhXZ6D+uY8UhXMCXFwk8fVUXp7NtErQeDYzgw4giIgc8BJ2WfV+q5BOAURgEF V5AO2FP2sQJxGDGmjwbXdnabl3EkrDBMmIVWShe5lYV85PsCFOv/7UqLC1dsSg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870366; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jIHJGcyGY0V0aJcaBH+xFPGYAym+5j4xuz0uER+GG98=; b=0mYywXzLhpqF3hICRyPLcikSeAXXvspXxB0pmDisC/jNMWV0YUQxUr7bXmKAvuTHI0t3qc NWL42u12zqKOT3Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 32/37] x86/microcode: Rendezvous and load in NMI References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:26 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774062684672435070 X-GMAIL-MSGID: 1774062684672435070 From: Thomas Gleixner stop_machine() does not prevent the spin-waiting sibling from handling an NMI, which is obviously violating the whole concept of rendezvous. Implement a static branch right in the beginning of the NMI handler which is NOOPed except when enabled by the late loading mechanism. The later loader enables the static branch before stop_machine() is invoked. Each CPU has an nmi_enable in its control structure which indicates whether the CPU should go into the update routine. This is required to bridge the gap between enabling the branch and actually being at the point where it makes sense. Each CPU which arrives in the stopper thread function sets that flag and issues a self NMI right after that. If the NMI function sees the flag clear, it returns. If it's set it clears the flag and enters the rendezvous. This is safe against a real NMI which hits in between setting the flag and sending the NMI to itself. The real NMI will be swallowed by the microcode update and the self NMI will then let stuff continue. Otherwise this would end up with a spurious NMI. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 12 ++++++++ arch/x86/kernel/cpu/microcode/core.c | 42 ++++++++++++++++++++++++++++--- arch/x86/kernel/cpu/microcode/intel.c | 1 arch/x86/kernel/cpu/microcode/internal.h | 3 +- arch/x86/kernel/nmi.c | 4 ++ 5 files changed, 57 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -75,4 +75,16 @@ void show_ucode_info_early(void); static inline void show_ucode_info_early(void) { } #endif /* !CONFIG_CPU_SUP_INTEL */ +bool microcode_nmi_handler(void); + +#ifdef CONFIG_MICROCODE_LATE_LOADING +DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); +static __always_inline bool microcode_nmi_handler_enabled(void) +{ + return static_branch_unlikely(µcode_nmi_handler_enable); +} +#else +static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } +#endif + #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include +#include #include #include #include @@ -334,8 +336,10 @@ struct ucode_ctrl { enum sibling_ctrl ctrl; enum ucode_state result; unsigned int ctrl_cpu; + bool nmi_enabled; }; +DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); static atomic_t late_cpus_in; @@ -349,7 +353,8 @@ static bool wait_for_cpus(atomic_t *cnt) if (!atomic_read(cnt)) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } /* Prevent the late comers to make progress and let them time out */ @@ -365,7 +370,8 @@ static bool wait_for_ctrl(void) if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } return false; @@ -443,7 +449,7 @@ static void ucode_load_primary(unsigned } } -static int ucode_load_cpus_stopped(void *unused) +static bool microcode_update_handler(void) { unsigned int cpu = smp_processor_id(); @@ -452,7 +458,29 @@ static int ucode_load_cpus_stopped(void else ucode_load_secondary(cpu); - /* No point to wait here. The CPUs will all wait in stop_machine(). */ + touch_nmi_watchdog(); + return true; +} + +bool microcode_nmi_handler(void) +{ + if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + return false; + + this_cpu_write(ucode_ctrl.nmi_enabled, false); + return microcode_update_handler(); +} + +static int ucode_load_cpus_stopped(void *unused) +{ + if (microcode_ops->use_nmi) { + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + } else { + /* Just invoke the handler directly */ + microcode_update_handler(); + } return 0; } @@ -473,8 +501,14 @@ static int ucode_load_late_stop_cpus(voi */ store_cpu_caps(&prev_info); + if (microcode_ops->use_nmi) + static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + stop_machine_cpuslocked(ucode_load_cpus_stopped, NULL, cpu_online_mask); + if (microcode_ops->use_nmi) + static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { switch (per_cpu(ucode_ctrl.result, cpu)) { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -688,6 +688,7 @@ static struct microcode_ops microcode_in .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, + .use_nmi = IS_ENABLED(CONFIG_X86_64), }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,7 +31,8 @@ struct microcode_ops { enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); - unsigned int nmi_safe : 1; + unsigned int nmi_safe : 1, + use_nmi : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -343,6 +344,9 @@ static noinstr void default_do_nmi(struc instrumentation_begin(); + if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) + goto out; + handled = nmi_handle(NMI_LOCAL, regs); __this_cpu_add(nmi_stats.normal, handled); if (handled) { From patchwork Sat Aug 12 19:59:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134951 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1897213vqi; Sat, 12 Aug 2023 14:10:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLT94PzXRxIh1nUbcCEuaRCMO3iMHFXyJeXe8tcewAGpUXYbyzmm8pDuoi5vK/cxpxeVtR X-Received: by 2002:a05:6a21:7888:b0:13e:4dee:b1f4 with SMTP id bf8-20020a056a21788800b0013e4deeb1f4mr5757107pzc.31.1691874619154; Sat, 12 Aug 2023 14:10:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691874619; cv=none; d=google.com; s=arc-20160816; b=HYpAAuUH0S/Q5QLhxli8aMo+rO3G8HGk714ZbMVxrs8n6X6DI4+JcmJlU5Y4TAJ5n6 KLYa4RxWGQl6IRTgwRa1gkNSXJ4fyu7Fyx1qJiJp/T2CigQeyWdxC3k7rpMFFooYtv1g 1017WsZw8vcN+MBXULJmlOYXPEFSRp0annWZ8/LyxuAMsk/W3bMHAsvAcnvB0R9/MjEF XmdvTAG+bPt4atYc5I+LkpAEAf82QEXMbPwEeui6vtjUh0QMgEj3voiC8VKlVpmYUe8m vuh/5GbtmeRajX2bl77XJSZiJCoff6kAP1TMCinORperWBnH0Sd9vYQeTDns6wHREUVR 15aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=TtETcwaZBeMEWfIYBHEIECw7Eyj9loaUv6MQlZZevNMj0BABAsWlGbDj6nSGdMUZZC bkt5XSyK2fTdjk7QgatGJpEVKO4LcdhUHCOsQutgNdnPFV6cgOFUVfPDyOI3RH2FMbs6 pzwQ9WpeGClZHK6wqaTy+3T2Ha+BGFvFqLgJJcnSv+eREyWv/HPirj7jD/9e1QlKFx/d DJcEo5P0E9UvGU1m9MQrlQD6w8Ems/XMu6NlL8vMT7KVmF27sRVt1IeR8pS3pDmHM/Bb m+le8764MP/SkuJuIVerAz2K17WpQfxwL9mLyt6zTtD9vsE268afGqk6/GlE0gAuhmEJ RJWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KwwjhB+5; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cm13-20020a056a00338d00b0068824f6f3c9si1287682pfb.97.2023.08.12.14.10.00; Sat, 12 Aug 2023 14:10:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KwwjhB+5; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231299AbjHLUHZ (ORCPT + 99 others); Sat, 12 Aug 2023 16:07:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231209AbjHLUGq (ORCPT ); Sat, 12 Aug 2023 16:06:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C237E19B1 for ; Sat, 12 Aug 2023 13:06:24 -0700 (PDT) Message-ID: <20230812195729.454136685@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; b=KwwjhB+5EBP2+E6m+pPVbNUT+KH1rgAxGQyN1QrBB9Ka6OHxFKfeJ5Ru3/JCV2iv6duy+9 tOI2qthFV9X24FJ/XQa1RYnjm3yTgnmng1zDzo8XpG29+FExSvyVjvRAUoZ403sK7R1dxs WjB/GZ3PfGOyi4jcfD3nbiZ1Eijk6MIvZ8HqAE7iW5WIUuLXSEEhcfzHcJ5rNTDIRaaE+e ltT/hzotkRoJCsiUUJI5dHWzPXX46qdLPmafFfTu04JMj+WFAuSl9INg9ZE4SCpf9oxoJ8 HI3yegQpKp/I2k3gmzH80CF1cuV/UnEgY0njj+sdB9ocj/Pei4wGdRRJqY9isA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870368; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; b=g5Ud4QdNP6SrpVc3hyF6u1xQMY7Ll8PMJXj1UL3NgTsRplA5PxEwSWjhmzyXNzy/AAMeWT fCL9CzRsOOcC4GBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 33/37] x86/microcode: Protect against instrumentation References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:27 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774059120616729275 X-GMAIL-MSGID: 1774059120616729275 From: Thomas Gleixner The wait for control loop in which the siblings are waiting for the microcode update on the primary thread must be protected against instrumentation as instrumentation can end up in #INT3, #DB or #PF, which then returns with IRET. That IRET reenables NMI which is the opposite of what the NMI rendezvouz is trying to achieve. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 112 ++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 28 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -341,53 +341,65 @@ struct ucode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); +static unsigned int loops_per_usec; static atomic_t late_cpus_in; -static bool wait_for_cpus(atomic_t *cnt) +static noinstr bool wait_for_cpus(atomic_t *cnt) { - unsigned int timeout; + unsigned int timeout, loops; - WARN_ON_ONCE(atomic_dec_return(cnt) < 0); + WARN_ON_ONCE(raw_atomic_dec_return(cnt) < 0); for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (!atomic_read(cnt)) + if (!raw_atomic_read(cnt)) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % 1000)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } /* Prevent the late comers to make progress and let them time out */ - atomic_inc(cnt); + raw_atomic_inc(cnt); return false; } -static bool wait_for_ctrl(void) +static noinstr bool wait_for_ctrl(void) { - unsigned int timeout; + unsigned int timeout, loops; for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + if (raw_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % 1000)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } return false; } -static void ucode_load_secondary(unsigned int cpu) +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr bool ucode_load_secondary_wait(unsigned int ctrl_cpu) { - unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); - enum ucode_state ret; - /* Initial rendevouz to ensure that all CPUs have arrived */ if (!wait_for_cpus(&late_cpus_in)) { - pr_err_once("Microcode load: %d CPUs timed out\n", - atomic_read(&late_cpus_in) - 1); this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return; + return false; } /* @@ -397,9 +409,33 @@ static void ucode_load_secondary(unsigne * scheduler, watchdogs etc. There is no way to safely evacuate the * machine. */ - if (!wait_for_ctrl()) - panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + if (wait_for_ctrl()) + return true; + + instrumentation_begin(); + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + instrumentation_end(); +} +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr void ucode_load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = raw_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + if (!ucode_load_secondary_wait(ctrl_cpu)) { + instrumentation_begin(); + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + instrumentation_end(); + return; + } + + /* Primary thread completed. Allow to invoke instrumentable code */ + instrumentation_begin(); /* * If the primary succeeded then invoke the apply() callback, * otherwise copy the state from the primary thread. @@ -411,6 +447,7 @@ static void ucode_load_secondary(unsigne this_cpu_write(ucode_ctrl.result, ret); this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + instrumentation_end(); } static void ucode_load_primary(unsigned int cpu) @@ -449,25 +486,43 @@ static void ucode_load_primary(unsigned } } -static bool microcode_update_handler(void) +static noinstr bool microcode_update_handler(void) { - unsigned int cpu = smp_processor_id(); + unsigned int cpu = raw_smp_processor_id(); - if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + if (raw_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) { + instrumentation_begin(); ucode_load_primary(cpu); - else + instrumentation_end(); + } else { ucode_load_secondary(cpu); + } + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + return true; } -bool microcode_nmi_handler(void) +/* + * Protection against instrumentation is required for CPUs which are not + * safe against an NMI which is delivered to the secondary SMT sibling + * while the primary thread updates the microcode. Instrumentation can end + * up in #INT3, #DB and #PF. The IRET from those exceptions reenables NMI + * which is the opposite of what the NMI rendevouz is trying to achieve. + * + * The primary thread is safe versus instrumentation as the actual + * microcode update handles this correctly. It's only the sibling code + * path which must be NMI safe until the primary thread completed the + * update. + */ +bool noinstr microcode_nmi_handler(void) { - if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) return false; - this_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.nmi_enabled, false); return microcode_update_handler(); } @@ -494,6 +549,7 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* * Take a snapshot before the microcode update in order to compare and From patchwork Sat Aug 12 19:59:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134963 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904707vqi; Sat, 12 Aug 2023 14:32:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHOwgCbl1uJoTXUYLioHeLg7oiWNqdUzQlEcgyn6uTLKLuqq+Wh3+EQ+bsqXzGxE99R/2HB X-Received: by 2002:a05:6a20:320e:b0:13b:79dc:4538 with SMTP id hl14-20020a056a20320e00b0013b79dc4538mr4496244pzc.62.1691875977910; Sat, 12 Aug 2023 14:32:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875977; cv=none; d=google.com; s=arc-20160816; b=cUDsJZOvUoFLdwPdL9r05uOm8NPVnzN7YncjwCw8us50DBMJrrqIHLK37y5A4uGoo3 AUHXm9vrJdwJzMNgfmvi4HVO/hEqFHoGmsOUeWkAnlBTLEjatjwx/lPm1QjpCQSsCpaH WipVvttkgH7EMP4nCHysVkmrtJLeT29j7EASAptSaO6SFAJqEjhwf01h/sGk2c8uFpMG Bcml7PJDRpcC2g7ThaI8hRKVTXUyTczAK0NV7NJlj7N5CBW9G9BxgYx2uVmcPi+Hnqvi J57yvQwaZhdIwYxkwsWVmBoLI3dk5p+MZBeK90dp/veRTceLh3c/BuaYlE6B4bifWV+P skpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ad2nYm8qlvD7vUCrpLZZfynt58mvDeIySR0Zislle5k=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=tnZgq6+hrJrfItPqz7M0Z11i8Tk+U/A9xIknqH1bpd4/hpKJ1/mUAO8m6WNy1HHu3A fHbxFPIdr2rjp8UTBF2Bfm0H0Nhu0QE2h3rkLeuzs38+bWzKm3yiM0/XkQdlMICwfwFK kgJbWFTMfSdmAnbVrMXd672I6AUvS/aDE0q207Bob8PwigExx36WNKtqS+SWfoOsXF1l b/bt1ng+fwSABkNVvtdyjxoEblCnuGxLUsYzp7aikNa8ZEV6klF0WqpJ4kYKgCkiGYg/ OMjVi5PSZfqKKO/swiR62HfgldWwO/lhd7U3gdgKwbxtIbJDsxIBMmqeArHhMGRe/hyb et8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="H/8c1sqo"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j190-20020a6380c7000000b005577ad28a97si5582669pgd.633.2023.08.12.14.32.44; Sat, 12 Aug 2023 14:32:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="H/8c1sqo"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231182AbjHLUGy (ORCPT + 99 others); Sat, 12 Aug 2023 16:06:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231239AbjHLUGp (ORCPT ); Sat, 12 Aug 2023 16:06:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5D0A170C for ; Sat, 12 Aug 2023 13:06:23 -0700 (PDT) Message-ID: <20230812195729.512632124@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ad2nYm8qlvD7vUCrpLZZfynt58mvDeIySR0Zislle5k=; b=H/8c1sqo/pB7GrLVFZYNapjMORyLh3Ddt07Y3godhlLNGr/xRMkZu7loqb2mn0VdYjnK0W mw3cg8Wo4pnKKnWmHh7bTJug1sMl92v22mb09Fi3rc9ETOjVkY8TC19pg1+VG3wNNFhnFP QA/C7NX2GkMJLJH7B/XpDSdL482fa1gfxqXiItsu0VCsUv740BT7QEZwrTQFfidn24tA7J r3K8VpYRCdt6h0wIbbEoLqOZ2kZiQBZbRxpVLn3+1uVnMta9sB1bt5Ju+Wy5GMTIlFXlQD zpfHdBT3PERL8fgGQvZWytHALtk8qaXwz4qQAG/xOy/ocLKKDOUfafx2LVvEHw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ad2nYm8qlvD7vUCrpLZZfynt58mvDeIySR0Zislle5k=; b=a23JQp9H80BMWWvd6gaOQ7bMea4kRZ2gC7x7OCmSetUPGxWsZ9LYj68kUqlmIR48N1eyZU 7srT2AzDJCOlmqAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 34/37] x86/apic: Provide apic_force_nmi_on_cpu() References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:29 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060545495025333 X-GMAIL-MSGID: 1774060545495025333 From: Thomas Gleixner When SMT siblings are soft-offlined and parked in one of the play_dead() variants they still react on NMI, which is problematic on affected Intel CPUs. The default play_dead() variant uses MWAIT on modern CPUs, which is not guaranteed to be safe when updated concurrently. Right now late loading is prevented when not all SMT siblings are online, but as they still react on NMI, it is possible to bring them out of their park position into a trivial rendevouz handler. Provide a function which allows to do that. I does sanity checks whether the target is in the cpus_booted_once_mask and whether the APIC driver supports it. Mark X2APIC and XAPIC as capable, but exclude 32bit and the UV and NUMACHIP variants as that needs feedback from the relevant experts. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 +++++ arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/ipi.c | 9 ++++++++- arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + 5 files changed, 17 insertions(+), 1 deletion(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -301,6 +301,9 @@ struct apic { enum apic_delivery_modes delivery_mode; bool dest_mode_logical; + /* Allows to send an NMI to an "offline" CPU which hangs in *play_dead() */ + bool nmi_to_offline_cpu; + u32 (*calc_dest_apicid)(unsigned int cpu); /* ICR related functions */ @@ -505,6 +508,8 @@ extern void default_ioapic_phys_id_map(p extern int default_cpu_present_to_apicid(int mps_cpu); extern int default_check_phys_apicid_present(int phys_apicid); +void apic_send_nmi_to_offline_cpu(unsigned int cpu); + #endif /* CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_SMP --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -138,6 +138,7 @@ static struct apic apic_flat __ro_after_ .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = default_inquire_remote_apic, @@ -229,6 +230,7 @@ static struct apic apic_physflat __ro_af .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = default_inquire_remote_apic, --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -95,8 +95,15 @@ void native_send_call_func_ipi(const str apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } +void apic_send_nmi_to_offline_cpu(unsigned int cpu) +{ + if (WARN_ON_ONCE(!apic->nmi_to_offline_cpu)) + return; + if (WARN_ON_ONCE(!cpumask_test_cpu(cpu, &cpus_booted_once_mask))) + return; + apic->send_IPI(cpu, NMI_VECTOR); +} #endif /* CONFIG_SMP */ - static inline int __prepare_ICR2(unsigned int mask) { return SET_XAPIC_DEST_FIELD(mask); --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -264,6 +264,7 @@ static struct apic apic_x2apic_cluster _ .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = NULL, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -188,6 +188,7 @@ static struct apic apic_x2apic_phys __ro .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = NULL, From patchwork Sat Aug 12 19:59:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134965 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1904825vqi; Sat, 12 Aug 2023 14:33:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEX3vKjkUay6b3ICbzYLF/qH3ATDuh4wfBoHpz1viD3oop9TJtRvcQdUzVY1y4GG4+QJvUw X-Received: by 2002:a05:6a20:42a2:b0:143:f4dd:dfae with SMTP id o34-20020a056a2042a200b00143f4dddfaemr1131939pzj.43.1691875993909; Sat, 12 Aug 2023 14:33:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691875993; cv=none; d=google.com; s=arc-20160816; b=pJN7+cekqwkkFu5Hy1je9FzqRto6L002PDoARcS/Y/zRNKoXfN+hoyAOop1Y+GwRYE ru6mEVHPh+OsRccUMPo6qU2iFQzlrdbXa0hvmOc/wWplV94muBKArUX8Aj7/Js+6V5EP jOdRfDSXsXWd3hw+u2CicXPxnP2H09UKXCIGkGHOjnXQB+dEyrFA7hQDOC7sGbADllKS JLKn7IjpkjKPgDtwtpKv8gZD/Ojkn+aVtoi+hgNQcNpDjCxld9LDT5zbKlbj+MwYZH4u SA32wzgOBKKresbieQIf1fKjsjHARxuDoiM3qEDw6paKPANz4JL6UUIfvdS3mBL94tT8 Okog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Cmgw61F2ex4w7spmiBvMIKhnwIjtZvFaMPXmda/ZPis=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=ahdmF2vIBzirF4W+JpxoqbH21inTg5gUFksnnvEUBhnq/FtE1Npz2ua8lfUTnaNS7Y 4GoyLOt0FBrLzx9KBRKrdf7WfksCw814NP4RprlXdPhvBzFgCrHF2yFrfJUBCiHeFmKd 2RPUMJH5oZkQVAaAFN7xz83tO7m00NlMrj62ArFab+XItyV6najc8kp78I80o0de+BPM N4lBV7nLpO9OguTppVdkOnke46zi93mndXXYC7I47OO9a1ywTaCVLXTGrxkJ9GLaVeJq 83qOUbkPs6VyhdToAyrXGdx6IBLYXKUY7AqgTUS9+QIddotLdBT5aC3ShbtquzIDSEJD fwZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=iqh3BamR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k70-20020a638449000000b0053ee9b21820si5390874pgd.72.2023.08.12.14.33.01; Sat, 12 Aug 2023 14:33:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=iqh3BamR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbjHLURK (ORCPT + 99 others); Sat, 12 Aug 2023 16:17:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229920AbjHLURE (ORCPT ); Sat, 12 Aug 2023 16:17:04 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E3321FC1 for ; Sat, 12 Aug 2023 13:16:46 -0700 (PDT) Message-ID: <20230812195729.570237823@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870371; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Cmgw61F2ex4w7spmiBvMIKhnwIjtZvFaMPXmda/ZPis=; b=iqh3BamRomj3miBly6PYKLF9Y6bvNg0deg5fdA3ZhDUqn5DaWEoSMaJev5h+UH0GeWJERO irSpJDVFih3ubppe18S9bdYmAM0uXBtWS+qy02ELu0l3/Upm5RzeCCqzjutWywITFV5UJv nLaB4XENc64Pk7GYjiS04uwtP5pgurIWCDr2oWBfEThbBUizoHJQ4hOTb8h0mKtQczrsLD jIb8kOkJZFudG5RidA4i5GwIk5b2/Ae1KOIzsT7mYoC4gs/1Z/DWf4XTUW5eAyARqCZfir 6DIKVqXrJOcLcOLHZTCh6hBxRcIMpYICLmAzNV70OCnVzVUdwKwEMgZ/5Ms2oA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870371; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Cmgw61F2ex4w7spmiBvMIKhnwIjtZvFaMPXmda/ZPis=; b=aK++AxZY/y8O/qfbk39tVvY3BUbDOUuHEKCpSRPJ9hiAv64yIMr5d0uQ7bICtIJeGQ+Fr0 5W66kdXaKaXba2CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 35/37] x86/microcode: Handle "offline" CPUs correctly References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:30 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774060562319019394 X-GMAIL-MSGID: 1774060562319019394 From: Thomas Gleixner Offline CPUs need to be parked in a safe loop when microcode update is in progress on the primary CPU. Currently offline CPUs are parked in 'mwait_play_dead()', and for Intel CPUs, its not a safe instruction, because 'mwait' instruction can be patched in the new microcode update that can cause instability. - Adds a new microcode state 'UCODE_OFFLINE' to report status on per-cpu basis. - Force NMI on the offline CPUs. Wakeup offline CPUs while the update is in progress and then return them back to 'mwait_play_dead()' after microcode update is complete. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 1 arch/x86/kernel/cpu/microcode/core.c | 112 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 1 arch/x86/kernel/nmi.c | 5 + 4 files changed, 113 insertions(+), 6 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -76,6 +76,7 @@ static inline void show_ucode_info_early #endif /* !CONFIG_CPU_SUP_INTEL */ bool microcode_nmi_handler(void); +void microcode_offline_nmi_handler(void); #ifdef CONFIG_MICROCODE_LATE_LOADING DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -341,8 +341,9 @@ struct ucode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); +static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; -static atomic_t late_cpus_in; +static cpumask_t cpu_offline_mask; static noinstr bool wait_for_cpus(atomic_t *cnt) { @@ -450,7 +451,7 @@ static noinstr void ucode_load_secondary instrumentation_end(); } -static void ucode_load_primary(unsigned int cpu) +static void __ucode_load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -486,6 +487,67 @@ static void ucode_load_primary(unsigned } } +static bool ucode_kick_offline_cpus(unsigned int nr_offl) +{ + unsigned int cpu, timeout; + + for_each_cpu(cpu, &cpu_offline_mask) { + /* Enable the rendevouz handler and send NMI */ + per_cpu(ucode_ctrl.nmi_enabled, cpu) = true; + apic_send_nmi_to_offline_cpu(cpu); + } + + /* Wait for them to arrive */ + for (timeout = 0; timeout < (USEC_PER_SEC / 2); timeout++) { + if (atomic_read(&offline_in_nmi) == nr_offl) + return true; + udelay(1); + } + /* Let the others time out */ + return false; +} + +static void ucode_release_offline_cpus(void) +{ + unsigned int cpu; + + for_each_cpu(cpu, &cpu_offline_mask) + per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE; +} + +static void ucode_load_primary(unsigned int cpu) +{ + unsigned int nr_offl = cpumask_weight(&cpu_offline_mask); + bool proceed = true; + + /* Kick soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + proceed = ucode_kick_offline_cpus(nr_offl); + + /* If the soft-offlined CPUs did not respond, abort */ + if (proceed) + __ucode_load_primary(cpu); + + /* Unconditionally release soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + ucode_release_offline_cpus(); +} + +/* + * Minimal stub rendevouz handler for soft-offlined CPUs which participate + * in the NMI rendevouz to protect against a concurrent NMI on affected + * CPUs. + */ +void noinstr microcode_offline_nmi_handler(void) +{ + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) + return; + raw_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.result, UCODE_OFFLINE); + raw_atomic_inc(&offline_in_nmi); + wait_for_ctrl(); +} + static noinstr bool microcode_update_handler(void) { unsigned int cpu = raw_smp_processor_id(); @@ -542,6 +604,7 @@ static int ucode_load_cpus_stopped(void static int ucode_load_late_stop_cpus(void) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; @@ -549,6 +612,7 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&offline_in_nmi, 0); loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* @@ -571,6 +635,7 @@ static int ucode_load_late_stop_cpus(voi case UCODE_UPDATED: updated++; break; case UCODE_TIMEOUT: timedout++; break; case UCODE_OK: siblings++; break; + case UCODE_OFFLINE: offline++; break; default: failed++; break; } } @@ -582,6 +647,13 @@ static int ucode_load_late_stop_cpus(voi /* Nothing changed. */ if (!failed && !timedout) return 0; + + nr_offl = cpumask_weight(&cpu_offline_mask); + if (offline < nr_offl) { + pr_warn("%u offline siblings did not respond.\n", + nr_offl - atomic_read(&offline_in_nmi)); + return -EIO; + } pr_err("Microcode update failed: %u CPUs failed %u CPUs timed out\n", failed, timedout); return -EIO; @@ -615,19 +687,49 @@ static int ucode_load_late_stop_cpus(voi * modern CPUs is using MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. * - * 2) Initialize the per CPU control structure + * As soft-offlined CPUs still react on NMIs, the SMT sibling + * restriction can be lifted when the vendor driver signals to use NMI + * for rendevouz and the APIC provides a mechanism to send an NMI to a + * soft-offlined CPU. The soft-offlined CPUs are then able to + * participate in the rendezvouz in a trivial stub handler. + * + * 2) Initialize the per CPU control structure and create a cpumask + * which contains "offline"; secondary threads, so they can be handled + * correctly by a control CPU. */ static bool ucode_setup_cpus(void) { struct ucode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; + bool allow_smt_offline; unsigned int cpu; + allow_smt_offline = microcode_ops->nmi_safe || + (microcode_ops->use_nmi && apic->nmi_to_offline_cpu); + + cpumask_clear(&cpu_offline_mask); + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + /* + * Offline CPUs sit in one of the play_dead() functions + * with interrupts disabled, but they still react on NMIs + * and execute arbitrary code. Also MWAIT being updated + * while the offline CPU sits there is not necessarily safe + * on all CPU variants. + * + * Mark them in the offline_cpus mask which will be handled + * by CPU0 later in the update process. + * + * Ensure that the primary thread is online so that it is + * guaranteed that all cores are updated. + */ if (!cpu_online(cpu)) { - if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { - pr_err("CPU %u not online\n", cpu); + if (topology_is_primary_thread(cpu) || !allow_smt_offline) { + pr_err("CPU %u not online, loading aborted\n", cpu); return false; } + cpumask_set_cpu(cpu, &cpu_offline_mask); + per_cpu(ucode_ctrl, cpu) = ctrl; + continue; } /* --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -17,6 +17,7 @@ enum ucode_state { UCODE_NFOUND, UCODE_ERROR, UCODE_TIMEOUT, + UCODE_OFFLINE, }; struct microcode_ops { --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -502,8 +502,11 @@ DEFINE_IDTENTRY_RAW(exc_nmi) if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) raw_atomic_long_inc(&nsp->idt_calls); - if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) + if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) { + if (microcode_nmi_handler_enabled()) + microcode_offline_nmi_handler(); return; + } if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { this_cpu_write(nmi_state, NMI_LATCHED); From patchwork Sat Aug 12 19:59:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134992 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1954262vqi; Sat, 12 Aug 2023 17:17:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGMwSa4a8K2HtnGmbOkIM8UscKKOK3LxNUq5gi3o4+/284H64xm+6xt6KkkeOO4okvRwjZl X-Received: by 2002:a17:906:7489:b0:974:183a:54b6 with SMTP id e9-20020a170906748900b00974183a54b6mr4545723ejl.33.1691885838730; Sat, 12 Aug 2023 17:17:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691885838; cv=none; d=google.com; s=arc-20160816; b=xHogV0kdLGICMUUGgNNzLzz9lxieQbKfG8Hx7goRygs9z+hOf05FH3INyRZi3wRymk ggnSOjy+0urs/MZlODgJ/C+niY9JAIfRT++vzbchwGaUoPL92wc0iRU7ezNWRf1M7sTD BPBSqsrVALL5HwkemrJgZbciBW8Gl+ExKvt5lobSADtqDg9QLZaZDlqGbf6xw1X0qAxY 4qZ6OD/xsNR+VbR+dxv6HwxYnJwhQWwaB37ISVPYIolQ4CroWR+Cmcgfz0qeV4woyyXB 6Ghc0zpvMWQgPQXKuAdf49P9KlTIzf81GCi4X0fr7rwS1cLShyZA9z2HIqOXWXpqYygc mBdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=vkb5eya832wOkrcECHFcR/66ZtKy/0rcIUb77ri1flg=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=LEAloTLo6esWr6dFdrPeNJawK6ctZ57ez1bgEE0XES31Ev5XnQi2BDfmNkj3NT7a7S OKlFr/TOGMboIdDPyoBGcmA/ptAQuRaV17wsI1jG7Pznoaq4okZTcdFk4yEPXGm9wnAh LVrDMPt2CyHg01tKnlNJr5r0H45RlPeL/0U61itPcPHIrCWtQ9AcWxfOMhad0SkY6EsT pGKF4uDht44wW+Loc/ayoSFLL2EwSx14snIhYS+g7K4j8AScOM+8SOFKK49Wr9mRWRm7 JFLg6oaH5oQhntcKcySLVQ9SJYTcW1GiVcMfmd0Cx1wJF3VoDVbrbzT0cKfSKeMjtR8q MATQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="yda/B0xC"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=HiTEdQye; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cd24-20020a170906b35800b0099cdab19fd5si5505481ejb.1034.2023.08.12.17.16.54; Sat, 12 Aug 2023 17:17:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="yda/B0xC"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=HiTEdQye; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbjHLURE (ORCPT + 99 others); Sat, 12 Aug 2023 16:17:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230059AbjHLURD (ORCPT ); Sat, 12 Aug 2023 16:17:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C29E1BFC for ; Sat, 12 Aug 2023 13:16:46 -0700 (PDT) Message-ID: <20230812195729.634757390@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870373; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vkb5eya832wOkrcECHFcR/66ZtKy/0rcIUb77ri1flg=; b=yda/B0xCcjVeOYF3HOrlrPoH5/8PbFevw2w8zSd5Vy/w+OtMSr8VsVqXH4WXq3tEo4wmBm pHIgcHKek4usBfQupJGMQKn9VvZ0SemX0RzxfgEoiBuPAwjfuNr9n2W1azQy2b2HJijbEU zwlweP97R/GaRYE5xn25lLsMDuaDghMYpprmGrsLpaeWQIHb+895OD2O+xMzxSgsoM4TzY FUNisuwbbuzFvT6IgfpbMvKq1mgTAAVa/XlVwFe1MTOysb6P0cRcM/NpsqvQ9x7gZTHYO3 ljzI4m/cf+O9j02xuqgzF0fpSkIFfYdFiPUPIXTHoRk+AHGyjxWUKe+ub9LWqQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870373; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=vkb5eya832wOkrcECHFcR/66ZtKy/0rcIUb77ri1flg=; b=HiTEdQyeeiEDI0HR94QL2i6Rzdnl2YxBJWK3vmKI4M0iJF3bpHi7iebWfrAzOXvtLb/tjW mbMR6YimNoUW3fAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 36/37] x86/microcode: Prepare for minimal revision check References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:32 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774070885345011922 X-GMAIL-MSGID: 1774070885345011922 From: Thomas Gleixner Applying microcode late can be fatal for the running kernel when the update changes functionality which is in use already in a non-compatible way, e.g. by removing a CPUID bit. There is no way for admins which do not have access to the vendors deep technical support to decide whether late loading of such a microcode is safe or not. Intel has added a new field to the microcode header which tells the minimal microcode revision which is required to be active in the CPU in order to be safe. Provide infrastructure for handling this in the core code and a command line switch which allows to enforce it. If the update is considered safe the kernel is not tainted and the annoying warning message not emitted. If it's enforced and the currently loaded microcode revision is not safe for late loading then the load is aborted. Signed-off-by: Thomas Gleixner --- Documentation/admin-guide/kernel-parameters.txt | 5 ++++ arch/x86/Kconfig | 23 ++++++++++++++++++- arch/x86/kernel/cpu/microcode/amd.c | 3 ++ arch/x86/kernel/cpu/microcode/core.c | 29 ++++++++++++++++++------ arch/x86/kernel/cpu/microcode/intel.c | 3 ++ arch/x86/kernel/cpu/microcode/internal.h | 3 ++ 6 files changed, 58 insertions(+), 8 deletions(-) --- --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3239,6 +3239,11 @@ mga= [HW,DRM] + microcode.force_minrev= [X86] + Format: + Enable or disable the microcode minimal revision + enforcement for the runtime microcode loader. + min_addr=nn[KMG] [KNL,BOOT,IA-64] All physical memory below this physical address is ignored. --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1320,7 +1320,28 @@ config MICROCODE_LATE_LOADING is a tricky business and should be avoided if possible. Just the sequence of synchronizing all cores and SMT threads is one fragile dance which does not guarantee that cores might not softlock after the loading. Therefore, - use this at your own risk. Late loading taints the kernel too. + use this at your own risk. Late loading taints the kernel unless the + microcode header indicates that it is safe for late loading via the + minimal revision check. This minimal revision check can be enforced on + the kernel command line with "microcode.minrev=Y". + +config MICROCODE_LATE_FORCE_MINREV + bool "Enforce late microcode loading minimal revision check" + default n + depends on MICROCODE_LATE_LOADING + help + To prevent that users load microcode late which modifies already + in use features, newer microcodes have a minimum revision field + in the microcode header, which tells the kernel which minimum + revision must be active in the CPU to safely load that new microcode + late into the running system. If disabled the check will not + be enforced but the kernel will be tainted when the minimal + revision check fails. + + This minimal revision check can also be controlled via the + "microcode.minrev" parameter on the kernel command line. + + If unsure say Y. config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -919,6 +919,9 @@ static enum ucode_state request_microcod enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; + if (force_minrev) + return UCODE_NFOUND; + if (c->x86 >= 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,6 +46,9 @@ static struct microcode_ops *microcode_ops; static bool dis_ucode_ldr = true; +bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV); +module_param(force_minrev, bool, S_IRUSR | S_IWUSR); + bool initrd_gone; /* @@ -601,15 +604,17 @@ static int ucode_load_cpus_stopped(void return 0; } -static int ucode_load_late_stop_cpus(void) +static int ucode_load_late_stop_cpus(bool is_safe) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); + if (!is_safe) { + pr_err("Late microcode loading without minimal revision check.\n"); + pr_err("You should switch to early loading, if possible.\n"); + } atomic_set(&late_cpus_in, num_online_cpus()); atomic_set(&offline_in_nmi, 0); @@ -659,7 +664,9 @@ static int ucode_load_late_stop_cpus(voi return -EIO; } - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + if (!is_safe || failed || timedout) + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("Microcode load: updated on %u primary CPUs with %u siblings\n", updated, siblings); if (failed || timedout) { pr_err("Microcode load incomplete. %u CPUs timed out or failed\n", @@ -753,9 +760,17 @@ static int ucode_load_late_locked(void) return -EBUSY; ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); - if (ret != UCODE_NEW) - return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; - return ucode_load_late_stop_cpus(); + + switch (ret) { + case UCODE_NEW: + case UCODE_NEW_SAFE: + break; + case UCODE_NFOUND: + return -ENOENT; + default: + return -EBADFD; + } + return ucode_load_late_stop_cpus(ret == UCODE_NEW_SAFE); } static ssize_t reload_store(struct device *dev, --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -551,6 +551,9 @@ static enum ucode_state read_ucode_intel int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; + if (force_minrev) + return UCODE_NFOUND; + while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -13,6 +13,7 @@ struct device; enum ucode_state { UCODE_OK = 0, UCODE_NEW, + UCODE_NEW_SAFE, UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, @@ -36,6 +37,8 @@ struct microcode_ops { use_nmi : 1; }; +extern bool force_minrev; + extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); From patchwork Sat Aug 12 19:59:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134952 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1898784vqi; Sat, 12 Aug 2023 14:14:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHr9nIWyRCKxWVlGaJkIMmHBJX6Tf4f6oMuhbYexEFFnAsxoxkvqjjfRjvBARXd5VMAZkV4 X-Received: by 2002:a05:6a00:1402:b0:687:5fdb:59ee with SMTP id l2-20020a056a00140200b006875fdb59eemr4739321pfu.12.1691874873187; Sat, 12 Aug 2023 14:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691874873; cv=none; d=google.com; s=arc-20160816; b=Kd6caEne0DD0Kb6XijtBkwYGW+CYYprFsJljwvo/M0+tPMIv1PdMtEV6z+twH6dDlO xsc+jjh7hXYa92ApbZKjGPpeglyyxpf8QewImnclBezDbsGHveZ0k9tVqd+XRDsS3/Lq LZBqRf5kXhW56yG4eFEeMNsldFCT6nOvUCfTr5aYRXQjqWdvEQAQ+KJzaLXOxhTNlCAT BmTZkSVLVq175RyHCr1o8mXkTeoOQrOSzcZJeEflqZvv8QMRykIe4GMXWuLvnG3WdPUd cwAiKhFOqQPWHBD053mqB+u5a0ywOURXSlVxC2f4Ysyh41yyOt7Zh4a8jghkFYowDegP URsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=w1SyTFpa9lrhJ4lGTg0lf2YQXOnASSGU3DRXcCp/oHw=; fh=yVae3u0BRTnDkPuniOcxLkA1wgvMDfOA8XxNsc4ELm4=; b=oZjXiO1fazj1e7yId6BNWNwvi9YDdYK83sJcsSqWVwtwBJxg3nT6J2SabAw98NmwqL b7ZlpLHaPxEfVleREpzcsGJFgMQXqbwqk4eamhzmzaNjVQ5CHTk7F1cdHPSGdcPM9vwa Dymen/99D0pk41dLiL9mmtd2R/Yp8UU+drCYavCddM1KBcGz56TbJRT7WMwA4fk0k599 ueZoJ3nuPPL1dC2P/ke+NrnUlqBDIZtCU6imX7Qv8RRRiIuHQZEBgU+aSgf30aTTcN26 3zleFM8bUYdMls0IrJQIGzWjEr+vrSwLMunL+cX55mQRO/ZQJvzjP/RYu9HhPgzYradH mfkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=lkdpuxaI; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y8-20020a056a00190800b006870c16c9d4si5546777pfi.123.2023.08.12.14.14.19; Sat, 12 Aug 2023 14:14:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=lkdpuxaI; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231409AbjHLURG (ORCPT + 99 others); Sat, 12 Aug 2023 16:17:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230395AbjHLURE (ORCPT ); Sat, 12 Aug 2023 16:17:04 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DDDC1BFD for ; Sat, 12 Aug 2023 13:16:46 -0700 (PDT) Message-ID: <20230812195729.693640265@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870374; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=w1SyTFpa9lrhJ4lGTg0lf2YQXOnASSGU3DRXcCp/oHw=; b=lkdpuxaIgkKAw5/H2Cjjkkt3E9IS48OQmBpLVgwS6/4waEGKkgxjV5zag6Av25xXqGHls3 T+wg6tYpc1Q8KPV0KiL/kvbBkJZj3Pv+mEmIpUG0nw2OhxJ55Rx0F2SqhgvpZy0LYjQYgR 1LI2B5WVo/34ZrOAnr/H1WR/S3x3unOOz23bvMOMud5iPKI03OuSfKwH4pYd8nt6tmRbSI nyHzL4WVXcw7/a6NHGnNEmk/krmItPAOCUkgkM6nvbA7m5/V6gEhYucNFx2bHnJMH5jfj9 SpCSG4ZF26p21p60IjvgbhyZrfTyd4rZyYys0Ls0H/o1HHzCdmoBaRiLf4z7Yw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870374; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=w1SyTFpa9lrhJ4lGTg0lf2YQXOnASSGU3DRXcCp/oHw=; b=QYYU2YXfHxQxYyLceD1EhSyLtOtNBnYmAgJCVOHPRNZaMURvzcwfUyLeAPdpLpH6V0hF6s GiTOI9G/SE/bbnAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 37/37] x86/microcode/intel: Add a minimum required revision for late-loads References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:59:34 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774059386775586502 X-GMAIL-MSGID: 1774059386775586502 From: Ashok Raj In general users don't have the necessary information to determine whether late loading of a new microcode version is safe and does not modify anything which the currently running kernel uses already, e.g. removal of CPUID bits or behavioural changes of MSRs. To address this issue, Intel has added a "minimum required version" field to a previously reserved field in the microcode header. Microcode updates should only be applied if the current microcode version is equal to, or greater than this minimum required version. Thomas made some suggestions on how meta-data in the microcode file could provide Linux with information to decide if the new microcode is suitable candidate for late loading. But even the "simpler" option requires a lot of metadata and corresponding kernel code to parse it, so the final suggestion was to add the 'minimum required version' field in the header. When microcode changes visible features, microcode will set the minimum required version to its own revision which prevents late loading. Old microcode blobs have the minimum revision field always set to 0, which indicates that there is no information and the kernel considers it as unsafe. This is a pure OS software mechanism. The hardware/firmware ignores this header field. For early loading there is no restriction because OS visible features are enumerated after the early load and therefor a change has no effect. The check is always enabled, but by default not enforced. It can be enforced via Kconfig or kernel command line. If enforced, the kernel refuses to late load microcode with a minium required version field which is zero or when the currently loaded microcode revision is smaller than the minimum required revision. If not enforced the load happens independent of the revision check to stay compatible with the existing behaviour, but it influences the decision whether the kernel is tainted or not. If the check signals that the late load is safe, then the kernel is not tainted. Early loading is not affected by this. [ tglx: Massaged changelog and fixed up the implementation ] Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 3 +- arch/x86/kernel/cpu/microcode/intel.c | 37 ++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -36,7 +36,8 @@ struct microcode_header_intel { unsigned int datasize; unsigned int totalsize; unsigned int metasize; - unsigned int reserved[2]; + unsigned int min_req_ver; + unsigned int reserved; }; struct microcode_intel { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -544,16 +544,40 @@ static enum ucode_state apply_microcode_ return ret; } +static bool ucode_validate_minrev(struct microcode_header_intel *mc_header) +{ + int cur_rev = boot_cpu_data.microcode; + + /* + * When late-loading, ensure the header declares a minimum revision + * required to perform a late-load. The previously reserved field + * is 0 in older microcode blobs. + */ + if (!mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Microcode header does not specify a required min version\n"); + return false; + } + + /* + * Check whether the minimum revision specified in the header is either + * greater or equal to the current revision. + */ + if (cur_rev < mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Current revision 0x%x too old\n", cur_rev); + pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver); + return false; + } + return true; +} + static enum ucode_state read_ucode_intel(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; + bool is_safe, new_is_safe = false; int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - if (force_minrev) - return UCODE_NFOUND; - while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; @@ -596,10 +620,15 @@ static enum ucode_state read_ucode_intel if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; + is_safe = ucode_validate_minrev(&mc_header); + if (force_minrev && !is_safe) + continue; + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; new_mc_size = mc_size; + new_is_safe = is_safe; mc = NULL; } @@ -616,7 +645,7 @@ static enum ucode_state read_ucode_intel return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; - return UCODE_NEW; + return new_is_safe ? UCODE_NEW_SAFE : UCODE_NEW; fail: kvfree(mc);