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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f20-20020a056a00229400b00687357a3793si4900359pfe.347.2023.08.12.03.27.02; Sat, 12 Aug 2023 03:27:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235819AbjHLK0H (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229727AbjHLK0F (ORCPT ); Sat, 12 Aug 2023 06:26:05 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3CED170D; Sat, 12 Aug 2023 03:26:08 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 293A182A9B; Sat, 12 Aug 2023 12:26:07 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:05 +0200 Subject: [PATCH v5 1/8] gpio: pxa: disable pinctrl calls for MMP_GPIO MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-1-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=717; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=KpHlcLrUY59P26MylBMaHpzA91WHfXQj5w9V31CEE9k=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114Ejn0o+sJ9R66MpkeqR5THvpE/2hx19CFsu I+erCRU2huJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4U+wD/4rCSSTNj8ky6MrA4t2w8MZUprN7nQFoRNWTzeT1k/JBeLJD232B4AWHVBaN8s645nc8zZ t/uLIrN77JlBAzm9+qTc97mF3MPZ3bmrxlRLgnqnLWxg+l+B+PmA4GzmoIw7QN1qW6F3De+LPkl yfIMQX653+tM16G8/P4FTzM/jcc4QvVmjuWEjLfv/Ocz0+5BuQxuqODvOVaMFZIsqimCp2ocYdB Uf6Br+DO06FPqtJ1+SEH2fUR8W/D6sR0K0D0dA3syjHqbN1tiUNlc74zJB6zFeZqciFt2f28OoP 27sT3lXuTCuj2CrUvF+Zs7YpfUge+P/fEyubSiAX0yvqfPfb/R5O+xFhGZhqzUwFsQ0r+nFw5UX qg9N5idsmwbelsRjz5UVoBgXymjaq8ehv0k8JkC/iRKAJF6Xe4JLuPSor5s+P4CskhKHBxGz7fR lwE/VpOFmjErezbJtr77NHhla7OGyTqcvkbb08q5AnWX4+Uy8nsBqs3CHEUXKNg60o8xY4PNl4k zCjYDqU7WX2C3rUC/n9iJTKYlCgiproqDqGQ/kq7JgptLm+qYKuD5GctY7ilirzgUm5a32VVenv BOWkAtwezBuJpuJnb0rHbaM5aXDVAuWn5lyetOgXqetp4br3+/PDSRd1BDDieLQsxybkM4N/XRu TXEKM5RqVOxT1oQ== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774018662733953146 X-GMAIL-MSGID: 1774018662733953146 Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting pin direction on MMP either. Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request") Signed-off-by: Duje Mihanović Reviewed-by: Andy Shevchenko Acked-by: Bartosz Golaszewski --- drivers/gpio/gpio-pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index a1630ed4b741..d92650aecb06 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -238,6 +238,7 @@ static bool pxa_gpio_has_pinctrl(void) switch (gpio_type) { case PXA3XX_GPIO: case MMP2_GPIO: + case MMP_GPIO: return false; default: From patchwork Sat Aug 12 10:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 134867 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1639746vqi; Sat, 12 Aug 2023 03:49:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHV8N4jT2d5giJEIla1nfoTEPRO8dXCChqGGVYv3+vgQE+c/VS3kBxHQeiUFcvU9SixqaMT X-Received: by 2002:a17:903:247:b0:1b8:8dbd:e1a0 with SMTP id j7-20020a170903024700b001b88dbde1a0mr5139996plh.13.1691837351445; Sat, 12 Aug 2023 03:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691837351; cv=none; d=google.com; s=arc-20160816; b=hpsaKvaPfJA/7p6p5+0ZJC0iDgHJkMM0yeUxIOyMnJ+YhS1OZAZkcdWAHuVzi+cQSd SRRSj7R44RC9AXhfXfRbi/+Jd4mDPUdWfK/iXtKk5vWCj46QUzDfsgUkBC62voAMOCQT PpkEHbvWbQDKDWVke+iwKY+0dQUNjfSFhZMz/KO3g1NePQRScfgtLvbkxSIvJRt69tST rzry5Uy3yktVH/P8YpdPGVcJindC1ZOEW5kWu53tJPa5CMlfQYvnhE/SP+jos4niyaHu vQSpG9M70FuiZvyF3TtpoHcMMeefBf3an7ExTTG/6Ve/cUPGPq0MrfuSzvvFkTEWMfmD G+Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=k67DB+5Iz8SfVN4j6GPnZqrDh7hs/FsADui/GwnMYlk=; fh=593uhcdDopDTnHSWY155XwSVTEs3hlalECORQKKDDvY=; b=XGdwBCrQJoR0JS2XIqe9f6z87X8bR2TRTUjmjbk/BKaY71g0Y03JK+kMICaY3NQKn2 cr2ccS/wkeGMbPan7mx+misNSc3fKG2xIdXb3eyIVZOXvUR4VbwrRmZMPqIdxBbiaLAo lDDYEOUNeOmTvauUEI1ihuHywZRHYnGXbBqGLax65t1o3MAULXj00oYN2Le+fuhPevQ5 oT3fm4aQUnYsL4GyuLm5y83+TfXX4FzwiHqNP9AllBu5BMXUo45jdnMmobJeYZkIcgoy T412Z+utLIm5ZPpVHpq86C1UwH2hf2c4kJ32Cuxay+5f1J/pwZFPY6CkH0gX81kE6pJc ti8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j7-20020a170903024700b001b89b77ce99si4786441plh.458.2023.08.12.03.48.58; Sat, 12 Aug 2023 03:49:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235037AbjHLK0Y (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236335AbjHLK0I (ORCPT ); Sat, 12 Aug 2023 06:26:08 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B005170D; Sat, 12 Aug 2023 03:26:10 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id CDC218407E; Sat, 12 Aug 2023 12:26:08 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:06 +0200 Subject: [PATCH v5 2/8] clk: mmp: Switch to use struct u32_fract instead of custom one MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-2-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de, Andy Shevchenko X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=12358; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=ixuacWD4Wzo9v++NPDFaZfVWUv2CHv+uQOCbb7DKqhU=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114Ek454LDTJ134PSCEeMuU5JPNMBrGdalIFz lFa8QU/+reJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4QiKD/4mrskwCG/7oMJJ6UqbJ88B3CnzcN3mb27HfV+TmMBQgUbAJZI/eI9xYdURIexFXgNq7ba zRedKvCmciHVg1SMLdHY3APEU2HltU49/AidMswhHXFMtJnwKymfAXssaUcNuX3rd73tR4nufK4 qJ0GEKuI7GNN589eeqUxYLHei9NZYUo+5EzRhGz1XrZYlyXPXYEhQ0S0rmbqQLsN+CDU+WmYkq5 ToCdZ/TFZtAvYifWn6CZGv2oZOPGAws0Egh8mPh+q7ThMzNSiRGDYy4cH8KHqJ93aM/lgZkioWv ok2HjuuSxghWzwxa2j0Uf9GZM/ADfJb21Dc8H4GUcqS+IkDZ46oaACAbGi9E+Ql74h6V60YyV5W FgySGEx1agwAmKEy+hthFB9G1/N8jl5EIKYGf4SqQa8QZRIbd174qpzju5NdD9bcnnZsJYHGcOY HYy5RoRom6gU0WYAfmsmh6uvfjUQcb2vuLZwbVxypbZmt3JGdrq3Y3XaF+Tu4XH/s3hctysdI29 azR1R0lXTfw2HEVuGr3/Ielekn3dTH+eo9pkVcx3N8Yn+8zTGVUXLUYWQremhQdUiEV360n17QO tl5WwXIz3H+aGIc2Ies8z3hcW9KGnB7sJap0GrU1WerP27+h+XkZS9Qs4RYNZJtAGlMFflGQUhx WPfJam6pHpux4Rw== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774020042759713536 X-GMAIL-MSGID: 1774020042759713536 From: Andy Shevchenko The struct mmp_clk_factor_tbl repeats the generic struct u32_fract. Kill the custom one and use the generic one instead. Signed-off-by: Andy Shevchenko Tested-by: Duje Mihanović Signed-off-by: Duje Mihanović --- drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++++++-------------------- drivers/clk/mmp/clk-mmp2.c | 6 ++--- drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++++--------- drivers/clk/mmp/clk-of-pxa168.c | 4 +-- drivers/clk/mmp/clk-of-pxa1928.c | 6 ++--- drivers/clk/mmp/clk-of-pxa910.c | 4 +-- drivers/clk/mmp/clk-pxa168.c | 4 +-- drivers/clk/mmp/clk-pxa910.c | 4 +-- drivers/clk/mmp/clk.h | 10 +++---- 9 files changed, 58 insertions(+), 63 deletions(-) diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 1b90867b60c4..6556f6ada2e8 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate, { struct mmp_clk_factor *factor = to_clk_factor(hw); u64 rate = 0, prev_rate; + struct u32_fract *d; int i; for (i = 0; i < factor->ftbl_cnt; i++) { - prev_rate = rate; - rate = *prate; - rate *= factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d = &factor->ftbl[i]; + prev_rate = rate; + rate = (u64)(*prate) * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } @@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, { struct mmp_clk_factor *factor = to_clk_factor(hw); struct mmp_clk_factor_masks *masks = factor->masks; - unsigned int val, num, den; + struct u32_fract d; + unsigned int val; u64 rate; val = readl_relaxed(factor->base); /* calculate numerator */ - num = (val >> masks->num_shift) & masks->num_mask; + d.numerator = (val >> masks->num_shift) & masks->num_mask; /* calculate denominator */ - den = (val >> masks->den_shift) & masks->den_mask; - - if (!den) + d.denominator = (val >> masks->den_shift) & masks->den_mask; + if (!d.denominator) return 0; - rate = parent_rate; - rate *= den; - do_div(rate, num * factor->masks->factor); + rate = (u64)parent_rate * d.denominator; + do_div(rate, d.numerator * factor->masks->factor); return rate; } @@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, int i; unsigned long val; unsigned long flags = 0; + struct u32_fract *d; u64 rate = 0; for (i = 0; i < factor->ftbl_cnt; i++) { - rate = prate; - rate *= factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d = &factor->ftbl[i]; + rate = (u64)prate * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } - if (i > 0) - i--; + d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0]; if (factor->lock) spin_lock_irqsave(factor->lock, flags); @@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, val = readl_relaxed(factor->base); val &= ~(masks->num_mask << masks->num_shift); - val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; + val |= (d->numerator & masks->num_mask) << masks->num_shift; val &= ~(masks->den_mask << masks->den_shift); - val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; + val |= (d->denominator & masks->den_mask) << masks->den_shift; writel_relaxed(val, factor->base); @@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw) { struct mmp_clk_factor *factor = to_clk_factor(hw); struct mmp_clk_factor_masks *masks = factor->masks; - u32 val, num, den; + struct u32_fract d; + u32 val; int i; unsigned long flags = 0; @@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw) val = readl(factor->base); /* calculate numerator */ - num = (val >> masks->num_shift) & masks->num_mask; + d.numerator = (val >> masks->num_shift) & masks->num_mask; /* calculate denominator */ - den = (val >> masks->den_shift) & masks->den_mask; + d.denominator = (val >> masks->den_shift) & masks->den_mask; for (i = 0; i < factor->ftbl_cnt; i++) - if (den == factor->ftbl[i].den && num == factor->ftbl[i].num) + if (d.denominator == factor->ftbl[i].denominator && + d.numerator == factor->ftbl[i].numerator) break; if (i >= factor->ftbl_cnt) { val &= ~(masks->num_mask << masks->num_shift); - val |= (factor->ftbl[0].num & masks->num_mask) << - masks->num_shift; + val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift; val &= ~(masks->den_mask << masks->den_shift); - val |= (factor->ftbl[0].den & masks->den_mask) << - masks->den_shift; + val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift; } if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) { @@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops = { struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct mmp_clk_factor_masks *masks, - struct mmp_clk_factor_tbl *ftbl, - unsigned int ftbl_cnt, spinlock_t *lock) + struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock) { struct mmp_clk_factor *factor; struct clk_init_data init; diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index aabacfa10158..ab7dde7e7a44 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c @@ -59,9 +59,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ - {.num = 3521, .den = 689}, /*19.23MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ + { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */ }; static const char *uart_parent[] = {"uart_pll", "vctcxo"}; diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index bcf60f43aa13..d771b3e5fb2d 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -141,9 +141,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ - {.num = 3521, .den = 689}, /*19.23MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ + { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */ }; static struct mmp_clk_factor_masks i2s_factor_masks = { @@ -155,16 +155,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = { .enable_mask = 0xd0000000, }; -static struct mmp_clk_factor_tbl i2s_factor_tbl[] = { - {.num = 24868, .den = 511}, /* 2.0480 MHz */ - {.num = 28003, .den = 793}, /* 2.8224 MHz */ - {.num = 24941, .den = 1025}, /* 4.0960 MHz */ - {.num = 28003, .den = 1586}, /* 5.6448 MHz */ - {.num = 31158, .den = 2561}, /* 8.1920 MHz */ - {.num = 16288, .den = 1845}, /* 11.2896 MHz */ - {.num = 20772, .den = 2561}, /* 12.2880 MHz */ - {.num = 8144, .den = 1845}, /* 22.5792 MHz */ - {.num = 10386, .den = 2561}, /* 24.5760 MHz */ +static struct u32_fract i2s_factor_tbl[] = { + { .numerator = 24868, .denominator = 511 }, /* 2.0480 MHz */ + { .numerator = 28003, .denominator = 793 }, /* 2.8224 MHz */ + { .numerator = 24941, .denominator = 1025 }, /* 4.0960 MHz */ + { .numerator = 28003, .denominator = 1586 }, /* 5.6448 MHz */ + { .numerator = 31158, .denominator = 2561 }, /* 8.1920 MHz */ + { .numerator = 16288, .denominator = 1845 }, /* 11.2896 MHz */ + { .numerator = 20772, .denominator = 2561 }, /* 12.2880 MHz */ + { .numerator = 8144, .denominator = 1845 }, /* 22.5792 MHz */ + { .numerator = 10386, .denominator = 2561 }, /* 24.5760 MHz */ }; static DEFINE_SPINLOCK(acgr_lock); diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 130d1a723879..17cb5c622c31 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -104,8 +104,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c index 2508a0d795f8..675d695c5f7d 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -58,9 +58,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 832, .den = 234}, /*58.5MHZ */ - {.num = 1, .den = 1}, /*26MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 832, .denominator = 234 }, /* 58.5MHZ */ + { .numerator = 1, .denominator = 1 }, /* 26MHZ */ }; static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c index 4d15bac987eb..f5b0b7b278c0 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -84,8 +84,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 8a9b8fb3a465..2ea88945bffd 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c @@ -52,8 +52,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 9fcd76316d7e..e29b0fd6f423 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c @@ -50,8 +50,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index 55ac05379781..c83cec169ddc 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -3,6 +3,7 @@ #define __MACH_MMP_CLK_H #include +#include #include #include @@ -20,16 +21,11 @@ struct mmp_clk_factor_masks { unsigned int enable_mask; }; -struct mmp_clk_factor_tbl { - unsigned int num; - unsigned int den; -}; - struct mmp_clk_factor { struct clk_hw hw; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i2-20020a170902c94200b001bdc78deb5csi1260107pla.398.2023.08.12.03.48.57; Sat, 12 Aug 2023 03:49:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237002AbjHLK0Q (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236540AbjHLK0I (ORCPT ); Sat, 12 Aug 2023 06:26:08 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F34691704; Sat, 12 Aug 2023 03:26:10 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 6177A82AE3; Sat, 12 Aug 2023 12:26:09 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:07 +0200 Subject: [PATCH v5 3/8] dt-bindings: clock: Add Marvell PXA1908 clock bindings MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-3-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4871; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=2hS/59djnNiGlrSBxD6bf42jKLEvv3C8gc9AUs/9pdg=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114E2PZzRbH9sFg4RCm6E/1BiRwXw6elALaK+ m/nvqL9om2JAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4d2TEAChXEx+d04pnMb4fSBLgjBJyYtPv1Th+bTGPo38C5yRyifPn92gfGNQ3YxCbKUKccTDV+I 49vIwNMqlMjAl3SqeXFt7BU25SSIv5DCXvLT6gk7b67KuAzYm6hxFY7t7ir7JGmgnnZQ+Kb2xnv hbzSRNoN7asamAI7jd9v2mzzrxQS2yPzPCgt3kN1saKRh3/qrusBzoMB0LgmUdmzrvYEYWYcXgU 5m5uTkqRfRvSoGooaUWrC1UrTQJvsvmoohVZwXC3KHCYTEKo896BQtgWXYooyS1E3mA0NVtea1y fbYtQ7hWmZlmlzTNemBYUJH8j34p1MDAhO+9IJdjEFKbmRZ+WjpDoJh5isla7E6eJOcHKtMF9eU wdMHMbTc8QUt5TKp8jvKhlY7pAMEq3UXoZHIKLMv6F0dxF4ItGw6Kh86UcgowaqmW+p80vMi1kG eY+ptBNeGYU8pOp82Tf3Ad5mgJCfuU7TzXRud0BrGFJLq7OTwJJ2znI8rkCcJ4SQsRcZNrMtBpM /7Y25AGRvd8+U966FMCHiPXIorPzMzf4uhSb/3UYQ8mOpJ9MM6sBwPWjSofCeDaKqu8m682D1gN MHqm3tvGeCZY+LLgPnRqjEDkGi/yPfKNmTR497rq9o4WgpHLKZwuSwiMl6lqItctc6j7oeg/389 B8aM/uryO8n2ALA== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774020041791510094 X-GMAIL-MSGID: 1774020041791510094 Add dt bindings and documentation for the Marvell PXA1908 clock controller. Signed-off-by: Duje Mihanović Reviewed-by: Conor Dooley --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..fb15b0d0cd4c --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif From patchwork Sat Aug 12 10:25:08 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ik29-20020a170902ab1d00b001b9e9edea43si4658575plb.552.2023.08.12.03.48.03; Sat, 12 Aug 2023 03:48:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237109AbjHLK0d (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236764AbjHLK0L (ORCPT ); Sat, 12 Aug 2023 06:26:11 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B0711712; Sat, 12 Aug 2023 03:26:12 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D15A9840F3; Sat, 12 Aug 2023 12:26:10 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:08 +0200 Subject: [PATCH v5 4/8] clk: mmp: Add Marvell PXA1908 clock driver MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-4-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=13375; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=WAACr3igjNasSLtYmb+GmwsS1YL9LR23z5Vfz85X0YA=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114E3QrpoXCN8SqnfK253brwbrw5FsnNLBU4h vTcXungthaJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4SsWD/9u6Vwoc18gUPkDrfRULhwO4DQQJiehW6bUe3VmOCfUfqKsl9zHZiPxQpwGe0UAnWj60Iw p8PIKDixkNACx0I0sdgBYX8cN0SXlTtPk4Nuz0Oq72h/cM5wz+7plNTnjYv8aBFptc64Wf2CgVL 9Ar7+llQ5yAquPl2yctpadcoPfQya21aPQV+FxyGf5X/lvnLF/qN1gMTQMYjzOjfJEaS2jweDfm NDaL5rx7Zf9eZpT4vegwxbnbpLVEoWP64AHIzAN4TTADQYMbI8NfHTBjvQlztqJwnkzcI9PrGL1 NQaAsvcCGRHBJC5wtc++iSGE5dnffKSXZm8rM6CfHzHpil0RFBNfC1MTBys6HFQ74tw35shVhw/ k4dL01e5eInI7qIGykOdc6KtBfZWly82zTTuCEW0HL13I9UMuce5plnQBDhavpCgIxaK1NDLZm1 IZwnvZyb7ghyPmNmfT8D5THwRWWpDLuIilQm8dImADXtJzwPJDPptLFpNos3YqqrbQpWLAdx/bX 5v45Z4/8m+Ug9INfeOv0ytmPaltA3XRivjJNflA0kIUM6F6rR7BgM5NT9jt2PxIef2PCWSN2nxx zCQDsFsIoSvsEpXqwur0xOXPTrxseXMNILJN1bMPXV5+fccQcIsMrPii8BQtwdZjbKRIne9Erjl LUYP0gEwvc0Rqeg== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774019990429062437 X-GMAIL-MSGID: 1774019990429062437 Add driver for Marvell PXA1908 clock controller blocks. The SoC has numerous clock controller blocks, currently supporting APBC, APBCP, MPMU and APMU. Signed-off-by: Duje Mihanović --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-of-pxa1908.c | 328 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 329 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index cbcc2f8430a2..feacddb28fc4 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -15,4 +15,4 @@ obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o -obj-y += clk-of-pxa1928.o +obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-of-pxa1908.o diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c new file mode 100644 index 000000000000..753dd031b147 --- /dev/null +++ b/drivers/clk/mmp/clk-of-pxa1908.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APMU_CLK_GATE_CTRL 0x40 +#define MPMU_UART_PLL 0x14 + +#define APBC_UART0 0x0 +#define APBC_UART1 0x4 +#define APBC_GPIO 0x8 +#define APBC_PWM0 0xc +#define APBC_PWM1 0x10 +#define APBC_PWM2 0x14 +#define APBC_PWM3 0x18 +#define APBC_SSP0 0x1c +#define APBC_SSP1 0x20 +#define APBC_IPC_RST 0x24 +#define APBC_RTC 0x28 +#define APBC_TWSI0 0x2c +#define APBC_KPC 0x30 +#define APBC_SWJTAG 0x40 +#define APBC_SSP2 0x4c +#define APBC_TWSI1 0x60 +#define APBC_THERMAL 0x6c +#define APBC_TWSI3 0x70 + +#define APBCP_UART2 0x1c +#define APBCP_TWSI2 0x28 +#define APBCP_AICER 0x38 + +#define APMU_CCIC1 0x24 +#define APMU_ISP 0x38 +#define APMU_DSI1 0x44 +#define APMU_DISP1 0x4c +#define APMU_CCIC0 0x50 +#define APMU_SDH0 0x54 +#define APMU_SDH1 0x58 +#define APMU_USB 0x5c +#define APMU_NF 0x60 +#define APMU_VPU 0xa4 +#define APMU_GC 0xcc +#define APMU_SDH2 0xe0 +#define APMU_GC2D 0xf4 +#define APMU_TRACE 0x108 +#define APMU_DVC_DFC_DEBUG 0x140 + +#define MPMU_NR_CLKS 39 +#define APBC_NR_CLKS 19 +#define APBCP_NR_CLKS 4 +#define APMU_NR_CLKS 17 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *mpmu_base; + void __iomem *apmu_base; + void __iomem *apbc_base; + void __iomem *apbcp_base; + void __iomem *apbs_base; + void __iomem *ciu_base; +}; + +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { + {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768}, + {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ}, +}; + +static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { + {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0}, + {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0}, + {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0}, + {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0}, + {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0}, + {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0}, + {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0}, + {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0}, + {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0}, + {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0}, + {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0}, + {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0}, + {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0}, +}; + +static struct mmp_clk_factor_masks uart_factor_masks = { + .factor = 2, + .num_mask = GENMASK(12, 0), + .den_mask = GENMASK(12, 0), + .num_shift = 16, + .den_shift = 0, +}; + +static struct u32_fract uart_factor_tbl[] = { + {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */ +}; + +static DEFINE_SPINLOCK(pll1_lock); +static struct mmp_param_general_gate_clk pll1_gate_clks[] = { + {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock}, +}; + +static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_register_fixed_rate_clks(unit, fixed_rate_clks, + ARRAY_SIZE(fixed_rate_clks)); + + mmp_register_fixed_factor_clks(unit, fixed_factor_clks, + ARRAY_SIZE(fixed_factor_clks)); + + mmp_clk_register_factor("uart_pll", "pll1_d4", + CLK_SET_RATE_PARENT, + pxa_unit->mpmu_base + MPMU_UART_PLL, + &uart_factor_masks, uart_factor_tbl, + ARRAY_SIZE(uart_factor_tbl), NULL); + +} + +static DEFINE_SPINLOCK(pwm0_lock); +static DEFINE_SPINLOCK(pwm2_lock); + +static DEFINE_SPINLOCK(uart0_lock); +static DEFINE_SPINLOCK(uart1_lock); +static DEFINE_SPINLOCK(uart2_lock); + +static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"}; +static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"}; + +static struct mmp_param_gate_clk apbc_gate_clks[] = { + {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &pwm0_lock}, + {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart0_lock}, + {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart1_lock}, +}; + +static struct mmp_param_mux_clk apbc_mux_clks[] = { + {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, + {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, + {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP0, 4, 3, 0, NULL}, + {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_SSP2, 4, 3, 0, NULL}, +}; + +static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->apbc_base + APBC_PWM0, + 0x5, 1, 0, 0, &pwm0_lock); + mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->apbc_base + APBC_PWM2, + 0x5, 1, 0, 0, &pwm2_lock); + mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, + ARRAY_SIZE(apbc_mux_clks)); + mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, + ARRAY_SIZE(apbc_gate_clks)); +} + +static struct mmp_param_gate_clk apbcp_gate_clks[] = { + {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, + {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL}, + {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL}, +}; + +static struct mmp_param_mux_clk apbcp_mux_clks[] = { + {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock}, +}; + +static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base, + ARRAY_SIZE(apbcp_mux_clks)); + mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base, + ARRAY_SIZE(apbcp_gate_clks)); +} + +static DEFINE_SPINLOCK(sdh0_lock); +static DEFINE_SPINLOCK(sdh1_lock); +static DEFINE_SPINLOCK(sdh2_lock); + +static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"}; + +static struct mmp_clk_mix_config sdh_mix_config = { + .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11), +}; + +static struct mmp_param_gate_clk apmu_gate_clks[] = { + {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL}, + {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock}, + {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock}, + {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock} +}; + +static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_register_general_gate_clks(unit, pll1_gate_clks, + pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks)); + + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; + mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh0_lock); + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH1; + mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh1_lock); + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH2; + mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh2_lock); + + mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, + ARRAY_SIZE(apmu_gate_clks)); +} + +static void __init pxa1908_apbc_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apbc_base = of_iomap(np, 0); + if (!pxa_unit->apbc_base) { + pr_err("failed to map apbc registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS); + + pxa1908_apb_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init); + +static void __init pxa1908_apbcp_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apbcp_base = of_iomap(np, 0); + if (!pxa_unit->apbcp_base) { + pr_err("failed to map apbcp registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, APBCP_NR_CLKS); + + pxa1908_apb_p_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_init); + +static void __init pxa1908_mpmu_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->mpmu_base = of_iomap(np, 0); + if (!pxa_unit->mpmu_base) { + pr_err("failed to map mpmu registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, MPMU_NR_CLKS); + + pxa1908_pll_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init); + +static void __init pxa1908_apmu_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apmu_base = of_iomap(np, 0); + if (!pxa_unit->apmu_base) { + pr_err("failed to map apmu registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS); + + pxa1908_axi_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init); From patchwork Sat Aug 12 10:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 134861 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1632933vqi; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u8-20020a1709026e0800b001b89bfd0c34si4472703plk.18.2023.08.12.03.27.25; Sat, 12 Aug 2023 03:27:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237063AbjHLK0U (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234748AbjHLK0J (ORCPT ); Sat, 12 Aug 2023 06:26:09 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 897F22133; Sat, 12 Aug 2023 03:26:12 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 000CB82AE5; Sat, 12 Aug 2023 12:26:10 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:09 +0200 Subject: [PATCH v5 5/8] dt-bindings: marvell: Document PXA1908 SoC MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-5-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de, Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=890; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=2ainjaUkEO8QAJQ9TFJg6BT5HCGIXfSI5apzikQRiN8=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114E7HTfT9tN/rAL215HciXtCc+q399A0tT/Z hs46NNU/HGJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4XGVEACJOjDghy+FVW9JMrbajmBAgiz7GitrR3uJhGoYZy3y2jRPeGHBpnfeycKpHvNm35rfyat +YLiSXkSBkSOApvOldPjqGf/7eHgEAGRZxHB1D+icGpYxn8rodNms3IrDdl8poFpMF2B/DyKrPg iJmn9fi3PGa4ycJMRWh1gvuh5e8baReAk+hQRR30W0UN2DBBSmxgy4u+Of/lZZ0XXEh+5F1tQBX /wT+rCs7LMfWzHBXqmic1wQRbFED91CGwJoaAtN36/yzgKXSB/MWGrPWwr2UD1iTOrMPixM+0q/ 9psV+2mCTcBVRzHS34jBUlW6K2sSkk2Yy5iL4HVJ2DZ9Ql42RKt3h4s18gTl+KrLEWWn6TgEY7p llj4HistUTUyMEpVUGtJvmtP5ZTWcGkMdC+eW/NkZ2zV56JSVXVKwyqbzDd1R/6vGvEifFt+vBo cci4PupBDFMPofbldcJoeN7kYOGnXsFpkRUy/2ZmthJFDN9pWNVFj+Wu9cAWWtDpJFmtGiTeJ6k v6LU6leUJ5JG9rjYEGUdmnMeAmOXmEVi6Chl95D4KTqWPN+xq4LKBmPyXygxhSgRaf5jgjnM+Wu /zHOh9V24fec6XBeN/Yjy9SOTU+TkyVNm7SZ3riFltyTlJuwebab+en8zP24HiybxGZyEk+JluR V8bHCp6Y0Lu293Q== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774018687204427723 X-GMAIL-MSGID: 1774018687204427723 Add dt binding for the Marvell PXA1908 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Duje Mihanović --- Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml index 4c43eaf3632e..f73bb8ec3a1a 100644 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -35,6 +35,11 @@ properties: - enum: - dell,wyse-ariel - const: marvell,mmp3 + - description: PXA1908 based boards + items: + - enum: + - samsung,coreprimevelte + - const: marvell,pxa1908 additionalProperties: true From patchwork Sat Aug 12 10:25:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 134864 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1636192vqi; Sat, 12 Aug 2023 03:37:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQwhQUoiyNoY8KpxdQXt6zBRF+yT+nBH/31agjG3ClCEPITCDV/JHG/7TGrLgHjGGuikZf X-Received: by 2002:a05:6a20:12c2:b0:123:152d:d46b with SMTP id v2-20020a056a2012c200b00123152dd46bmr5518046pzg.26.1691836641902; Sat, 12 Aug 2023 03:37:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691836641; cv=none; d=google.com; s=arc-20160816; b=duuNvntbr0q5omNvgO7iahU892W0fT/dG722izZORnBpcTm62+HuNZD9/gwrL1ulJf nnJFyF+1QwRxCdw3j7mDh8LprggUzHrGkIINye8B7vy6hYCeTuhID1t3J7utKRw60vGd q6tNmfpJX6VrTsR/ZmTYUq4PXYFXXNCFPJbXim3HhH8K+qja/bVKUH7TVYEGDZ0E694x ovD5sbBVsCJ+3wHZXYPhxjChedtkDP6QBQN5/EQlVJcnXSSyQ9EomYuHAMSlUxhTWNkx Y9c37cEJsM+b5/2p0o/0s9/FUuT2YY05gZYzQ1tv+w7W82UNfQuKlyaXXuQuumwo1Ea3 idbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=wVjmKbVaHpWRt7Z4ZOSl2FKTB+SL8sY1i33zcP0PheE=; fh=gVj9ppBdMlwIkItVqLo/K1C9sxJsP6QcvClbF/EE+nA=; b=xdlzt04RAYXDJc0gU34GbXM0HzOhOZlEa01wOqi7FWnSDX83FDDUGBEHVuOZDxdJk+ aagMjK/PuIH7fqvlf53G3yj2RommIMZxSULlp7HXDaU1R97QeGGD/3hqbB1Uwe3g4zY6 cCzz44KdwJpzuDQJr7IrzYwOzHctMeYV3rAGfcWT44l8ZPRq7L4ThIPzz3QFiJCchRcy aI9LX0oZEyTeJo7UiLCXBmk1WTD7v9wJCdMvgJEDE5wyeaZ5OYqLlJwZUgmT/pF3X3uK 3MlTE4FHFU1EJKdV1Wnmd2dhhXmwUcJ1BVpvYVSIcDGYRBGEFRqufdEfI7aDOnkIDmCY yu9Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r5-20020a654985000000b005641315d956si4863295pgs.147.2023.08.12.03.37.07; Sat, 12 Aug 2023 03:37:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236937AbjHLK02 (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234007AbjHLK0K (ORCPT ); Sat, 12 Aug 2023 06:26:10 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E0201704; Sat, 12 Aug 2023 03:26:13 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id EBCAF837F2; Sat, 12 Aug 2023 12:26:11 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:10 +0200 Subject: [PATCH v5 6/8] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-6-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. 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Signed-off-by: Duje Mihanović --- arch/arm64/Kconfig.platforms | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..b417cae42c84 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,17 @@ config ARCH_BERLIN help This enables support for Marvell Berlin SoC Family +config ARCH_MMP + bool "Marvell MMP SoC Family" + select ARM_GIC + select ARM_ARCH_TIMER + select ARM_SMMU + select MMP_PDMA + select PINCTRL_SINGLE + help + This enables support for Marvell MMP SoC family, currently + supporting PXA1908 aka IAP140. + config ARCH_BITMAIN bool "Bitmain SoC Platforms" help From patchwork Sat Aug 12 10:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 134862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp1633103vqi; Sat, 12 Aug 2023 03:28:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFd5zj+F021gKD8zljzPta1obJwAuIHCLpn5NT+aVHbFIPSitaHXmDh1Vr7YapS3cGsG+MW X-Received: by 2002:aa7:d1d8:0:b0:522:2019:2020 with SMTP id g24-20020aa7d1d8000000b0052220192020mr3003404edp.17.1691836092876; Sat, 12 Aug 2023 03:28:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691836092; cv=none; d=google.com; s=arc-20160816; b=LbyhYdMcqY/1FXvyPLoNX2qU9ANlxsvrRSBFndPJX5RnkIqEAfT9ZDcqA7x+czQcBC A32Ti2xwnMSa6P+3OfTfrJD/PJPXrGMfQdAXWplKxUBNtJdrsER6cYkBElgoELGD+7kL TqO279YA6GwwOgoYIpa600YvgPJ70ccEITgHWW74jhi1Y0oZ6kAFES4tfYkRSXEkBCwV AQNwz8WA+ZjSYxtEbiWjXyW7xmmOfMNQBiqbvnW9bsnU2+wH9PRa2gAmE70qLxEj/A28 qOznET4hAjf2OPPX4oDp4byCs+5n2MdTjeSrdFZcuQlHywhCRmv3gfbgcMRb/crDJKcl tF5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=UPRoUe+YZPR1bybAwYSaWsYo4q8dvFq7QUKB6nV4JNc=; fh=gVj9ppBdMlwIkItVqLo/K1C9sxJsP6QcvClbF/EE+nA=; b=f+otmr6Ma+1C4I0R9Sr6B4WfES/UtS8nNiHRFd1fV3rjprf+hbc+HxigHQyXvpWsd0 XYQVkieMFN0Rkl4EwzMB40lQi/odFjOrAyffEwQrYno6C3ZlkQD7mhegwUclOC1EeVls k7B4KLwKaQC4Rth2L4IanaMSriovsbwcYfKoKd1kwE/+Hc/kDlS7Ct7L9PR3qG1ApVVc /KChRWf/XfubOU8XKQupJBxwunPps83BQI3S5nOt4sDNge1fSXNHBzlxFFnqaF6U/6jA R3dXyGTvx2rt91RAW/uuUg5pqxAGsi/SPXUn1Mgnl1pAxyREUCYGrk8G7O9SiF1/tm9+ kM4g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v4-20020a056402184400b00521953ce6eesi4581534edy.97.2023.08.12.03.27.44; Sat, 12 Aug 2023 03:28:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235504AbjHLK0j (ORCPT + 99 others); Sat, 12 Aug 2023 06:26:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236974AbjHLK0O (ORCPT ); Sat, 12 Aug 2023 06:26:14 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E575170D; Sat, 12 Aug 2023 03:26:15 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D736882AE6; Sat, 12 Aug 2023 12:26:13 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Sat, 12 Aug 2023 12:25:11 +0200 Subject: [PATCH v5 7/8] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte MIME-Version: 1.0 Message-Id: <20230812-pxa1908-lkml-v5-7-a5d51937ee34@skole.hr> References: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> In-Reply-To: <20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr> To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , =?utf-8?q?Duje_Mihanovi=C4=87?= Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.de X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=16631; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=quTomvn3gr/hybIjdZsPfEB1DGFR5jS0tMGXtewBkGo=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBk114E68/GaCN6v06LoNi1ZmrBRsXcBR/o3mH9m 2lFYVGK/F2JAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZNdeBAAKCRCaEZ6wQi2W 4awxD/9Xu5Qck7NOoUpId2pIiNPk4F8990pnEm4twLwaxfBvPpoQ2MA498e3Q89CBv+ZFC0lV1d pHdqSNIz4vvnUwJEJGlgBDLTsEzgOPeKdM/9YOm/eqlz+JXy75MFCQNgPaPZv7CFyRlje23bZF4 gAEkPSdJLZ7r4dq427BIM3Oq88zoNHk4xu9JGKSM6sHImmAFlZ00OfYz//j5t4iCPevANtriEEd cQOz9TEjg83CwmwW/cm812sFJUFgG2wYDc9mnhPdtSw42J/nDRDUuDycIjJCAZTPRDrB5yR55Mo kUZWSxvnJmvMeS3P1VGtVh8SXrQVdfowKDAcX0bSsDoXVIsppDWj+l5CRRhQi8yIonHHCy4V8Hy W9M+lBLl2D0IgS+PIg8tlIdgpsll4eoUYkc8LupVoNPseITHBULkzY9/eJc29+uMzEPJ4Z80WZ5 8E//8/NEljSMtYJxs/DRM7ahiSZdPoyPBj4d10afO4Vdwn6U3N8H6mvpauxqnEbpl+vlfDYUCh2 5FM2on0pHFnViZQkaNfZMz7psOeyaBvGlRmIEHJayHrZk72afmaecvWfREqcT/3D4L7UiMB6nZU ooFbvXW/zk59EVv8S+sagjou1C6y0l+GZXwYvSIMftwWCm4yJw/xH+kVgmt88pznrckH6X9HAvM 3b/rPz+Jd9AbNCw== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774018722909388619 X-GMAIL-MSGID: 1774018722909388619 Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value Edition LTE, a smartphone based on said SoC. Signed-off-by: Duje Mihanović --- arch/arm64/boot/dts/marvell/Makefile | 3 + .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 333 +++++++++++++++++++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi | 295 ++++++++++++++++++ 3 files changed, 631 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 79ac09b58a89..263be6ec7567 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -27,3 +27,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb + +# MMP SoC Family +dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 000000000000..e3c863d517a8 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" +#include +#include + +/ { + model = "Samsung Galaxy Core Prime VE LTE"; + compatible = "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + mmc0 = &sdh2; /* eMMC */ + mmc1 = &sdh0; /* SD card */ + serial0 = &uart0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + fb0: framebuffer@17177000 { + compatible = "simple-framebuffer"; + reg = <0 0x17177000 0 (480 * 800 * 4)>; + width = <480>; + height = <800>; + stride = <(480 * 4)>; + format = "a8r8g8b8"; + }; + }; + + /* Bootloader fills this in */ + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@17000000 { + reg = <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg = <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@3000000 { + reg = <0 0x3000000 0 0x5000000>; + }; + + cm3@a000000 { + reg = <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg = <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; + + + i2c-muic { + compatible = "i2c-gpio"; + sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <3>; + i2c-gpio,timeout-ms = <100>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_muic_pins>; + + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + interrupt-parent = <&gpio>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + autorepeat; + + key-home { + label = "Home"; + linux,code = ; + gpios = <&gpio 50 GPIO_ACTIVE_LOW>; + }; + + key-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + key-voldown { + label = "Volume Down"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&pmx { + pinctrl-single,gpio-range = <&range 55 55 0>, + <&range 110 32 0>, + <&range 52 1 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>; + + board_pins_1: pinmux-board-1 { + pinctrl-single,pins = < + 0x160 0 + 0x164 0 + 0x168 0 + 0x16c 0 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x288 0x388>; + }; + + board_pins_2: pinmux-board-2 { + pinctrl-single,pins = < + 0x44 1 + 0x48 1 + 0x20 1 + 0x18 1 + 0x14 1 + 0x10 1 + 0xc 1 + 0x8 1 + 0x68 1 + 0x58 0 + 0x54 0 + 0x7c 0 + 0x6c 0 + 0x70 0 + 0x4c 1 + 0x50 1 + 0xac 0 + 0x90 0 + 0x8c 0 + 0x88 0 + 0x84 0 + 0xc8 0 + 0x128 0 + 0x190 0 + 0x194 0 + 0x1a0 0 + 0x114 0 + 0x118 0 + 0x1d8 0 + 0x1e4 0 + 0xe8 0 + 0x100 0 + 0x204 0 + 0x210 0 + 0x218 0 + >; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>; + pinctrl-single,low-power-mode = <0x288 0x388>; + }; + + board_pins_3: pinmux-board-3 { + pinctrl-single,pins = < + 0x260 0 + 0x264 0 + 0x268 0 + 0x26c 0 + 0x270 0 + 0x274 0 + 0x78 0 + 0x74 0 + 0xb0 1 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + uart0_pins: pinmux-uart0 { + pinctrl-single,pins = < + 0x198 6 + 0x19c 6 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + gpio_keys_pins: pinmux-gpio-keys { + pinctrl-single,pins = < + 0x11c 0 + 0x120 0 + 0x1a4 0 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + i2c_muic_pins: pinmux-i2c-muic { + pinctrl-single,pins = < + 0x154 0 + 0x150 0 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x288 0x388>; + }; + + sdh0_pins_1: pinmux-sdh0-1 { + pinctrl-single,pins = < + 0x108 0 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh0_pins_2: pinmux-sdh0-2 { + pinctrl-single,pins = < + 0x94 0 + 0x98 0 + 0x9c 0 + 0xa0 0 + 0xa4 0 + >; + pinctrl-single,drive-strength = <0x800 0x1800>; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh0_pins_3: pinmux-sdh0-3 { + pinctrl-single,pins = < + 0xa8 0 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x208 0x388>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&twsi0 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; +}; + +&twsi2 { + status = "okay"; +}; + +&twsi3 { + status = "okay"; +}; + +&usb { + extcon = <&muic>, <&muic>; +}; + +&sdh2 { + /* Disabled for now because initialization fails with -ETIMEDOUT. */ + status = "disabled"; + bus-width = <8>; + non-removable; + broken-cd; + mmc-ddr-1_8v; +}; + +&sdh0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdh0_pins_1 &sdh0_pins_2 &sdh0_pins_3>; + cd-gpios = <&gpio 11 0>; + cd-inverted; + bus-width = <4>; + wp-inverted; +}; diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi new file mode 100644 index 000000000000..cc322b9a0e9e --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include +#include + +/ { + model = "Marvell Armada PXA1908"; + compatible = "marvell,pxa1908"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smmu: iommu@c0010000 { + compatible = "arm,mmu-400"; + reg = <0 0xc0010000 0 0x10000>; + #global-interrupts = <1>; + #iommu-cells = <1>; + interrupts = , + ; + status = "disabled"; + }; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0 0xd4000000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4000000 0x200000>; + + pdma: dma-controller@0 { + compatible = "marvell,pdma-1.0"; + reg = <0 0x10000>; + interrupts = ; + dma-channels = <30>; + #dma-cells = <2>; + }; + + twsi1: i2c@10800 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10800 0x64>; + interrupts = ; + clocks = <&apbc PXA1908_CLK_TWSI1>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi0: i2c@11000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11000 0x64>; + interrupts = ; + clocks = <&apbc PXA1908_CLK_TWSI0>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi3: i2c@13800 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x13800 0x64>; + interrupts = ; + clocks = <&apbc PXA1908_CLK_TWSI3>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + apbc: clock-controller@15000 { + compatible = "marvell,pxa1908-apbc"; + reg = <0x15000 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@17000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x17000 0x1000>; + interrupts = ; + clocks = <&apbc PXA1908_CLK_UART0>; + reg-shift = <2>; + }; + + uart1: serial@18000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x18000 0x1000>; + interrupts = ; + clocks = <&apbc PXA1908_CLK_UART1>; + reg-shift = <2>; + }; + + gpio: gpio@19000 { + compatible = "marvell,mmp-gpio"; + reg = <0x19000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&apbc PXA1908_CLK_GPIO>; + interrupts = ; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <2>; + ranges = <0 0x19000 0x800>; + + gpio@0 { + reg = <0x0 0x4>; + }; + + gpio@4 { + reg = <0x4 0x4>; + }; + + gpio@8 { + reg = <0x8 0x4>; + }; + + gpio@100 { + reg = <0x100 0x4>; + }; + }; + + pmx: pinmux@1e000 { + compatible = "pinconf-single"; + reg = <0x1e000 0x330>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + ranges; + + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + uart2: serial@36000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x36000 0x1000>; + interrupts = ; + clocks = <&apbcp PXA1908_CLK_UART2>; + reg-shift = <2>; + }; + + twsi2: i2c@37000 { + compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x37000 0x64>; + interrupts = ; + clocks = <&apbcp PXA1908_CLK_TWSI2>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + apbcp: clock-controller@3b000 { + compatible = "marvell,pxa1908-apbcp"; + reg = <0x3b000 0x1000>; + #clock-cells = <1>; + }; + + mpmu: clock-controller@50000 { + compatible = "marvell,pxa1908-mpmu"; + reg = <0x50000 0x1000>; + #clock-cells = <1>; + }; + }; + + axi@d4200000 { + compatible = "simple-bus"; + reg = <0 0xd4200000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4200000 0x200000>; + + usbphy: phy@7000 { + compatible = "marvell,pxa1928-usb-phy"; + reg = <0x7000 0x200>; + clocks = <&apmu PXA1908_CLK_USB>; + #phy-cells = <0>; + }; + + usb: usb@8000 { + compatible = "chipidea,usb2"; + reg = <0x8000 0x200>; + interrupts = ; + clocks = <&apmu PXA1908_CLK_USB>; + phys = <&usbphy>; + phy-names = "usb-phy"; + }; + + sdh0: mmc@80000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0x80000 0x120>; + interrupts = ; + clocks = <&apmu PXA1908_CLK_SDH0>; + clock-names = "io"; + mrvl,clk-delay-cycles = <31>; + }; + + sdh1: mmc@80800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0x80800 0x120>; + interrupts = ; + clocks = <&apmu PXA1908_CLK_SDH1>; + clock-names = "io"; + mrvl,clk-delay-cycles = <31>; + }; + + sdh2: mmc@81000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0x81000 0x120>; + interrupts = ; + clocks = <&apmu PXA1908_CLK_SDH2>; + clock-names = "io"; + mrvl,clk-delay-cycles = <31>; + }; + + apmu: clock-controller@82800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0x82800 0x400>; + #clock-cells = <1>; + }; + }; + }; +};