From patchwork Fri Aug 11 10:11:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 134397 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp980318vqi; Fri, 11 Aug 2023 03:13:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHSX+/tNL1LUZ3bdZtlpKehCXQ/TerumZrPrEKDckdHSz+UyaPClS7zee2wp24xrPbPnNyt X-Received: by 2002:a17:906:200a:b0:991:b554:e64b with SMTP id 10-20020a170906200a00b00991b554e64bmr1231275ejo.54.1691748785015; Fri, 11 Aug 2023 03:13:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691748784; cv=none; d=google.com; s=arc-20160816; b=hz3BVYkyUtnCn7BmeGaSLYT2sb8wIyyqAK5O68HzstwiMY6kzCryDKxmsXFIEJ6ap6 7kVl9WhTVhKWL8VtZWOY/sJfsqbU3tmGpQWWRWqXKzevNzMXuJ0A+iTNYvKgRnOA+7Aj KwYVuMaN8/l7sj0FNuHQs0jE4frUflf7itaULc5SBKHpMPL/dIDAuAjmfgncVPcFpNeK RITvtEpN/wXlnnt1wV4M+z1BtXZVI/BI7Cbde0iiRTAvHIgboPRs2fIAk92XNvL2e3fz V2XKkzNiuZ0DSPmyQgWvlzzOjSqhx+X5PUhiDEFKhYtmRSi4OWbV5k9yD+o+PXHkSIcc 3hqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=gowGBlsj+t3thIl4qTA1Ra7DZCBOyBZCOcEjUYITC3U=; fh=PmVSnvRlVeKkg+dPKzMCyvykdI2+tUdRpMZVt54Vt9k=; b=D27sEq9+BeS2O1+V86GciX8GoQFOlvZL95T4aPWdJ/WvPNCLx/F1pr817iQ/CCX7XT UkTQfDY5nERZyBgyPEGNZTHuIhSJreSHtEZ7+4BfY5hWoOUzZoYQuyADmvVnqw5UI+Ve l6o+AJSmMOLA4uwPvQbHV0fRiFGCnC63weWMQVrXSFN4aF0WlUsgLFRH1zQwPyNtCYKs l69D+at1vkSnwEiru0f8+v9yP9LNg8Qb63fJztioCLSVtJEpmJzEy/XxyJ+JN+zUXJVR AuycoCFjmy7lQ0L6VtV3obc6iVGO/+Rm1U8dP2FvYU0WvLUS2KrRsJnI7wrglePrW/rh e6uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=YAd5A0PY; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n6-20020a170906840600b00988a0d78152si3344715ejx.55.2023.08.11.03.13.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 03:13:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=YAd5A0PY; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A6397385828D for ; Fri, 11 Aug 2023 10:13:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6397385828D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691748783; bh=gowGBlsj+t3thIl4qTA1Ra7DZCBOyBZCOcEjUYITC3U=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=YAd5A0PYZzhBCjF8gRveMdrF92j4kPlr3qcvmavhGxP3HtbeGc1MWQAvSs1oy/MCM xBc0OrhwKb6fGDgL7nNtIHBkJt5j9kcLtdbzJ/6WlnNJJgUkluQ1xa9sRKMhta0SGl DdbkEY78SQGke0KNcT42iRMbdZw8Yo6oo/k/93Qw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 2AAF13858D20 for ; Fri, 11 Aug 2023 10:12:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2AAF13858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="437982150" X-IronPort-AV: E=Sophos;i="6.01,165,1684825200"; d="scan'208";a="437982150" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 03:11:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="726209984" X-IronPort-AV: E=Sophos;i="6.01,165,1684825200"; d="scan'208";a="726209984" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga007.jf.intel.com with ESMTP; 11 Aug 2023 03:11:55 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 810F010085B5; Fri, 11 Aug 2023 18:11:54 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMSUB rounding mode intrinsic API Date: Fri, 11 Aug 2023 18:11:53 +0800 Message-Id: <20230811101153.1621235-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773927173727508984 X-GMAIL-MSGID: 1773927173727508984 From: Pan Li This patch would like to support the rounding mode API for the VFMSUB as the below samples. * __riscv_vfmsub_vv_f32m1_rm * __riscv_vfmsub_vv_f32m1_rm_m * __riscv_vfmsub_vf_f32m1_rm * __riscv_vfmsub_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmsub_frm): New class for vfmsub frm. (vfmsub_frm): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmsub_frm): New function declaration. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-msub.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-msub.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b085ba4f52d..381bc72c784 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -493,6 +493,29 @@ public: } }; +/* Implements below instructions for frm + - vfmsub +*/ +class vfmsub_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + false, code_for_pred_mul_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + false, code_for_pred_mul (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2266,6 +2289,7 @@ static CONSTEXPR const vfmsac_frm vfmsac_frm_obj; static CONSTEXPR const vfnmadd vfnmadd_obj; static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj; static CONSTEXPR const vfmsub vfmsub_obj; +static CONSTEXPR const vfmsub_frm vfmsub_frm_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; @@ -2507,6 +2531,7 @@ BASE (vfmsac_frm) BASE (vfnmadd) BASE (vfnmadd_frm) BASE (vfmsub) +BASE (vfmsub_frm) BASE (vfwmacc) BASE (vfwnmacc) BASE (vfwmsac) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 4ade0ace7b2..99cfbfd78c8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -173,6 +173,7 @@ extern const function_base *const vfmsac_frm; extern const function_base *const vfnmadd; extern const function_base *const vfnmadd_frm; extern const function_base *const vfmsub; +extern const function_base *const vfmsub_frm; extern const function_base *const vfwmacc; extern const function_base *const vfwnmacc; extern const function_base *const vfwmsac; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index e9b16f99180..75235ec01d3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -361,6 +361,8 @@ DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c new file mode 100644 index 00000000000..e58519d0742 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmsub_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmsub_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmsub_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmsub_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmsub_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmsub_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmsub\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */