From patchwork Wed Nov 2 17:38:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14410 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp45742wru; Wed, 2 Nov 2022 10:40:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM40XYIkT6woXTIAJJwDWKDXJn4G7YM4Bg1QacGJwy/ZhDp5oQOU7JFEiyIm1iM9fGe+Vo0m X-Received: by 2002:a50:bb06:0:b0:461:4acc:4540 with SMTP id y6-20020a50bb06000000b004614acc4540mr26706077ede.307.1667410804356; Wed, 02 Nov 2022 10:40:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667410804; cv=none; d=google.com; s=arc-20160816; b=fyT1yKS9pKzxdRiqboZ/0sEeTB1FYD52E39WCV9gz71t/RGqkU65GA4RsphAl/CVO4 O1ezqS96iOqGw3mDOOkgdQYJGO4FYNUdLvUTFyOJxpkx6UiNGD8hCaLozCJ0/H6+iJc9 NjRq2qYWNly3b5rvxAB2ZL7OQ3mZ2qoPKfEG5URXretgS5BnvpXsQ3HRtXQPmQ/2ggOe HQpVrmtiLtxtcjvhd2WOI1/IcRaH1JjoyWAx+Twid2xN/ILdT6snMkc0ROzrokFLOO7R SRM3bx1phVyaxREzwHilllknzCETcDQR7BNhpMu81Kq2ZzijazZr7rHVUEoLtI7tW9Pi 7VqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=56/n03mz4wi60Ws7/Zw0WT44Iwy4GO+OJ1Zg9+XJrtk=; b=MrU1mojVC76N0imPUXAqqnCaL47nW6X+NEbUvGqrCU6haGYUFlyKRVrRpUT6JqX6H9 o8shi9GhjyVU5LKqjvhYsxQ0TTalh1s6BXAobLLDP+baJjFhntJBmCFnF7j/JjrL9zlT b0BowrEvQeIfHMkV/QYoD4uuu08VnKtkxW6qCOQohvgLtDfT8Q4GC67olT8ygmjCb6By aLtvn9lbV65J82KmWvVom6pr6h/zsSsAQvCVKUGIhn44BZtVS8Ze8WXAcY7rOn2kRBBN gnNxWavm5TEBU7sT4ttQg+4m/wO2AXVCppahjcMTFew948PAqfMRQygiLL7+t3L6DYLt jiuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=FjY+MwJ1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qw18-20020a1709066a1200b0078d2197d670si17627755ejc.661.2022.11.02.10.39.40; Wed, 02 Nov 2022 10:40:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=FjY+MwJ1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230314AbiKBRjR (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231445AbiKBRix (ORCPT ); Wed, 2 Nov 2022 13:38:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C4A6DDC; Wed, 2 Nov 2022 10:38:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DC19461A32; Wed, 2 Nov 2022 17:38:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E80CC433C1; Wed, 2 Nov 2022 17:38:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410731; bh=/ON+gsXdFppkI6cKXNcthQ/QCtA2Pr6PzO03HRm7PDc=; h=From:To:Cc:Subject:Date:From; b=FjY+MwJ1cGJ3hWSa+inCk7llbc3rznAhNJ1KoHHNuIcE7dbjsUv6TqLQmaW0qxhbR ZjqDy6Q+hBQqxrADq1wtPzX3iIfeJzAvB9eBi4EyhRH5qI6qUrilA0pnsi0DZzf7lB /86Osba7IWuUp35Y7dIVFAQgn8847vJeyOkhrjFCFSAlVt7ryrhqYG0r9a+sm/IkXc Y7XebqST9SSD39b8PE5vnS9RK565woRHiQtlPHmfRGMvfbyo8kScoWD0xCx5+SnFny O2elFs8ly8wo8uRvOwSkaa8OsjQVJbufLxTxVaKJQAtRtktm95Sp8huiAXDIgCigw9 XyS+eTGTN0/VA== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Wed, 2 Nov 2022 12:38:38 -0500 Message-Id: <20221102173843.409039-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748406951603198046?= X-GMAIL-MSGID: =?utf-8?q?1748406951603198046?= Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen --- v7: and "not" for the required "altr,sysmgr-syscon" binding v6: make "altr,sysmgr-syscon" optional v5: document reg shift v4: add else statement v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 33 +++++++++++++++++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..80dd3d72424f 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson @@ -38,6 +35,36 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + This property is optional. Contains the phandle to System Manager block + that contains the SDMMC clock-phase control register. The first value is + the pointer to the sysmgr, the 2nd value is the register offset for the + SDMMC clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + not: + required: + - altr,sysmgr-syscon + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg From patchwork Wed Nov 2 17:38:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14412 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp46054wru; Wed, 2 Nov 2022 10:40:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM58A+A/E4lfPTMCf43UD9xCTp9XdxhfDg8Uk/FnnNMqVsxolT3Ep7MOqr4/76aKEoA8eGo4 X-Received: by 2002:a05:6402:440d:b0:450:de54:3fcf with SMTP id y13-20020a056402440d00b00450de543fcfmr25231357eda.312.1667410848931; Wed, 02 Nov 2022 10:40:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667410848; cv=none; d=google.com; s=arc-20160816; b=FyTPhm8UBPQ+8L3pncRGSyRTad/auoiWUq073u2lY5siGCC6TVNLJVcezYR7Y+yc/S k/YYbOUCCSXO9GcDQy95B/asHvabdtp1YsFE5REW523IpmS/O6JXfgOwR0LQZauMgKRo Rmj01N+DMI+bUh+2g0vqkNqUZvis8VWMGZsKA3oB0Qma1frvTYQfUeVBF7isdSnXvDxk KHQ8xX2l2aaVIZssZFh3ipjMgGHpvHIwn8fu7KrxuV+VMF3yhB3urA8NKVlY/Ks0R7pi YlDnOqaUIWW/OmLJJmurl0BE1G5d30G+AZPfcJFGb+7lcWoKmkpEZWbzV7SRzM262mx2 k+tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f6oryBWOatloGAiHYyz8+GyzgyaU5sCa3Scs+i9YXlI=; b=eGBXpmosEDf3/tIlRHdOXdh0IY81FyHd2o3Gl0X7hdZgxOvLnRDvjQOh/Wa4s566dg I74D42IYckmqodUHSAL2UJvSsDPQKdYM8y8KByMIJ4dBfChnR4xhVd1QYcMCcYGpmn2L SzptzdTG4qEdyfcQxLj5gehNRG70LINARu4sDOB893FywndxiR7jlo1D91jfbqCLYhhL hfT/bRtsU1ekbQNNhDuVpzlNeTFMwKpC33Stx8gL7Mp+4PityuLQE7YJJwI0n1WdzqrF zxr3/pFyAF3G6hWbEZO9N2lWLa8+ZMXHVsZrkq5j6Ng2EVyppst8L1SXouyFPwFRvEXi 4k5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=D81gtj3g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ga23-20020a1709070c1700b007adffbaa908si4279985ejc.916.2022.11.02.10.40.25; Wed, 02 Nov 2022 10:40:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=D81gtj3g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231572AbiKBRjY (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231316AbiKBRjB (ORCPT ); Wed, 2 Nov 2022 13:39:01 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564BB24096; Wed, 2 Nov 2022 10:38:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EC87DB82420; Wed, 2 Nov 2022 17:38:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9045CC433D6; Wed, 2 Nov 2022 17:38:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410732; bh=oLdI0UN3bIk1n9xDiM9bptnCKiq/HHUtln4OkDfO7F0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D81gtj3g9EyA+4g0HtNJ9KHAJs1/JJBKtOQlMmt5JQzUB5f3pS7ZlqavsIz6Snk4h YMqHagmwxyfAttiwKzjNJSSBoaWTIY1Knlai/WVr6mSgxmHAfoOSXHwvAh8E+08+OH z1cuWQquzrH4G+sPohsIjqB4HWCEzwX221X8SF6eIYm+rhbXzImfjy+4A2mYURoBCT thDb7Oc1/8ilEfKPe5KNLBEi/AsLMNYonIAiAiDQXq1F7PZOf+o/G5RgSfKzGKqE6H pXi0b4Z7/60ym5xZ/dNS2b3bFYZU1KeRW4ukVWgnPInM/JG/8NIajhLVnqaVwvtIa/ bIREuw0zGG0og== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 2 Nov 2022 12:38:39 -0500 Message-Id: <20221102173843.409039-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> References: <20221102173843.409039-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748406998438752116?= X-GMAIL-MSGID: =?utf-8?q?1748406998438752116?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v7: no changes v6: no changes v5: add back reg_shift v4: no change v3: removed unnecessary property in "altr,sysmgr-syscon" --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..55c5e1fdddc7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..849b46dd8098 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { From patchwork Wed Nov 2 17:38:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14411 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp45899wru; Wed, 2 Nov 2022 10:40:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM692ZRJcFogCvPhWw+sApJlkhuR5wiJ1ymGL00D7b1JqKh3iKisklyc+FbwuzEfoYYgoGwT X-Received: by 2002:a17:903:244a:b0:187:10f1:9f91 with SMTP id l10-20020a170903244a00b0018710f19f91mr22538977pls.37.1667410822200; Wed, 02 Nov 2022 10:40:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667410822; cv=none; d=google.com; s=arc-20160816; b=WZ6olLEMara4VIbBIN/Hh13gA40tF5wFJSLJxOwGOLNzN6Q26aYbpSz7CSyJu7ndsB cSJ3WDo/Q9Z2bCBWHm9L6iosuBlg28JDN9dG8gxxVg5Kt7zGDGu7TUT0kGcS3lZdcUec frsF8iDXnLDqrhRtLrB1+4PWD4Z6/4k7DT0JJgMvG03cZAQwdJBHQ4/4gXMWdeCJQA9H 011CadrG1tNm27b3hU8LfGbLM91GEblX0fpNTeFGJXq9dmv1Gv92XM89Sxnd+516cHO8 h3RRFejBeuucahgZLYlQ2mKvBXRt7cbFyxEtHyy0pDCz83qdMNBjfwxTyxpMA2RlWABN 32Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a99/sU26Jv3f/jBfc4M0jdtiSvg0iFDx2pTLY5X8Amo=; b=0+9LUpjswzJHV1VXBuCxqDefntp2vkwvd+mwmctuDQHNVpXuxzMrex8lY619hXRSxU xubUxJxrHfM5d1LH2TT8/r4+rI1H9q6t5oeTP1F6b74bWEt5sep6ycGuiSpicSTx4Qa4 xfhN29ICf/BdCJ9CYqUoUpTmsk10RHDxg1NrtCBwpH34TCqxlsDIcKBCI0rsX4RdqEal PjYUzZohGQe0ca6EjApiF8ODvVzZk0sYJkixlW+SJIXUasi2USJt85RsJaAlUw7k76w0 WtghzShCbyeaYg0OeI9BdM+0uje1juQAUTvs7mDP/JcEd3YC+Yf3cohMKkkrBWJyxFWg FPqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=KvHK87X3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lb12-20020a17090b4a4c00b00201d6d4cc79si3501069pjb.113.2022.11.02.10.40.09; Wed, 02 Nov 2022 10:40:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=KvHK87X3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231546AbiKBRjU (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230442AbiKBRjA (ORCPT ); Wed, 2 Nov 2022 13:39:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 563541E729; Wed, 2 Nov 2022 10:38:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E0F9661AF9; Wed, 2 Nov 2022 17:38:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9C14C43141; Wed, 2 Nov 2022 17:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410734; bh=Fbe89/u5hYuerS0IUMgE9aNX3engI+3rWO1QlQHBlZI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KvHK87X3Xh8LSAaG+w/bovqcRqKr/RGrVEbwPAQ8HT57OYil0vNHXaeqqlpGkQNar 0RO+gQwgdne0m/+VWiBqev3iEozUVgdryIgHynTcurAbUroAZ/BnEZAfLYhMga/fIf JBWWVq686yeFnxZzA2uTxrzzjrkSXayE9afaZqBzDQKYXHina1moaJaFkmT05GC+g1 DvvKQxkxz5Hx2xYJ9s7ms4024kTM+n0hOVdOfzYXcqNeeVOXF8QAtq4cG/az5gZIfQ Rj3B1UnvikVu7BiR33JWaElAbPW+fdJS8dOvUTMOHH3RkVzIzUqRp8HbulQ0HNG0GB ULeXa3Q5kKlCw== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 2 Nov 2022 12:38:40 -0500 Message-Id: <20221102173843.409039-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> References: <20221102173843.409039-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748406970555079279?= X-GMAIL-MSGID: =?utf-8?q?1748406970555079279?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v7: no changes v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + arch/arm/boot/dts/socfpga_arria5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2459f3cd7dd9..604fc6e0c4ad 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 { clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..b6ebe207e2bc 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 { clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index ad7cd14de6b6..41f865c8c098 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -73,6 +73,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 64dc0799f3d7..d3969367f4b5 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -12,6 +12,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &eccmgr { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 22dbf07afcff..b531639ce7dc 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 319a71e41ea4..a9d1ba66f1ff 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index bd92806ffc12..3b9daddf91cd 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,5 +18,6 @@ memory@0 { &mmc0 { /* On-SoM eMMC */ bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; status = "okay"; }; From patchwork Wed Nov 2 17:38:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14413 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp46209wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n24-20020a056402515800b004617f587912si15075622edd.279.2022.11.02.10.40.44; Wed, 02 Nov 2022 10:41:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=LV5blLJ4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbiKBRj1 (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231458AbiKBRjC (ORCPT ); Wed, 2 Nov 2022 13:39:02 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F67927CCD; Wed, 2 Nov 2022 10:38:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4E36661B04; Wed, 2 Nov 2022 17:38:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8DA53C433D6; Wed, 2 Nov 2022 17:38:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410735; bh=j2JZZklAUwIF0SbgFmqZfYU/oISYRUECmh9pSZ4xh4g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LV5blLJ4pLXF9oEEXp5lAHCY2r4yACyhuu4LeY4aHiThpoQwb0UVh4wx2m0yd/cck /kSTxByHfgbvyXV5D8sgpm+C3ewIjQbXOH/HhPFEk7sWn9r+VkfClWI79U39r0322l ++FUpkZW+VSzgCcCTHuuGkUis1z8xOFJqxDCqBBUEPryipmWYJ2xFk0b174PCAnprh E7gRpX2GKe6w90RbtRP8MD+HIixVCnok1o3bw10Di2MZMb+9jWfNCYTHrnc7Ifp88K s/gf66oT76EOa3AKqCaD5ONJrwmWhTjb11z07gbMxqHL1NpKW6w2RedDKD+tmsuxTk rbQzJsfSpj8Vg== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Wed, 2 Nov 2022 12:38:41 -0500 Message-Id: <20221102173843.409039-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> References: <20221102173843.409039-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748407020225518188?= X-GMAIL-MSGID: =?utf-8?q?1748407020225518188?= The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v7: use dev_warn if clk-phase-sd-hs is specified, but "altr,sysmgr-syscon" is not found v6: not getting the clk-phase-sd-hs is not a hard failure v5: change error handling from of_property_read_variable_u32_array() support arm32 by reading the reg_shift v4: no change v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations --- drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..13e55cff8237 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset, reg_shift; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc < 0) + return 0; + + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n"); + return 0; + } + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, }; From patchwork Wed Nov 2 17:38:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14414 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp46231wru; Wed, 2 Nov 2022 10:41:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5OHHc+StkF7QELoLVJ2YZ8JspNAnXZ3MLGLLoSta3km9Xj/kv5DR9QZs4hgkNIHKE0UeBl X-Received: by 2002:a05:6402:348b:b0:45c:b22b:c4a9 with SMTP id v11-20020a056402348b00b0045cb22bc4a9mr26640478edc.65.1667410873365; Wed, 02 Nov 2022 10:41:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667410873; cv=none; d=google.com; s=arc-20160816; b=k8KmVe0NrMRFbSrVWM8pi59rC5gIVR2ob8KnDrPAnFH1mQaDYlLCDYs7BsgUHwS1iN HDGl9F5Hv7sr6ysh4fRfGd6meUfMNUwy2RgzqQY9M9HPWaK3yEdJAeXZGMp/QMZ6ukx5 Ml2BdDWZUoRdvvvoz0D1LepImYT73fD94YOiAaYTKEHtHi+DeMcB1WnZhsFwikngv/Hb bU4yWP+gAfjpFPnIt8UUoxaH8MUDKUakbWuzVnNNhe5UE68G+f21ICHHjtTiRIy6rrxY sORIOkIbOMQu/lKILVf1uC+vrPRZkveweSmRnAGXXv+Hxoo78uDfguOo/pHyIIHQoHaP 37GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=V9ZImdUnQwSp4m9d2Q+F4jUooEDS7gkCcbPWxSuZLUA=; b=pzxIpnQcSBUL4CsEA9vbLr8GbAyJlDLjniAbyr2RLXBr1s5pAsFlK8Y/xv1GTZ//Se H4oLGDWKy4iBWZKjDk+wrAYxThF21Rq7dmwMDcnjG4gdhPdWQ4ucrVByGoSeDizBuMMX VakgIe5DQv1skT8Wr4G4989O4kAbilWOkPbi8XPtp2V8lEsEcTYDWOtoUAhlB/uBJwxN s34Tc+s2Gam9xQ54pQ2C2QiZhoMgHEhXKMhg9vJ5Y8SAJ50q0P8cwQ2fxpYBnvDOC8pM YsyZo925wT4ZR3Xv8CKmeNOVyhlbC/go5Qn/VEIJ6sNqdpKF+suJzQcC0ALOmmYiH60k 0TYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=aAm8uEmN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hv9-20020a17090760c900b007919388d2d1si17128308ejc.970.2022.11.02.10.40.49; Wed, 02 Nov 2022 10:41:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=aAm8uEmN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231591AbiKBRja (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231459AbiKBRjH (ORCPT ); Wed, 2 Nov 2022 13:39:07 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 151532AE1C; Wed, 2 Nov 2022 10:38:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2AD261AED; Wed, 2 Nov 2022 17:38:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F390DC433C1; Wed, 2 Nov 2022 17:38:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410737; bh=vJuL+V48MkqMm8umZo+EHyh6FIjX/Bgwb9AdgXLAKIg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aAm8uEmN56f4KB3zdtZ8hwuFhHpAdEd9p10eDWNIB2zV3dv7ZQOXymJ5y8jIWq7Nw KMqJ+HWnu1yThqQw3/WTjRciSZkgHVyP75NgSK0K0F4M47D9FQKkZO97I6eRDWmjzn ETzoLunI/hhRk1zM3x7R77EhxVZ+XT0HBtI3XfL058rUrhG7vWYqH7IJGQ3eiDc123 mUXTPou6DpbqDNVRzag51FHyeha73gtpfgl6ZHW57wrqXvzbR2xMg/KEjCNeT+ROfM QXk9G6zY2OsJWX0qXo9x0MQXoe3VPL8kxztE4ixNDECDmG/e2GVzj0whjiOHQ8Z7P7 ml66I7wkDhKew== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Date: Wed, 2 Nov 2022 12:38:42 -0500 Message-Id: <20221102173843.409039-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> References: <20221102173843.409039-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748407024140057519?= X-GMAIL-MSGID: =?utf-8?q?1748407024140057519?= Now that the SDMMC driver supports setting the clk-phase, we can remove the need to do it in the clock driver. Acked-by: Stephen Boyd Signed-off-by: Dinh Nguyen --- v7: add acked-by v6: remove unused clk_phase in clk-gate.c v5: new --- drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------ drivers/clk/socfpga/clk-gate.c | 61 --------------------------- drivers/clk/socfpga/clk.h | 1 - 3 files changed, 130 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 738c53391e39..7cdf2f07c79b 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - - hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); - if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) - regmap_write(socfpgaclk->sys_mgr_base_addr, - SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); - else - pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", - __func__); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_gate_clk_recalc_rate, }; @@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node, { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - - socfpga_clk->sys_mgr_base_addr = - syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", - __func__); - kfree(socfpga_clk); - return; - } - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 53d6e3ec4309..3e347b9e9eff 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - struct regmap *sys_mgr_base_addr; - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); - return -EINVAL; - } - - for (i = 0; i < 2; i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); - regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, - hs_timing); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_clk_recalc_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, @@ -172,7 +118,6 @@ void __init socfpga_gate_init(struct device_node *node) { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -218,12 +163,6 @@ void __init socfpga_gate_init(struct device_node *node) socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d80115fbdd6a..9a2fb2dde5b8 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -50,7 +50,6 @@ struct socfpga_gate_clk { u32 width; /* only valid if div_reg != 0 */ u32 shift; /* only valid if div_reg != 0 */ u32 bypass_shift; /* only valid if bypass_reg != 0 */ - u32 clk_phase[2]; }; struct socfpga_periph_clk { From patchwork Wed Nov 2 17:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 14415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp46305wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id gt41-20020a1709072da900b0073d9c412570si20852953ejc.785.2022.11.02.10.41.03; Wed, 02 Nov 2022 10:41:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IesK7MHd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231478AbiKBRjf (ORCPT + 99 others); Wed, 2 Nov 2022 13:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231377AbiKBRjJ (ORCPT ); Wed, 2 Nov 2022 13:39:09 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C21C2494F; Wed, 2 Nov 2022 10:39:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id AD838B820D6; Wed, 2 Nov 2022 17:38:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FC89C4347C; Wed, 2 Nov 2022 17:38:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667410738; bh=rZM/Jb1cF/J5Dk3UhHZ90vCNfl/3XrVYW+A+ti6fTZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IesK7MHd5dukyAch713I2OIRLuxBIEKDFThjLDy+6HpPA7XO44jmY/IudmGKOzHhI fhtLEZHiZPF3W618g13kxdNg2tnI4NvyOZVJqmQmBUa8J+c1uO4pVk94gdlzrMIDXa bh6ISUfiDFu5i7tUpvvdvfDuY7hs4NPSULfnevvj7QLa3/supqr3azusXRue9rh/LK PVG9xE+acBHC301oQ2eB1kctQf1wlDNEESIjPMK7FctYNwYgra+KBbTRuT0nitNDCM 6e3C5/gqs+ppnV+goFfPJzzeDrCfxJrlMY5tTiBQ1z0SebI5RLu4jbBSSoPeFOFO+X 71MFSiTvHTeng== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv7 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Date: Wed, 2 Nov 2022 12:38:43 -0500 Message-Id: <20221102173843.409039-6-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> References: <20221102173843.409039-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748407039118283536?= X-GMAIL-MSGID: =?utf-8?q?1748407039118283536?= Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen --- v7: no changes v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 604fc6e0c4ad..a2419a5c6c26 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index b6ebe207e2bc..eb528c103d70 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk {