From patchwork Fri Aug 11 07:17:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 134345 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp910447vqi; Fri, 11 Aug 2023 00:19:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG6HRcIuEINH0KmrvY3940pBVy5qy9F1AfKUracCY2kVeQ8HoQ8wLSbVXQUJWMVqyTMPRpH X-Received: by 2002:a17:907:a068:b0:99d:626f:adb with SMTP id ia8-20020a170907a06800b0099d626f0adbmr978929ejc.58.1691738397614; Fri, 11 Aug 2023 00:19:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691738397; cv=none; d=google.com; s=arc-20160816; b=bwaEW1k6i2gxiq98Svi3WDYhagJS+t23AY8JN6J3OyO4VTJF/C1xl5zKin4Owk6n9o 5ceZi2co3NmdVDDi9dMh7lmYbEa/OGGJTAUyme4Nm7bIzNCG7PCXleYJpatWVQ4XznNo hXWaz3QZxwxYaX8S92Gr2SsPGN7VRKBlZBFzHWASLOWizJE2jOT8ksdeH9NKVsP+rgpr dcZ92MkuZRry4Jgw1hMXY7rGeccnRNagVE8rcM04jLgmVUHKGNdHmYlnQRXS+uPT8g6E B+F8BTb7aEWkKawu52IsVsQXRzD2YrINSJfhAjL6hM99DCE6ER60DsTepnbyvlyi+eNs f6yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=q15CXZsdlaEK/CtHNieLgPzABzVc3ix5LNr/48IM85o=; fh=PmVSnvRlVeKkg+dPKzMCyvykdI2+tUdRpMZVt54Vt9k=; b=JrDl+u7DwpmEwLfOO29DaskWk3mAdgq3Fr0/ayfCtq856nsY2Ri1avu1GivlkWAluO HlGU1kVTODtkEck8HRnzcdyFBfkCmSvt/MK4J/GM830Cmk7FUIaPWCDC6YdTCj7es/iX opC58FfEBosiax1DpJFn2uDxF0IY0mXhblQZ41K77ayi2XJscHrPXVhz8KJYOycGgazw 6SnWjvXpJF3ZGcZfPqnjGQWLHn+rM1LH1Dxi7grEvuGxF9U8wi3IUh3bF0lAwQu2T4hW t6D4xUIar2Y2+kwRJhgVVDAha1oaVD9djTsFRuXdpFume/kfBTgvz2yVcTgkUbd9U2Ak OXfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=j12T9bPE; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id h26-20020a170906829a00b00996e0a8a2dfsi2852714ejx.78.2023.08.11.00.19.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 00:19:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=j12T9bPE; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 85BFA3858020 for ; Fri, 11 Aug 2023 07:19:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 85BFA3858020 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691738396; bh=q15CXZsdlaEK/CtHNieLgPzABzVc3ix5LNr/48IM85o=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=j12T9bPEs0En/1Dt55LJ4nIKYbogxNp4+yuJ0H3u1k7swdIyuEKlaIWN1jyFOsMSS Xk4B+GEA6EfOEDXkRDHyKYaNlFPYy0/85d0v7nWr6D0+1OgGKvTEaxWwbCEK6xX7rf 9lQBNX6Qa9MCYKJqRB+GwajBDRfVoBg/UHOhibaY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 5201B3858D20 for ; Fri, 11 Aug 2023 07:19:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5201B3858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="361753656" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="361753656" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 00:17:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="767577580" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="767577580" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 11 Aug 2023 00:17:50 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8377B1007821; Fri, 11 Aug 2023 15:17:49 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMADD rounding mode intrinsic API Date: Fri, 11 Aug 2023 15:17:48 +0800 Message-Id: <20230811071748.486528-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773916281695202309 X-GMAIL-MSGID: 1773916281695202309 From: Pan Li This patch would like to support the rounding mode API for the VFMADD as the below samples. * __riscv_vfmadd_vv_f32m1_rm * __riscv_vfmadd_vv_f32m1_rm_m * __riscv_vfmadd_vf_f32m1_rm * __riscv_vfmadd_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmadd_frm): New class for vfmadd frm. (vfmadd_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmadd_frm): New function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-madd.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-madd.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 60c6e16f6ae..7476cdc317d 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -447,6 +447,29 @@ public: } }; +/* Implements below instructions for frm + - vfmadd +*/ +class vfmadd_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + false, code_for_pred_mul_scalar (PLUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + false, code_for_pred_mul (PLUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2211,6 +2234,7 @@ static CONSTEXPR const vfmacc_frm vfmacc_frm_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj; static CONSTEXPR const vfmadd vfmadd_obj; +static CONSTEXPR const vfmadd_frm vfmadd_frm_obj; static CONSTEXPR const vfnmsub vfnmsub_obj; static CONSTEXPR const vfnmacc vfnmacc_obj; static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj; @@ -2450,6 +2474,7 @@ BASE (vfmacc_frm) BASE (vfnmsac) BASE (vfnmsac_frm) BASE (vfmadd) +BASE (vfmadd_frm) BASE (vfnmsub) BASE (vfnmacc) BASE (vfnmacc_frm) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 28eec2c3e99..5850ff0cf2e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -164,6 +164,7 @@ extern const function_base *const vfmacc_frm; extern const function_base *const vfnmsac; extern const function_base *const vfnmsac_frm; extern const function_base *const vfmadd; +extern const function_base *const vfmadd_frm; extern const function_base *const vfnmsub; extern const function_base *const vfnmacc; extern const function_base *const vfnmacc_frm; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index c84e052c1a9..04f3de1275c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -357,6 +357,8 @@ DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops) // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c new file mode 100644 index 00000000000..00c9d002998 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmadd_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmadd_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmadd_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmadd_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmadd_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmadd_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmadd_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmadd\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */