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Signed-off-by: Thomas Gleixner --- arch/x86/mm/init.c | 1 - 1 file changed, 1 deletion(-) --- diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 8192452d1d2d..f1697a522845 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -20,7 +20,6 @@ #include #include #include /* for MAX_DMA_PFN */ -#include #include #include #include From patchwork Thu Aug 10 18:37:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp667157vqi; Thu, 10 Aug 2023 13:24:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEbK2rP1l9UxUtM8SOwe2jvkwwveNm9Kk62ZYqUEP5BmIIhqZoRW25ALprm9GTERBNf1ZeY X-Received: by 2002:a17:906:1dd:b0:99b:f58d:1c49 with SMTP id 29-20020a17090601dd00b0099bf58d1c49mr3225274ejj.53.1691699093344; Thu, 10 Aug 2023 13:24:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691699093; cv=none; d=google.com; s=arc-20160816; b=uYjyzBE9TYar9cviPPVglNjq/KmPZqmaBZjpxxWYe+/9EECfcLgpELZFfK8PzRVGVN EtT+dSuLwRsaZSYxpeDZEACqAfT8CDOssbblhnyUnlK8xVIO0f67BHjADVzJcrNDDgIv ku5iv8KGIqfKIt/1L0/7cWPJMykV29x5N6Mo5nl5AquRtPQh0cV77pzr3kmcOD/lnDuH VNHPTSG02mRW1FsDoCWi09D6pFpawDRF5hOk+frD1son//T6jwFxVDF7aDkl+MVmZUlo yfWAowGjcacLvUhy6/FsbJ72jWnp3DOGHr90c9ztpD7CiKRLbD0+bxgbOfwLPs7l2Hen 9OyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=HoMtRyVAokHsr4z8w1z/t7PYpfEqpx3960He4ZbXI2X6+pbmELOeNbtx0avrgyYHsZ RSJ8TZjAL6Jw4OREre6kdDJ11/9ye06m+Wk4kC/drvEn8zV2wXJQTh0WNbLj9z8l9a+Z bSFfEVaK7l3XceNbWSgOQ3V0uEu8ce1ZMybs2jfMrAfH43/nG7w/ZqIu1VKwkY6Mrcic cJSmo6DVRcN8hkbXNJ2Rz+jRuflTF1g+GMhqYL5kgQQdjouSsf5jg3Ja0mkhjVg8bsZm fKMJnU83fc1+mw6ov88f0j9yV/T+AQgsbt5DIBobCnooAFDB/6u/kMrO2ujiEtHPKKlw CDig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=evyP1aTS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gg8-20020a170906e28800b0099396546ffesi2048879ejb.768.2023.08.10.13.24.27; Thu, 10 Aug 2023 13:24:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=evyP1aTS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235599AbjHJShe (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235503AbjHJShc (ORCPT ); Thu, 10 Aug 2023 14:37:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 400B726B8 for ; Thu, 10 Aug 2023 11:37:31 -0700 (PDT) Message-ID: <20230810160805.081212701@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=evyP1aTSj4s+pDdHb+BlplYfAbRCDo2B8Saee/j3qKDNevs3VGiT8G6N4fVsDzmnFuKHim 0fMD34+++ma9W8zm15gwcgIponOD0ltjR/BXOja/3ix6CDB9z18azSlfCI0F9OzUUuxCuE Ok2JLj+EW9WLwLGVsZ6cCHjED/CFm9q4dOF3lIm/Zv8V9cOh6SPJ1/iu1WyaqLLdz3+h6C d+gMba+0F2WmOsdRbfky9ZOy8u2vzcRTw/ek4dn6+wEbWiHUkM5JoLACzF+zBiEYJ+O/q1 GVcpi2y2FfcY/T6MrcwKOFIvPOOuszJebCNn3dXCwJx8UX2tG7q0trXcdl1YZw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=tyiZuKFPNqJKPORQQbqy97g3KC7NfzBEm8aqMLunZGyos2ChEEBfjbsjwlPNpG4VMXVqHc /pDVZVvxJQyTWJAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 02/30] x86/microcode: Hide the config knob References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:29 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773875068615244388 X-GMAIL-MSGID: 1773875068615244388 In reality CONFIG_MICROCODE is enabled in any reasonable configuration when Intel or AMD support is enabled. Accomodate to reality. Requested-by: Borislav Petkov Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 38 --------------------------------- arch/x86/include/asm/microcode.h | 6 ++--- arch/x86/include/asm/microcode_amd.h | 2 - arch/x86/include/asm/microcode_intel.h | 2 - arch/x86/kernel/cpu/microcode/Makefile | 4 +-- 5 files changed, 8 insertions(+), 44 deletions(-) --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1308,44 +1308,8 @@ config X86_REBOOTFIXUPS Say N otherwise. config MICROCODE - bool "CPU microcode loading support" - default y + def_bool y depends on CPU_SUP_AMD || CPU_SUP_INTEL - help - If you say Y here, you will be able to update the microcode on - Intel and AMD processors. The Intel support is for the IA32 family, - e.g. Pentium Pro, Pentium II, Pentium III, Pentium 4, Xeon etc. The - AMD support is for families 0x10 and later. You will obviously need - the actual microcode binary data itself which is not shipped with - the Linux kernel. - - The preferred method to load microcode from a detached initrd is described - in Documentation/arch/x86/microcode.rst. For that you need to enable - CONFIG_BLK_DEV_INITRD in order for the loader to be able to scan the - initrd for microcode blobs. - - In addition, you can build the microcode into the kernel. For that you - need to add the vendor-supplied microcode to the CONFIG_EXTRA_FIRMWARE - config option. - -config MICROCODE_INTEL - bool "Intel microcode loading support" - depends on CPU_SUP_INTEL && MICROCODE - default MICROCODE - help - This options enables microcode patch loading support for Intel - processors. - - For the current Intel microcode data package go to - and search for - 'Linux Processor Microcode Data File'. - -config MICROCODE_AMD - bool "AMD microcode loading support" - depends on CPU_SUP_AMD && MICROCODE - help - If you select this option, microcode patch loading support for AMD - processors will be enabled. config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -54,16 +54,16 @@ struct ucode_cpu_info { extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern struct microcode_ops * __init init_intel_microcode(void); #else static inline struct microcode_ops * __init init_intel_microcode(void) { return NULL; } -#endif /* CONFIG_MICROCODE_INTEL */ +#endif /* CONFIG_CPU_SUP_INTEL */ -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern struct microcode_ops * __init init_amd_microcode(void); extern void __exit exit_amd_microcode(void); #else --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -43,7 +43,7 @@ struct microcode_amd { #define PATCH_MAX_SIZE (3 * PAGE_SIZE) -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern void load_ucode_amd_early(unsigned int cpuid_1_eax); extern int __init save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -71,7 +71,7 @@ static inline u32 intel_get_microcode_re return rev; } -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern void __init load_ucode_intel_bsp(void); extern void load_ucode_intel_ap(void); extern void show_ucode_info_early(void); --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only microcode-y := core.o obj-$(CONFIG_MICROCODE) += microcode.o -microcode-$(CONFIG_MICROCODE_INTEL) += intel.o -microcode-$(CONFIG_MICROCODE_AMD) += amd.o +microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o +microcode-$(CONFIG_CPU_SUP_AMD) += amd.o From patchwork Thu Aug 10 18:37:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134155 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp619154vqi; Thu, 10 Aug 2023 11:56:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGNjnZTjl20V/8GYwRhYTOfHobJjK9WIVUDt0o0bqQXp1rBmWXF3TOQsyOywwgizfvy11HH X-Received: by 2002:a17:906:5189:b0:99c:f837:bab4 with SMTP id y9-20020a170906518900b0099cf837bab4mr2828943ejk.76.1691693788831; Thu, 10 Aug 2023 11:56:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691693788; cv=none; d=google.com; s=arc-20160816; b=mbDnTOBDflIkqENf0zWjuZW+4MHUWXhq+Jmy/nGlGP1MR57shriDc+YQrEAsJyL+G5 e2Y52vgCDx3bromaKtSukTZ8Ww7QOI4Pf7X7uId6o74vyLUGU7cf8dsAbBJXrZdACZOt LdsqCSr1doIUi0v3fmdWZnjDpxocVgTiX37DFxf0nAIaR2U5uF6wmI6wvAONh6ANz0zv 2XpN+BTdwcFa4FHJ1q5cWdHaEr16EY5sGsPprBj75+FjXmfd89yWa+t5SaN94ZH0lv1l FvHNpiWJoPU5HoD64O3Vlp3sBC8gbWQQdAZQRj99DU1L4vWfepxZ4ybLU3uM0x6oAolF pcKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=bal3enkn+t4/7yJ6RyIGi77vrlIBjAf9vF+oNGJwCIA=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=Kg7ntgw8sviGQ8YXqSN7N+SgqTXBHq+XiqH3i6425dUNBAfljGJdrCZUKhg1r9wNVy JDZgJZXCx4jayK9zP4YVPHQ7M0j3nL3InEtCsx/fkMLaVhJYvN/dCZZ0tHV2V76dZVd3 e0ZfufkgUvY6Axfd3vPgcIrl8XZfj8cz+h6pLpuwhVmJjwW3QdEwpWNBtc7wAu2diiYu vJrEu0H4aa1uaUkwBfV+HgUjfYXIPhbhGZgRypgagFlOgUAKCIbxF/GbtJqnnHMImpvL prvBH/IFwQJ4/4ve7vQA7jR2am77HXFx4W9luG0plNlj6pGnwR+raAIFlApX54AQ4cFM /dEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=iyizzaVQ; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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s=2020e; t=1691692651; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bal3enkn+t4/7yJ6RyIGi77vrlIBjAf9vF+oNGJwCIA=; b=6T3GCJbxfDaldPzyA7iPWAL0snJa+yyEkON49npzUUxQ4Skh9wzhU4/rRJNJkdAiFVeuGN jAKfCbOSyP+FNDBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 03/30] x86/microcode/intel: Move microcode functions out of cpu/intel.c References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:30 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773869506333684176 X-GMAIL-MSGID: 1773869506333684176 Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/intel.c | 174 ---------------------------------- arch/x86/kernel/cpu/microcode/intel.c | 174 ++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+), 174 deletions(-) --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -184,180 +184,6 @@ static bool bad_spectre_microcode(struct return false; } -int intel_cpu_collect_info(struct ucode_cpu_info *uci) -{ - unsigned int val[2]; - unsigned int family, model; - struct cpu_signature csig = { 0 }; - unsigned int eax, ebx, ecx, edx; - - memset(uci, 0, sizeof(*uci)); - - eax = 0x00000001; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - csig.sig = eax; - - family = x86_family(eax); - model = x86_model(eax); - - if (model >= 5 || family > 6) { - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig.pf = 1 << ((val[1] >> 18) & 7); - } - - csig.rev = intel_get_microcode_revision(); - - uci->cpu_sig = csig; - - return 0; -} -EXPORT_SYMBOL_GPL(intel_cpu_collect_info); - -/* - * Returns 1 if update has been found, 0 otherwise. - */ -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) -{ - struct microcode_header_intel *mc_hdr = mc; - struct extended_sigtable *ext_hdr; - struct extended_signature *ext_sig; - int i; - - if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) - return 1; - - /* Look for ext. headers: */ - if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) - return 0; - - ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; - ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; - - for (i = 0; i < ext_hdr->count; i++) { - if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) - return 1; - ext_sig++; - } - return 0; -} -EXPORT_SYMBOL_GPL(intel_find_matching_signature); - -/** - * intel_microcode_sanity_check() - Sanity check microcode file. - * @mc: Pointer to the microcode file contents. - * @print_err: Display failure reason if true, silent if false. - * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. - * Validate if the microcode header type matches with the type - * specified here. - * - * Validate certain header fields and verify if computed checksum matches - * with the one specified in the header. - * - * Return: 0 if the file passes all the checks, -EINVAL if any of the checks - * fail. - */ -int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) -{ - unsigned long total_size, data_size, ext_table_size; - struct microcode_header_intel *mc_header = mc; - struct extended_sigtable *ext_header = NULL; - u32 sum, orig_sum, ext_sigcount = 0, i; - struct extended_signature *ext_sig; - - total_size = get_totalsize(mc_header); - data_size = get_datasize(mc_header); - - if (data_size + MC_HEADER_SIZE > total_size) { - if (print_err) - pr_err("Error: bad microcode data file size.\n"); - return -EINVAL; - } - - if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { - if (print_err) - pr_err("Error: invalid/unknown microcode update format. Header type %d\n", - mc_header->hdrver); - return -EINVAL; - } - - ext_table_size = total_size - (MC_HEADER_SIZE + data_size); - if (ext_table_size) { - u32 ext_table_sum = 0; - u32 *ext_tablep; - - if (ext_table_size < EXT_HEADER_SIZE || - ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { - if (print_err) - pr_err("Error: truncated extended signature table.\n"); - return -EINVAL; - } - - ext_header = mc + MC_HEADER_SIZE + data_size; - if (ext_table_size != exttable_size(ext_header)) { - if (print_err) - pr_err("Error: extended signature table size mismatch.\n"); - return -EFAULT; - } - - ext_sigcount = ext_header->count; - - /* - * Check extended table checksum: the sum of all dwords that - * comprise a valid table must be 0. - */ - ext_tablep = (u32 *)ext_header; - - i = ext_table_size / sizeof(u32); - while (i--) - ext_table_sum += ext_tablep[i]; - - if (ext_table_sum) { - if (print_err) - pr_warn("Bad extended signature table checksum, aborting.\n"); - return -EINVAL; - } - } - - /* - * Calculate the checksum of update data and header. The checksum of - * valid update data and header including the extended signature table - * must be 0. - */ - orig_sum = 0; - i = (MC_HEADER_SIZE + data_size) / sizeof(u32); - while (i--) - orig_sum += ((u32 *)mc)[i]; - - if (orig_sum) { - if (print_err) - pr_err("Bad microcode data checksum, aborting.\n"); - return -EINVAL; - } - - if (!ext_table_size) - return 0; - - /* - * Check extended signature checksum: 0 => valid. - */ - for (i = 0; i < ext_sigcount; i++) { - ext_sig = (void *)ext_header + EXT_HEADER_SIZE + - EXT_SIGNATURE_SIZE * i; - - sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - - (ext_sig->sig + ext_sig->pf + ext_sig->cksum); - if (sum) { - if (print_err) - pr_err("Bad extended signature checksum, aborting.\n"); - return -EINVAL; - } - } - return 0; -} -EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); - static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -45,6 +45,180 @@ static struct microcode_intel *intel_uco /* last level cache size per core */ static int llc_size_per_core; +int intel_cpu_collect_info(struct ucode_cpu_info *uci) +{ + unsigned int val[2]; + unsigned int family, model; + struct cpu_signature csig = { 0 }; + unsigned int eax, ebx, ecx, edx; + + memset(uci, 0, sizeof(*uci)); + + eax = 0x00000001; + ecx = 0; + native_cpuid(&eax, &ebx, &ecx, &edx); + csig.sig = eax; + + family = x86_family(eax); + model = x86_model(eax); + + if (model >= 5 || family > 6) { + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + csig.pf = 1 << ((val[1] >> 18) & 7); + } + + csig.rev = intel_get_microcode_revision(); + + uci->cpu_sig = csig; + + return 0; +} +EXPORT_SYMBOL_GPL(intel_cpu_collect_info); + +/* + * Returns 1 if update has been found, 0 otherwise. + */ +int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) +{ + struct microcode_header_intel *mc_hdr = mc; + struct extended_sigtable *ext_hdr; + struct extended_signature *ext_sig; + int i; + + if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) + return 1; + + /* Look for ext. headers: */ + if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) + return 0; + + ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; + ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; + + for (i = 0; i < ext_hdr->count; i++) { + if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) + return 1; + ext_sig++; + } + return 0; +} +EXPORT_SYMBOL_GPL(intel_find_matching_signature); + +/** + * intel_microcode_sanity_check() - Sanity check microcode file. + * @mc: Pointer to the microcode file contents. + * @print_err: Display failure reason if true, silent if false. + * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. + * Validate if the microcode header type matches with the type + * specified here. + * + * Validate certain header fields and verify if computed checksum matches + * with the one specified in the header. + * + * Return: 0 if the file passes all the checks, -EINVAL if any of the checks + * fail. + */ +int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) +{ + unsigned long total_size, data_size, ext_table_size; + struct microcode_header_intel *mc_header = mc; + struct extended_sigtable *ext_header = NULL; + u32 sum, orig_sum, ext_sigcount = 0, i; + struct extended_signature *ext_sig; + + total_size = get_totalsize(mc_header); + data_size = get_datasize(mc_header); + + if (data_size + MC_HEADER_SIZE > total_size) { + if (print_err) + pr_err("Error: bad microcode data file size.\n"); + return -EINVAL; + } + + if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { + if (print_err) + pr_err("Error: invalid/unknown microcode update format. Header type %d\n", + mc_header->hdrver); + return -EINVAL; + } + + ext_table_size = total_size - (MC_HEADER_SIZE + data_size); + if (ext_table_size) { + u32 ext_table_sum = 0; + u32 *ext_tablep; + + if (ext_table_size < EXT_HEADER_SIZE || + ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { + if (print_err) + pr_err("Error: truncated extended signature table.\n"); + return -EINVAL; + } + + ext_header = mc + MC_HEADER_SIZE + data_size; + if (ext_table_size != exttable_size(ext_header)) { + if (print_err) + pr_err("Error: extended signature table size mismatch.\n"); + return -EFAULT; + } + + ext_sigcount = ext_header->count; + + /* + * Check extended table checksum: the sum of all dwords that + * comprise a valid table must be 0. + */ + ext_tablep = (u32 *)ext_header; + + i = ext_table_size / sizeof(u32); + while (i--) + ext_table_sum += ext_tablep[i]; + + if (ext_table_sum) { + if (print_err) + pr_warn("Bad extended signature table checksum, aborting.\n"); + return -EINVAL; + } + } + + /* + * Calculate the checksum of update data and header. The checksum of + * valid update data and header including the extended signature table + * must be 0. + */ + orig_sum = 0; + i = (MC_HEADER_SIZE + data_size) / sizeof(u32); + while (i--) + orig_sum += ((u32 *)mc)[i]; + + if (orig_sum) { + if (print_err) + pr_err("Bad microcode data checksum, aborting.\n"); + return -EINVAL; + } + + if (!ext_table_size) + return 0; + + /* + * Check extended signature checksum: 0 => valid. + */ + for (i = 0; i < ext_sigcount; i++) { + ext_sig = (void *)ext_header + EXT_HEADER_SIZE + + EXT_SIGNATURE_SIZE * i; + + sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - + (ext_sig->sig + ext_sig->pf + ext_sig->cksum); + if (sum) { + if (print_err) + pr_err("Bad extended signature checksum, aborting.\n"); + return -EINVAL; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); + /* * Returns 1 if update has been found, 0 otherwise. */ From patchwork Thu Aug 10 18:37:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134193 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp646898vqi; Thu, 10 Aug 2023 12:48:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHqxrV8FTFj9fwGoA8yLzDJjEO4dKeNABjSaKbk+rfe7J8UHBcgDAbEBVbR70zylxZbiCxh X-Received: by 2002:a05:6402:1358:b0:51d:fa7c:c330 with SMTP id y24-20020a056402135800b0051dfa7cc330mr3077625edw.26.1691696931865; Thu, 10 Aug 2023 12:48:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691696931; cv=none; d=google.com; s=arc-20160816; b=hsgGYZMEU3uw+9HdNchdUvAtRvjgOgGzIZNBnluYlHuUqaSa0fbsWPAEoKYF78bcXh igip6LKG23sBQk8O704+L2OH1/sJ16Lc7gi2Cv9CHAsrYY4zFcRYY2Gcwii1EIb+pfgv FPetb9Y69FFzEkt7hKkJZHAJ1PMngBviUQcNe4iTB/d3SM7h7Bt7Y1+XKv/3PLKcG0la 1vSgq6kpd+TKzN3CebmUZ1Si9laQaF3sknejJEhR4FFIANQ+F+0sqa4M41qHnzmshzgA 2+PFpexHonM0dXT03P1R+9DD12q9Z3gxrOgdvViJzrEGeDxuUiDnkmcktd61XMEBvycx keXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Yla6bgyMGJY6FRDLJy+QJ04amN52g+/SwC5xFVnIX7s=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=ocJH7Dnpc+IA7/KijZG9yOkwJ3BtlgEYys6pDywhl/tyMCOCGqZayM/lEM9JB3BdTB 4GU0+id5c8YtDUcHjxqeDc8AmeoDk1XkbPZo6bf1ps0U8HOsFyoENd7FWgZ+wqpjtYnC JnwP04Z78lPYba+bTjjixte/gqcfEFKpN6b2BeuuIRhJALLjFKj5xTXhugNEEUv+in7x qZ/bFujc+N6wIXcf8t0wwsAaM5+wipwLvh67uKoZ1QIbBmGz0WboD4F7Hd5XCMK/dzEb 8kC1F/UhFuzYlbPRCQCJchfeTjNlGNoAGzJrvC9fZ3nMTEjgzviu0FgwAUra6+ky1AK0 uBiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=zpyeHLs4; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z19-20020aa7cf93000000b005234a115ba9si2028412edx.480.2023.08.10.12.48.27; Thu, 10 Aug 2023 12:48:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=zpyeHLs4; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235653AbjHJShk (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235600AbjHJShe (ORCPT ); Thu, 10 Aug 2023 14:37:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4DD52713 for ; Thu, 10 Aug 2023 11:37:33 -0700 (PDT) Message-ID: <20230810160805.193094420@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692652; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Yla6bgyMGJY6FRDLJy+QJ04amN52g+/SwC5xFVnIX7s=; b=zpyeHLs4q1IIzG3oVdAmqZn6FBkJqTeXYW/6Rft4wXxTLj4ICM7mAf0bUZ885XO1Efbcxq 0/BK6OhoGfXt2fUqNVBhCNwWv5Q4yw5Q1H6CqxP9kz+3adr5RRLnpsGGz9IUk7E8xH2GYT tw7cEDqirwCr/1jyGvSY1QHE7vqXOc/RvjnoFNdxhrvDJbF8e2gemHK/zQrBg1UdLrNmZH Astt7SG5/WI4avhW4veqEhUl7/4ovChAIORW8ByAWAQ4kzuIAVAFxxqfzzJ7UsDEgYwTup zfh4aCxGAsitG1uN+tBNS0ZmI7HimX2C/vZKAcKmDC/oBnQpfU0n4G5lT2uFPA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692652; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Yla6bgyMGJY6FRDLJy+QJ04amN52g+/SwC5xFVnIX7s=; b=pYr3vp6ReAHaL7w5dC/pUfJ4myEvxHIfo6R9M9FKf5GsHmHllXvjBEtQVqcydtqYdJlg8S 0pcA/FBPcDtAYZCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 04/30] x86/microcode: Include vendor headers into microcode.h References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:32 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773872802305017746 X-GMAIL-MSGID: 1773872802305017746 From: Ashok Raj Currently vendor specific headers are included explicitly when used in common code. Instead, include the vendor specific headers in microcode.h, and include that in all usages. No functional change. Suggested-by: Boris Petkov Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 5 ++++- arch/x86/include/asm/microcode_amd.h | 2 -- arch/x86/include/asm/microcode_intel.h | 2 -- arch/x86/kernel/cpu/common.c | 1 - arch/x86/kernel/cpu/intel.c | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 1 - arch/x86/kernel/cpu/microcode/core.c | 2 -- arch/x86/kernel/cpu/microcode/intel.c | 2 +- drivers/platform/x86/intel/ifs/load.c | 2 +- 9 files changed, 7 insertions(+), 12 deletions(-) --- diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 320566a0443d..2e1a9d0582e7 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -2,10 +2,13 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H -#include #include #include +#include +#include +#include + struct ucode_patch { struct list_head plist; void *data; /* Intel uses only this one */ diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index a995b7685223..0531983016c9 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -2,8 +2,6 @@ #ifndef _ASM_X86_MICROCODE_AMD_H #define _ASM_X86_MICROCODE_AMD_H -#include - #define UCODE_MAGIC 0x00414d44 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 #define UCODE_UCODE_TYPE 0x00000001 diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h index f1fa979e05bf..3ca740451a3d 100644 --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -2,8 +2,6 @@ #ifndef _ASM_X86_MICROCODE_INTEL_H #define _ASM_X86_MICROCODE_INTEL_H -#include - struct microcode_header_intel { unsigned int hdrver; unsigned int rev; diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 06015f304cb8..1ea5f822a7ca 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -59,7 +59,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 1c4639588ff9..9fd67e68179f 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index a28b103256ff..dc0a3bed5f6e 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index c9a53e330df3..73a3c22773c2 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -31,9 +31,7 @@ #include #include -#include #include -#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 467cf37ea90a..0ae0c3fd66a1 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -30,9 +30,9 @@ #include #include -#include #include #include +#include #include #include #include diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c index e6ae8265f3a3..390862ab0357 100644 --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -3,7 +3,7 @@ #include #include -#include +#include #include "ifs.h" From patchwork Thu Aug 10 18:37:33 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r13-20020aa7d58d000000b005221edcf201si2036846edq.57.2023.08.10.13.01.46; Thu, 10 Aug 2023 13:02:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="0/fN3PCh"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235705AbjHJShl (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235620AbjHJShf (ORCPT ); Thu, 10 Aug 2023 14:37:35 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FDAE2718 for ; Thu, 10 Aug 2023 11:37:35 -0700 (PDT) Message-ID: <20230810160805.249932786@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692653; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0JPnaj3cEEDg9kfAdYzRsElPoyj/8+m1dAg/elVKOy0=; b=0/fN3PChyKL0HYnGHcp+08GLkN57JlCxlYeEGuIJMBDiB23r1MJsqkAeIJ+aZSp1sCXQuu UeStf4apgxKJhhIK+JvokTYTT26VNjy2S1HOiTU02wxhEXxkM4+kVlmNdCZScnwj8b31W5 gAKCtHsx++AkXk+KTThVhggSWE+kOSGeERIzcX2Fa/Ks1VmSexCOwL2Mv16a+xNAxEFLM5 OKjqYWnOdtVEoOOFg+JicWt9sZebrC2WYf7XFSHqK7TvJ8Pa5KOGyBN+v6wekV8o8Yalzm X4dNVSYdT0RF0f/z0/Oi/j0cV+LPHUGwYGaVhsFC5a/dm+yZaJ6N19N+SU9dvQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692653; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0JPnaj3cEEDg9kfAdYzRsElPoyj/8+m1dAg/elVKOy0=; b=axrq3mlyZqJAinbj9uXKy65atjoCuGvHGlwKHxELThzF8q72FBbQnqnAOatGUBANNs7QLV f+rWzAVE3MWckBBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 05/30] x86/microcode: Make reload_early_microcode() static References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:33 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773873642817154994 X-GMAIL-MSGID: 1773873642817154994 From: Thomas Gleixner fe055896c040 ("x86/microcode: Merge the early microcode loader") left this needlessly public. Git archaeology provided by Borislav. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 2 -- arch/x86/kernel/cpu/microcode/core.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -128,13 +128,11 @@ static inline unsigned int x86_cpuid_fam #ifdef CONFIG_MICROCODE extern void __init load_ucode_bsp(void); extern void load_ucode_ap(void); -void reload_early_microcode(unsigned int cpu); extern bool initrd_gone; void microcode_bsp_resume(void); #else static inline void __init load_ucode_bsp(void) { } static inline void load_ucode_ap(void) { } -static inline void reload_early_microcode(unsigned int cpu) { } static inline void microcode_bsp_resume(void) { } #endif --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -293,7 +293,7 @@ struct cpio_data find_microcode_in_initr #endif } -void reload_early_microcode(unsigned int cpu) +static void reload_early_microcode(unsigned int cpu) { int vendor, family; From patchwork Thu Aug 10 18:37:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp646655vqi; Thu, 10 Aug 2023 12:48:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+qTQHNBjOoL6ZSkQTaB8nMHSY/poMGJXI/3FUuzocKxLJ9v7dGQDgTRBXFoiMpjm0yTcg X-Received: by 2002:a19:750c:0:b0:4fe:2ac1:4151 with SMTP id y12-20020a19750c000000b004fe2ac14151mr2361125lfe.63.1691696898472; Thu, 10 Aug 2023 12:48:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691696898; cv=none; d=google.com; s=arc-20160816; b=yOE2y3QT7FMWMZ4NYwto7xbuF8DxhlTX3H919ajLQ3FmX/yp0Gsvjl6Pz5S+CaNCFJ eWCl3bEyc2S8PnOgicxzqJZR7WIQVi5mqpZy7oFpuRiVBJj5ffEQjUAgi6nLOBxk0CmN Q2WOexR1bc97j2cJ1YqjUHZP5dek2441qC3KfkhSg/xdlR4u4Kl8k2K3R4SVRHHFYHZM d7EgO7Qnzd379qRHz2u9WKop/UVZaCoEKmXbtRKKnp0tvvcmahZLJDH52OProIJngWPX NNYfku0LamxhDjVk60EwQ2imtgDTNiXqPkgCkRDZwEI8sFLiiR0R+geMUto9AshYfUSb l3hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=kRzAe5D8Ty6sdUSFrz8caC1tS6s07rg/biNnW6lm4Xo=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=kYcEHXHM+9Lfk+uCe3j662VWyY4LpmJURPEa0x0AfZ2c8qxktZz9yrhT8g77BMmLgG 9DMyj09F03EgFYB9s1ssKuRp9LOZZGrRmKiTdfsdpOcT2s4jJcF1TMCVG/O/46MHbVI9 yf4LOURiWAKS1znfrSovSZH0q4lVjHl1BnAj/ttI1qEyKCEO6Vy5DcXq5bznPdqNuOZj dWghAafkMp0zfOjpHyFzcCpNtvR4ub+ZRCnWInW7eqa4Q9cNL1h1jShi6KXKyfjVzdDv BY92cmRBsYwxabVUYtaChukLYk3gNPF/kq98/5xZLgXGQjZ3HeXnqEcpXlrYxDQUFGQR /ouw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tAbFx+gV; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n24-20020a1709065e1800b0099cbf068b6bsi1992316eju.588.2023.08.10.12.47.46; Thu, 10 Aug 2023 12:48:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tAbFx+gV; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235712AbjHJShn (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235651AbjHJShh (ORCPT ); Thu, 10 Aug 2023 14:37:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8386271F for ; Thu, 10 Aug 2023 11:37:36 -0700 (PDT) Message-ID: <20230810160805.306362600@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692655; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kRzAe5D8Ty6sdUSFrz8caC1tS6s07rg/biNnW6lm4Xo=; b=tAbFx+gV3dAAHxeTR4TlThnMhnMCtMRpsn3cXur0T2ngyjccq37C4jGQQdrYuIwGLCZh8W ddoIABweZs4SvBK4oR/eqeu/sgu/TbLBFeaDL1+8cyXxxfsmwchApYHYcpDBSkFpUT7dwn UrYmUxQSGIsYnGWGKzGOQG82+85si91fdMKvdYJj8pq6MvGX0JVQEO4jca3qqVdbWdDhmz fmQGXOK0n0H04HB4eHdaBXzZFZdKR+WkWAHPxHP1N563Ia2ZaiFhMBpr/V2yCCUS0xhNMM 1vFgKQLyJPR0JZ3b9ruqSkzCbxOzrGa0z7AOI1EFh9E70i8SZFCOKy0OfIfobQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692655; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kRzAe5D8Ty6sdUSFrz8caC1tS6s07rg/biNnW6lm4Xo=; b=JfQwejENl+HSQeeJLCgU887lBpSDkBcpEegiD5ON07Jd+md53E4XWRrZiBI/NCbLX+vyTF eCAnbKDJU2wW1bCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 06/30] x86/microcode/intel: Rename get_datasize() since its used externally References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:35 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773872766573883031 X-GMAIL-MSGID: 1773872766573883031 From: Ashok Raj Rename get_datasize() to intel_microcode_get_datasize() and make it an inline. Suggested-by: Boris Petkov Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode_intel.h | 9 ++++++--- arch/x86/kernel/cpu/microcode/intel.c | 8 ++++---- drivers/platform/x86/intel/ifs/load.c | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) --- --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -48,9 +48,12 @@ struct extended_sigtable { ((struct microcode_intel *)mc)->hdr.totalsize : \ DEFAULT_UCODE_TOTALSIZE) -#define get_datasize(mc) \ - (((struct microcode_intel *)mc)->hdr.datasize ? \ - ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE) +static inline int intel_microcode_get_datasize(void *data) +{ + struct microcode_intel *mc = data; + + return mc->hdr.datasize ? : DEFAULT_UCODE_DATASIZE; +} #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -90,10 +90,10 @@ int intel_find_matching_signature(void * return 1; /* Look for ext. headers: */ - if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) + if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) return 0; - ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; + ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { @@ -128,7 +128,7 @@ int intel_microcode_sanity_check(void *m struct extended_signature *ext_sig; total_size = get_totalsize(mc_header); - data_size = get_datasize(mc_header); + data_size = intel_microcode_get_datasize(mc_header); if (data_size + MC_HEADER_SIZE > total_size) { if (print_err) @@ -410,7 +410,7 @@ static void show_saved_mc(void) date = mc_saved_header->date; total_size = get_totalsize(mc_saved_header); - data_size = get_datasize(mc_saved_header); + data_size = intel_microcode_get_datasize(mc_saved_header); pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", i++, sig, pf, rev, total_size, --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -60,7 +60,7 @@ static struct metadata_header *find_meta unsigned long data_size, total_meta; unsigned long meta_size = 0; - data_size = get_datasize(ucode); + data_size = intel_microcode_get_datasize(ucode); total_meta = ((struct microcode_intel *)ucode)->hdr.metasize; if (!total_meta) return NULL; From patchwork Thu Aug 10 18:37:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134144 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp611618vqi; Thu, 10 Aug 2023 11:40:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGk6wAdZw5m5ityvLibGyyx2J4UJE6KNkgDRHGpm9hZJ2HeY7G7pgdlXJhMp3vzyyH04OS2 X-Received: by 2002:a05:6e02:1bad:b0:348:fd8b:a17d with SMTP id n13-20020a056e021bad00b00348fd8ba17dmr4517947ili.21.1691692807762; Thu, 10 Aug 2023 11:40:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691692807; cv=none; d=google.com; s=arc-20160816; b=MhgJ5JYz6SWHW9d0eR6yOKVFNdKbKwOUDufWHvq4ZnwcUh9ZVURp8ygxWItWV8eApL PEQ/FuE2qrsWIgpJ9yyPNtHoNXRThbAH/qkQwVUXP+NwKiCAezS0rUdhUpybnWcONg2W 8ITlJrw/WQzYLjahrFo5fqaHZQypsgnYW1OcRy/h6MMraDsfubonWXZw8bSzbFfVtHvL QGnp+9dDfCXOWXDMUvL91146wTDHbCF/GkCZlEUDLWPQn3B07Y6nd1v1G7dQi8yX7M9w n1v5JaX6HzFONQsDO/+flf6HmCNzCV5wgboBz3WLuTlshoVj8gjugQVBr8tFymAk5JgY GOZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=sG/Z1v2dmYrqXzMKn+/H+cbtZ9fNSjBKsYPr23/YsBg=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=NwP3aC5sIehuGj83hLKM+PDgKZUGfhOGmvNzLd/jdnn2xpsZkvnuMAU5tneqtFpJwc aYSK2bUFpSpWyXPChzVUb38Ti+kuRPyYZ2mZi0g4JnzV3BCDZ6aNznDFnnr5Pjfmvy6g k9T/NgyfSrVMIkH/hTmpfVepGdfJqTjqFM9ln+RK7UmxQQhKw3EJMkuN9Yf1YkL/f/I9 twKJkw5XhPWyDW9IkJciZLo51JX7fIbQfTHNZQhKzy+DHpWdTF+cSuyd84tslAGPO97u DcClBiz+tFPZQ/4Cnh0JKFSWyCMoUCk0ZOx3gqdUmtfNSouTLeYGoIk7Z5ciz9puYkb0 hcKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="p74/Z0EH"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bv68-20020a632e47000000b00563ee39a642si1974645pgb.308.2023.08.10.11.39.54; Thu, 10 Aug 2023 11:40:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="p74/Z0EH"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235633AbjHJShu (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235729AbjHJShq (ORCPT ); Thu, 10 Aug 2023 14:37:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71F302715 for ; Thu, 10 Aug 2023 11:37:38 -0700 (PDT) Message-ID: <20230810160805.362918410@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sG/Z1v2dmYrqXzMKn+/H+cbtZ9fNSjBKsYPr23/YsBg=; b=p74/Z0EH7u0nd3EpcQtwzVjHbapeBtTmGzgqdANM82lz+x1CPX1r9wWIvkUPsRSpBUp4Ul DNWobwW9EF1o4M0FjXXEnA3gyWaBSpzI7O5Seh2sw5mQRZlk5hv/fZdcu6R41FGXhEhZXi Q2R6FNVzcHCdsH7xji2JLqbXMcvZGoiO3dV+LpLCLEOThu2+E9zpxqBQ+jppDgm5SQWoYi M8NzkYRJvRK3ZHuKq8PqWCD58C3EqYYIn82ckyRdFb8fGzcRa6dYTISbzQtLWcsQ3AowSQ +XBoILY3Q8Eed16Nf/Dh2L3dmp67480G6o/cxM2wfayqYOo6Ztkioz5leL45eQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sG/Z1v2dmYrqXzMKn+/H+cbtZ9fNSjBKsYPr23/YsBg=; b=iWnOxDPEOo4TyY5uzi+uCZjLqdGPq39ih1hgbEFmKM0vFL/QPHi3T6M9FSngJePN5e0sh/ xjzhPOiGOosN7RCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 07/30] x86/microcode: Move core specific defines to local header References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:36 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773868477558757281 X-GMAIL-MSGID: 1773868477558757281 From: Thomas Gleixner There is no reason to expose all of this globally. Move everything which is not required outside of the microcode specific code to local header files. No functional change. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 157 +++++++----------------- arch/x86/include/asm/microcode_amd.h | 54 -------- arch/x86/include/asm/microcode_intel.h | 89 -------------- arch/x86/kernel/cpu/microcode/amd.c | 2 arch/x86/kernel/cpu/microcode/core.c | 3 arch/x86/kernel/cpu/microcode/intel.c | 3 arch/x86/kernel/cpu/microcode/internal.h | 196 +++++++++++++++++++++++++++++++ 7 files changed, 251 insertions(+), 253 deletions(-) --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -2,138 +2,79 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H -#include -#include - -#include -#include -#include - -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct cpu_signature { unsigned int sig; unsigned int pf; unsigned int rev; }; -struct device; - -enum ucode_state { - UCODE_OK = 0, - UCODE_NEW, - UCODE_UPDATED, - UCODE_NFOUND, - UCODE_ERROR, -}; - -struct microcode_ops { - enum ucode_state (*request_microcode_fw) (int cpu, struct device *); - - void (*microcode_fini_cpu) (int cpu); - - /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. - * See also the "Synchronization" section in microcode_core.c. - */ - enum ucode_state (*apply_microcode) (int cpu); - int (*collect_cpu_info) (int cpu, struct cpu_signature *csig); -}; - struct ucode_cpu_info { struct cpu_signature cpu_sig; void *mc; }; -extern struct ucode_cpu_info ucode_cpu_info[]; -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); - -#ifdef CONFIG_CPU_SUP_INTEL -extern struct microcode_ops * __init init_intel_microcode(void); -#else -static inline struct microcode_ops * __init init_intel_microcode(void) -{ - return NULL; -} -#endif /* CONFIG_CPU_SUP_INTEL */ -#ifdef CONFIG_CPU_SUP_AMD -extern struct microcode_ops * __init init_amd_microcode(void); -extern void __exit exit_amd_microcode(void); +#ifdef CONFIG_MICROCODE +void load_ucode_bsp(void); +void load_ucode_ap(void); +void microcode_bsp_resume(void); #else -static inline struct microcode_ops * __init init_amd_microcode(void) -{ - return NULL; -} -static inline void __exit exit_amd_microcode(void) {} +static inline void load_ucode_bsp(void) { } +static inline void load_ucode_ap(void) { } +static inline void microcode_bsp_resume(void) { } #endif -#define MAX_UCODE_COUNT 128 - -#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) -#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') -#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') -#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') -#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') -#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') -#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') - -#define CPUID_IS(a, b, c, ebx, ecx, edx) \ - (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c)))) - -/* - * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. - * x86_cpuid_vendor() gets vendor id for BSP. - * - * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify - * coding, we still use x86_cpuid_vendor() to get vendor id for AP. - * - * x86_cpuid_vendor() gets vendor information directly from CPUID. - */ -static inline int x86_cpuid_vendor(void) -{ - u32 eax = 0x00000000; - u32 ebx, ecx = 0, edx; +#ifdef CONFIG_CPU_SUP_INTEL +/* Intel specific microcode defines. Public for IFS */ +struct microcode_header_intel { + unsigned int hdrver; + unsigned int rev; + unsigned int date; + unsigned int sig; + unsigned int cksum; + unsigned int ldrver; + unsigned int pf; + unsigned int datasize; + unsigned int totalsize; + unsigned int metasize; + unsigned int reserved[2]; +}; - native_cpuid(&eax, &ebx, &ecx, &edx); +struct microcode_intel { + struct microcode_header_intel hdr; + unsigned int bits[]; +}; - if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) - return X86_VENDOR_INTEL; +#define DEFAULT_UCODE_DATASIZE (2000) +#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) +#define MC_HEADER_TYPE_MICROCODE 1 +#define MC_HEADER_TYPE_IFS 2 - if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) - return X86_VENDOR_AMD; +static inline int intel_microcode_get_datasize(void *data) +{ + struct microcode_intel *mc = data; - return X86_VENDOR_UNKNOWN; + return mc->hdr.datasize ? : DEFAULT_UCODE_DATASIZE; } -static inline unsigned int x86_cpuid_family(void) +static inline u32 intel_get_microcode_revision(void) { - u32 eax = 0x00000001; - u32 ebx, ecx = 0, edx; + u32 rev, dummy; + + native_wrmsrl(MSR_IA32_UCODE_REV, 0); - native_cpuid(&eax, &ebx, &ecx, &edx); + /* As documented in the SDM: Do a CPUID 1 here */ + native_cpuid_eax(1); - return x86_family(eax); + /* get the current revision from MSR 0x8B */ + native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); + + return rev; } -#ifdef CONFIG_MICROCODE -extern void __init load_ucode_bsp(void); -extern void load_ucode_ap(void); -extern bool initrd_gone; -void microcode_bsp_resume(void); -#else -static inline void __init load_ucode_bsp(void) { } -static inline void load_ucode_ap(void) { } -static inline void microcode_bsp_resume(void) { } -#endif +void show_ucode_info_early(void); + +#else /* CONFIG_CPU_SUP_INTEL */ +static inline void show_ucode_info_early(void) { } +#endif /* !CONFIG_CPU_SUP_INTEL */ #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/include/asm/microcode_amd.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_MICROCODE_AMD_H -#define _ASM_X86_MICROCODE_AMD_H - -#define UCODE_MAGIC 0x00414d44 -#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 -#define UCODE_UCODE_TYPE 0x00000001 - -#define SECTION_HDR_SIZE 8 -#define CONTAINER_HDR_SZ 12 - -struct equiv_cpu_entry { - u32 installed_cpu; - u32 fixed_errata_mask; - u32 fixed_errata_compare; - u16 equiv_cpu; - u16 res; -} __attribute__((packed)); - -struct microcode_header_amd { - u32 data_code; - u32 patch_id; - u16 mc_patch_data_id; - u8 mc_patch_data_len; - u8 init_flag; - u32 mc_patch_data_checksum; - u32 nb_dev_id; - u32 sb_dev_id; - u16 processor_rev_id; - u8 nb_rev_id; - u8 sb_rev_id; - u8 bios_api_rev; - u8 reserved1[3]; - u32 match_reg[8]; -} __attribute__((packed)); - -struct microcode_amd { - struct microcode_header_amd hdr; - unsigned int mpb[]; -}; - -#define PATCH_MAX_SIZE (3 * PAGE_SIZE) - -#ifdef CONFIG_CPU_SUP_AMD -extern void load_ucode_amd_early(unsigned int cpuid_1_eax); -extern int __init save_microcode_in_initrd_amd(unsigned int family); -void reload_ucode_amd(unsigned int cpu); -#else -static inline void load_ucode_amd_early(unsigned int cpuid_1_eax) {} -static inline int __init -save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } -static inline void reload_ucode_amd(unsigned int cpu) {} -#endif -#endif /* _ASM_X86_MICROCODE_AMD_H */ --- a/arch/x86/include/asm/microcode_intel.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_MICROCODE_INTEL_H -#define _ASM_X86_MICROCODE_INTEL_H - -struct microcode_header_intel { - unsigned int hdrver; - unsigned int rev; - unsigned int date; - unsigned int sig; - unsigned int cksum; - unsigned int ldrver; - unsigned int pf; - unsigned int datasize; - unsigned int totalsize; - unsigned int metasize; - unsigned int reserved[2]; -}; - -struct microcode_intel { - struct microcode_header_intel hdr; - unsigned int bits[]; -}; - -/* microcode format is extended from prescott processors */ -struct extended_signature { - unsigned int sig; - unsigned int pf; - unsigned int cksum; -}; - -struct extended_sigtable { - unsigned int count; - unsigned int cksum; - unsigned int reserved[3]; - struct extended_signature sigs[]; -}; - -#define DEFAULT_UCODE_DATASIZE (2000) -#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) -#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) -#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) -#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) -#define MC_HEADER_TYPE_MICROCODE 1 -#define MC_HEADER_TYPE_IFS 2 - -#define get_totalsize(mc) \ - (((struct microcode_intel *)mc)->hdr.datasize ? \ - ((struct microcode_intel *)mc)->hdr.totalsize : \ - DEFAULT_UCODE_TOTALSIZE) - -static inline int intel_microcode_get_datasize(void *data) -{ - struct microcode_intel *mc = data; - - return mc->hdr.datasize ? : DEFAULT_UCODE_DATASIZE; -} - -#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) - -static inline u32 intel_get_microcode_revision(void) -{ - u32 rev, dummy; - - native_wrmsrl(MSR_IA32_UCODE_REV, 0); - - /* As documented in the SDM: Do a CPUID 1 here */ - native_cpuid_eax(1); - - /* get the current revision from MSR 0x8B */ - native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); - - return rev; -} - -#ifdef CONFIG_CPU_SUP_INTEL -extern void __init load_ucode_intel_bsp(void); -extern void load_ucode_intel_ap(void); -extern void show_ucode_info_early(void); -extern int __init save_microcode_in_initrd_intel(void); -void reload_ucode_intel(void); -#else -static inline __init void load_ucode_intel_bsp(void) {} -static inline void load_ucode_intel_ap(void) {} -static inline void show_ucode_info_early(void) {} -static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; } -static inline void reload_ucode_intel(void) {} -#endif - -#endif /* _ASM_X86_MICROCODE_INTEL_H */ --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -35,6 +35,8 @@ #include #include +#include "internal.h" + static struct equiv_cpu_table { unsigned int num_entries; struct equiv_cpu_entry *entry; --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -33,11 +33,12 @@ #include #include -#include #include #include #include +#include "internal.h" + #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -32,11 +32,12 @@ #include #include -#include #include #include #include +#include "internal.h" + static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ --- /dev/null +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _X86_MICROCODE_INTERNAL_H +#define _X86_MICROCODE_INTERNAL_H + +#include +#include + +#include +#include + +struct ucode_patch { + struct list_head plist; + void *data; /* Intel uses only this one */ + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +extern struct list_head microcode_cache; + +struct device; + +enum ucode_state { + UCODE_OK = 0, + UCODE_NEW, + UCODE_UPDATED, + UCODE_NFOUND, + UCODE_ERROR, +}; + +struct microcode_ops { + enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); + + void (*microcode_fini_cpu)(int cpu); + + /* + * The generic 'microcode_core' part guarantees that + * the callbacks below run on a target cpu when they + * are being called. + * See also the "Synchronization" section in microcode_core.c. + */ + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); +}; + +extern struct ucode_cpu_info ucode_cpu_info[]; +struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); + +#define MAX_UCODE_COUNT 128 + +#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) +#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') +#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') +#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') +#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') +#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') +#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') + +#define CPUID_IS(a, b, c, ebx, ecx, edx) \ + (!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c)))) + +/* + * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. + * x86_cpuid_vendor() gets vendor id for BSP. + * + * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify + * coding, we still use x86_cpuid_vendor() to get vendor id for AP. + * + * x86_cpuid_vendor() gets vendor information directly from CPUID. + */ +static inline int x86_cpuid_vendor(void) +{ + u32 eax = 0x00000000; + u32 ebx, ecx = 0, edx; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) + return X86_VENDOR_INTEL; + + if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) + return X86_VENDOR_AMD; + + return X86_VENDOR_UNKNOWN; +} + +static inline unsigned int x86_cpuid_family(void) +{ + u32 eax = 0x00000001; + u32 ebx, ecx = 0, edx; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + return x86_family(eax); +} + +extern bool initrd_gone; + +#ifdef CONFIG_CPU_SUP_AMD +#define UCODE_MAGIC 0x00414d44 +#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 +#define UCODE_UCODE_TYPE 0x00000001 + +#define SECTION_HDR_SIZE 8 +#define CONTAINER_HDR_SZ 12 + +struct equiv_cpu_entry { + u32 installed_cpu; + u32 fixed_errata_mask; + u32 fixed_errata_compare; + u16 equiv_cpu; + u16 res; +} __packed; + +struct microcode_header_amd { + u32 data_code; + u32 patch_id; + u16 mc_patch_data_id; + u8 mc_patch_data_len; + u8 init_flag; + u32 mc_patch_data_checksum; + u32 nb_dev_id; + u32 sb_dev_id; + u16 processor_rev_id; + u8 nb_rev_id; + u8 sb_rev_id; + u8 bios_api_rev; + u8 reserved1[3]; + u32 match_reg[8]; +} __packed; + +struct microcode_amd { + struct microcode_header_amd hdr; + unsigned int mpb[]; +}; + +#define PATCH_MAX_SIZE (3 * PAGE_SIZE) + +void load_ucode_amd_bsp(unsigned int family); +void load_ucode_amd_ap(unsigned int family); +void load_ucode_amd_early(unsigned int cpuid_1_eax); +int save_microcode_in_initrd_amd(unsigned int family); +void reload_ucode_amd(unsigned int cpu); +struct microcode_ops *init_amd_microcode(void); +void exit_amd_microcode(void); +#else /* CONFIG_MICROCODE_AMD */ +static inline void load_ucode_amd_bsp(unsigned int family) { } +static inline void load_ucode_amd_ap(unsigned int family) { } +static inline void load_ucode_amd_early(unsigned int family) { } +static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } +static inline void reload_ucode_amd(unsigned int cpu) { } +static inline struct microcode_ops *init_amd_microcode(void) { return NULL; } +static inline void exit_amd_microcode(void) { } +#endif /* !CONFIG_MICROCODE_AMD */ + +#ifdef CONFIG_CPU_SUP_INTEL +struct extended_signature { + unsigned int sig; + unsigned int pf; + unsigned int cksum; +}; + +struct extended_sigtable { + unsigned int count; + unsigned int cksum; + unsigned int reserved[3]; + struct extended_signature sigs[]; +}; + +#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) +#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) +#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) + +#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) + +static inline int get_totalsize(void *mc) +{ + struct microcode_intel *intel_mc = (struct microcode_intel *)mc; + + return intel_mc->hdr.datasize ? intel_mc->hdr.totalsize : DEFAULT_UCODE_TOTALSIZE; +} + +void load_ucode_intel_bsp(void); +void load_ucode_intel_ap(void); +int save_microcode_in_initrd_intel(void); +void reload_ucode_intel(void); +struct microcode_ops *init_intel_microcode(void); +#else /* CONFIG_CPU_SUP_INTEL */ +static inline void load_ucode_intel_bsp(void) { } +static inline void load_ucode_intel_ap(void) { } +static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } +static inline void reload_ucode_intel(void) { } +static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } +#endif /* !CONFIG_CPU_SUP_INTEL */ + +#endif /* _X86_MICROCODE_INTERNAL_H */ From patchwork Thu Aug 10 18:37:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp667148vqi; Thu, 10 Aug 2023 13:24:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3Cr8pJAyBkfpETt/qsTxLg/976hz14bsFGi0jYGumSEwtRyZo6EhnvZ08o1n6vUH/Hr91 X-Received: by 2002:a17:902:b48b:b0:1bc:3944:9391 with SMTP id y11-20020a170902b48b00b001bc39449391mr2840731plr.25.1691699091597; Thu, 10 Aug 2023 13:24:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691699091; cv=none; d=google.com; s=arc-20160816; b=rgsBvVWoStO9LHpoAecdGo/JeYB0n3jG0tFiJqFb48ZPqOW66Bd1tmbNbniQ0C2AP7 YKMcYeoVfT5MSPDEcRt8ZBvGHqjbhMpsl67JQHoWzYgKmdk53p5PwSMLQD4GNnuQFGUK OgxGuqo5aVmvTjuMYd1mJdqFjCgxxVq9XCkWOX3dRJoU2fvYldAtjxUrZT4PH1Xa8xng 7KXG6DmdhL/Z4RylXAXYOkpSyQ/9vue/g6Yrdd+aem/wutScz6wOEWQJwo8xpQEMrwGt xzUzWuIsc9cHfVt4TTakzPQloyh+VhGkwFhQ7SZcKgxSbWzegu13a/9FPn9v2LyomApc 39xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=EOXgyVN41yCAFGpUe+VjUMzw2fD0p6oTWYpHxVlpzMk=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=h04jCNMHN1SN/sQQ9nSRJifW0Jk89J263gKfgOnvdQdwnh6rhkqUfd1ElyC+zxFC2+ 0zDVUpSW88rPxMjGWoj6p1SdxQIYv30exptzMu0wZiT+ubPbApz3FrjdOGciLgM8r/ny uZSiJqMa8Mwm93jdQjFBC+brpPyLq0l/7no757uXDTZW5l7ODGDXDAxZB8QsJ136f5tG CarN7mJnrp+7pt/GCpGFSIVF7clgVGQRuAfQsRJrUBb8pfIadlMQO41IpYMp2ClBmOKd jMNzSS8k00Yg8hZFMACrVlIBFZMbsbHmj8ZNlFURQJMjS03WF8dObRaJrMlv4bFoxuD/ L0IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=s2QVDAOx; dkim=neutral (no key) header.i=@linutronix.de header.b=jUWZ9jza; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d11-20020a170902654b00b001bb8a57d518si1916129pln.379.2023.08.10.13.24.37; Thu, 10 Aug 2023 13:24:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=s2QVDAOx; dkim=neutral (no key) header.i=@linutronix.de header.b=jUWZ9jza; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235651AbjHJShw (ORCPT + 99 others); Thu, 10 Aug 2023 14:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235078AbjHJShr (ORCPT ); Thu, 10 Aug 2023 14:37:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCCCD2D4B for ; Thu, 10 Aug 2023 11:37:39 -0700 (PDT) Message-ID: <20230810160805.418991257@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692658; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EOXgyVN41yCAFGpUe+VjUMzw2fD0p6oTWYpHxVlpzMk=; b=s2QVDAOxyNGpPQA/aQHUrL225eLnHImX/yChvcPWr7pW1+ntdKyEIjG4CXVopvRkwXJsV9 vAPVqA9+v2Ld0OaNv8Ue+Scsg2bYAB70ch9GYVVpNig5j0BCatH7gmwtuvrTtOTneGEKAt 1ncyur9NwBi/LK4F4zanx7MMsQ+X622zIGsj5sxzjYCMNcDJt0+1Z5Pt2I75bXVxYvO6P7 hvudfxEpDxTWiMDcvFMIxI1a+Vf5N5n+qaANE/qGPdQ6oW98+qTwk13Hi9Yt+LQNN0NJoQ EHyQttDEBYkpZSlE/tRrJkL4JfDtt7gVlAqV7jB43EsduUgyokctT5BVbrEZng== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692658; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EOXgyVN41yCAFGpUe+VjUMzw2fD0p6oTWYpHxVlpzMk=; b=jUWZ9jzaPOsz2ytlhSj9hda/n/f4KWgdDDtp4pwnz8fN3YhOpdc5y63OC25MIkAx9UTNoU GvRThji8HOTd3sCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 08/30] x86/microcode/intel: Rip out mixed stepping support for Intel CPUs References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:38 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773875066918730389 X-GMAIL-MSGID: 1773875066918730389 From: Ashok Raj Mixed steppings aren't supported on Intel CPUs. Only one patch is required for the entire system. The caching of micro code blobs which match the family and model is therefore pointless and in fact it is disfunctional as CPU hotplug updates use only a single microcode blob, i.e. the one where *intel_ucode_patch points to. Remove the microcode cache and make it an AMD local feature. [ tglx: Save only at the end. Otherwise random microcode ends up in the pointer for early loading ] Originally-From: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/amd.c | 10 + arch/x86/kernel/cpu/microcode/core.c | 2 arch/x86/kernel/cpu/microcode/intel.c | 201 ++++++++----------------------- arch/x86/kernel/cpu/microcode/internal.h | 10 - 4 files changed, 64 insertions(+), 159 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -37,6 +37,16 @@ #include "internal.h" +struct ucode_patch { + struct list_head plist; + void *data; + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +static LIST_HEAD(microcode_cache); + static struct equiv_cpu_table { unsigned int num_entries; struct equiv_cpu_entry *entry; --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,8 +46,6 @@ static bool dis_ucode_ldr = true; bool initrd_gone; -LIST_HEAD(microcode_cache); - /* * Synchronization. * --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -41,10 +41,10 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch; +static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core; +static int llc_size_per_core __ro_after_init; int intel_cpu_collect_info(struct ucode_cpu_info *uci) { @@ -233,81 +233,26 @@ static int has_newer_microcode(void *mc, return intel_find_matching_signature(mc, csig, cpf); } -static struct ucode_patch *memdup_patch(void *data, unsigned int size) +static void save_microcode_patch(void *data, unsigned int size) { - struct ucode_patch *p; + struct microcode_header_intel *p; - p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL); - if (!p) - return NULL; - - p->data = kmemdup(data, size, GFP_KERNEL); - if (!p->data) { - kfree(p); - return NULL; - } - - return p; -} - -static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigned int size) -{ - struct microcode_header_intel *mc_hdr, *mc_saved_hdr; - struct ucode_patch *iter, *tmp, *p = NULL; - bool prev_found = false; - unsigned int sig, pf; - - mc_hdr = (struct microcode_header_intel *)data; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - mc_saved_hdr = (struct microcode_header_intel *)iter->data; - sig = mc_saved_hdr->sig; - pf = mc_saved_hdr->pf; - - if (intel_find_matching_signature(data, sig, pf)) { - prev_found = true; - - if (mc_hdr->rev <= mc_saved_hdr->rev) - continue; - - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer %p\n", data); - else { - list_replace(&iter->plist, &p->plist); - kfree(iter->data); - kfree(iter); - } - } - } - - /* - * There weren't any previous patches found in the list cache; save the - * newly found. - */ - if (!prev_found) { - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer for %p\n", data); - else - list_add_tail(&p->plist, µcode_cache); - } + kfree(intel_ucode_patch); + intel_ucode_patch = NULL; + p = kmemdup(data, size, GFP_KERNEL); if (!p) return; - if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) - return; - /* * Save for early loading. On 32-bit, that needs to be a physical * address as the APs are running from physical addresses, before * paging has been enabled. */ if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); + intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p); else - intel_ucode_patch = p->data; + intel_ucode_patch = (struct microcode_intel *)p; } /* @@ -319,6 +264,7 @@ scan_microcode(void *data, size_t size, { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; + u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; while (size) { @@ -328,8 +274,7 @@ scan_microcode(void *data, size_t size, mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); - if (!mc_size || - mc_size > size || + if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; @@ -341,31 +286,16 @@ scan_microcode(void *data, size_t size, continue; } - if (save) { - save_microcode_patch(uci, data, mc_size); + /* BSP scan: Check whether there is newer microcode */ + if (save && cur_rev >= mc_header->rev) goto next; - } - - if (!patch) { - if (!has_newer_microcode(data, - uci->cpu_sig.sig, - uci->cpu_sig.pf, - uci->cpu_sig.rev)) - goto next; - - } else { - struct microcode_header_intel *phdr = &patch->hdr; - - if (!has_newer_microcode(data, - phdr->sig, - phdr->pf, - phdr->rev)) - goto next; - } + /* Save scan: Check whether there is newer or matching microcode */ + if (save && cur_rev != mc_header->rev) + goto next; - /* We have a newer patch, save it. */ patch = data; + cur_rev = mc_header->rev; next: data += mc_size; @@ -374,18 +304,22 @@ scan_microcode(void *data, size_t size, if (size) return NULL; + if (save && patch) + save_microcode_patch(patch, mc_size); + return patch; } static void show_saved_mc(void) { #ifdef DEBUG - int i = 0, j; unsigned int sig, pf, rev, total_size, data_size, date; + struct extended_sigtable *ext_header; + struct extended_signature *ext_sig; struct ucode_cpu_info uci; - struct ucode_patch *p; + int j, ext_sigcount; - if (list_empty(µcode_cache)) { + if (!intel_ucode_patch) { pr_debug("no microcode data saved.\n"); return; } @@ -397,45 +331,34 @@ static void show_saved_mc(void) rev = uci.cpu_sig.rev; pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); - list_for_each_entry(p, µcode_cache, plist) { - struct microcode_header_intel *mc_saved_header; - struct extended_sigtable *ext_header; - struct extended_signature *ext_sig; - int ext_sigcount; - - mc_saved_header = (struct microcode_header_intel *)p->data; - - sig = mc_saved_header->sig; - pf = mc_saved_header->pf; - rev = mc_saved_header->rev; - date = mc_saved_header->date; - - total_size = get_totalsize(mc_saved_header); - data_size = intel_microcode_get_datasize(mc_saved_header); - - pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", - i++, sig, pf, rev, total_size, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); - - /* Look for ext. headers: */ - if (total_size <= data_size + MC_HEADER_SIZE) - continue; + sig = intel_ucode_patch->hdr.sig; + pf = intel_ucode_patch->hdr.pf; + rev = intel_ucode_patch->hdr.rev; + date = intel_ucode_patch->hdr.date; + + total_size = get_totalsize(mc_saved_header); + data_size = intel_microcode_get_datasize(mc_saved_header); + + pr_debug("mc_saved: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", + sig, pf, rev, total_size, date & 0xffff, + date >> 24, (date >> 16) & 0xff); - ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE; - ext_sigcount = ext_header->count; - ext_sig = (void *)ext_header + EXT_HEADER_SIZE; + /* Look for ext. headers: */ + if (total_size <= data_size + MC_HEADER_SIZE) + return; - for (j = 0; j < ext_sigcount; j++) { - sig = ext_sig->sig; - pf = ext_sig->pf; + ext_header = (void *)intel_ucode_patch + data_size + MC_HEADER_SIZE; + ext_sigcount = ext_header->count; + ext_sig = (void *)ext_header + EXT_HEADER_SIZE; + + for (j = 0; j < ext_sigcount; j++) { + sig = ext_sig->sig; + pf = ext_sig->pf; - pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", - j, sig, pf); + pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", + j, sig, pf); - ext_sig++; - } + ext_sig++; } #endif } @@ -451,7 +374,7 @@ static void save_mc_for_early(struct uco mutex_lock(&x86_cpu_microcode_mutex); - save_microcode_patch(uci, mc, size); + save_microcode_patch(mc, size); show_saved_mc(); mutex_unlock(&x86_cpu_microcode_mutex); @@ -675,26 +598,10 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci, true); } -static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) +/* Accessor for microcode pointer */ +static struct microcode_intel *ucode_get_patch(void) { - struct microcode_header_intel *phdr; - struct ucode_patch *iter, *tmp; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - - phdr = (struct microcode_header_intel *)iter->data; - - if (phdr->rev <= uci->cpu_sig.rev) - continue; - - if (!intel_find_matching_signature(phdr, - uci->cpu_sig.sig, - uci->cpu_sig.pf)) - continue; - - return iter->data; - } - return NULL; + return intel_ucode_patch; } void reload_ucode_intel(void) @@ -704,7 +611,7 @@ void reload_ucode_intel(void) intel_cpu_collect_info(&uci); - p = find_patch(&uci); + p = ucode_get_patch(); if (!p) return; @@ -748,7 +655,7 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; /* Look for a newer patch in our cache: */ - mc = find_patch(uci); + mc = ucode_get_patch(); if (!mc) { mc = uci->mc; if (!mc) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -8,16 +8,6 @@ #include #include -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct device; enum ucode_state { From patchwork Thu Aug 10 18:37:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134221 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp673202vqi; Thu, 10 Aug 2023 13:36:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEXdmkDuGojTEGDN07PTXsC6MFxEJyEip3V1umJzHcybaTKws8n0TFqtMvewqVfedebjUbW X-Received: by 2002:a17:903:186:b0:1bd:9498:f15d with SMTP id z6-20020a170903018600b001bd9498f15dmr4136549plg.24.1691699786904; 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Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 65 ---------------------------------- 1 file changed, 65 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -10,15 +10,7 @@ * Copyright (C) 2012 Fenghua Yu * H Peter Anvin" */ - -/* - * This needs to be before all headers so that pr_debug in printk.h doesn't turn - * printk calls into no_printk(). - * - *#define DEBUG - */ #define pr_fmt(fmt) "microcode: " fmt - #include #include #include @@ -310,59 +302,6 @@ scan_microcode(void *data, size_t size, return patch; } -static void show_saved_mc(void) -{ -#ifdef DEBUG - unsigned int sig, pf, rev, total_size, data_size, date; - struct extended_sigtable *ext_header; - struct extended_signature *ext_sig; - struct ucode_cpu_info uci; - int j, ext_sigcount; - - if (!intel_ucode_patch) { - pr_debug("no microcode data saved.\n"); - return; - } - - intel_cpu_collect_info(&uci); - - sig = uci.cpu_sig.sig; - pf = uci.cpu_sig.pf; - rev = uci.cpu_sig.rev; - pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); - - sig = intel_ucode_patch->hdr.sig; - pf = intel_ucode_patch->hdr.pf; - rev = intel_ucode_patch->hdr.rev; - date = intel_ucode_patch->hdr.date; - - total_size = get_totalsize(mc_saved_header); - data_size = intel_microcode_get_datasize(mc_saved_header); - - pr_debug("mc_saved: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", - sig, pf, rev, total_size, date & 0xffff, - date >> 24, (date >> 16) & 0xff); - - /* Look for ext. headers: */ - if (total_size <= data_size + MC_HEADER_SIZE) - return; - - ext_header = (void *)intel_ucode_patch + data_size + MC_HEADER_SIZE; - ext_sigcount = ext_header->count; - ext_sig = (void *)ext_header + EXT_HEADER_SIZE; - - for (j = 0; j < ext_sigcount; j++) { - sig = ext_sig->sig; - pf = ext_sig->pf; - - pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", - j, sig, pf); - - ext_sig++; - } -#endif -} - /* * Save this microcode patch. It will be loaded early when a CPU is * hot-added or resumes. @@ -375,7 +314,6 @@ static void save_mc_for_early(struct uco mutex_lock(&x86_cpu_microcode_mutex); save_microcode_patch(mc, size); - show_saved_mc(); mutex_unlock(&x86_cpu_microcode_mutex); } @@ -526,9 +464,6 @@ int __init save_microcode_in_initrd_inte intel_cpu_collect_info(&uci); scan_microcode(cp.data, cp.size, &uci, true); - - show_saved_mc(); - return 0; } From patchwork Thu Aug 10 18:37:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134158 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp625013vqi; Thu, 10 Aug 2023 12:06:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkE8qJDMp5iHMOVfJ4n3f/qgwiJecVKTR430rzSZpAxlno2ovD1S6QmU29QzIwDhvaxQWV X-Received: by 2002:a17:90a:7f02:b0:269:3498:3bad with SMTP id k2-20020a17090a7f0200b0026934983badmr2485321pjl.14.1691694363331; Thu, 10 Aug 2023 12:06:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691694363; cv=none; d=google.com; s=arc-20160816; b=Q3JiUsQRbLBHwprNlVsAeB8r+PaOtX0yB4tKiDjoRx0XH9HHoIDEe/+LgITunPeQhJ AqkmdfTocJmrmU6GZbzRC2bdFjWqkdJSXqVSxdOXwTzFw93oM5GjZs16xDpD30EXunwN AuDpx0NojdgIHd8uTUg7grGpdgbIpok4bBNSHH7uoS+lJV5qCX6zYUQFfn67hNJPk1VQ bsGvr3n0KslGBVwRyJX9COGPZenAg4ipdztLCmkFg6B8YlVg97Z8LDmSnpSALKGlIGXT w6c9pxaHodDbyaxps9pxPrNazdggiVN6Qayb3yi0Fol12CN9T1kKKAAk8Q7W4bELVcOW DObA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=22EAgAQ5hctFTD7Flcc/WpTEDSRyz3fGpB62K9c30Ls=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=f9CslD9PmPr1LmoslfZAzRRVNtoeUUZU1kU+So7OEVnL4dQJRS0ZXm565ynF3Gui7P YWQFRYB3EvC5Yp6ELhf0nU2gjObUVQ5k9ruR/KL9HeIP3ttIKCaSFO+qVq3/RTu1Ddsa IDPL7+q8BcD1MlnVjKQbzfk3ij51X1N4p3R6WSNTR5CyqK3KzgXpt6vnRiuquGzTH4St muXRIKc+PaFgvtwnxWeOvMuipzAfxNhO3ef/Ecng0+IZObyeld4a+WVvDowC5p1q/PgE jWeYRuqTnfnlsMqS4tiFb2yraMbNffZhwoOD5T3lMSdJ93/vU1SbAFU3jy8gBw7xqkJA pHVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZV9uKay5; dkim=neutral (no key) header.i=@linutronix.de header.b=p5TOZc1N; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -302,22 +302,6 @@ scan_microcode(void *data, size_t size, return patch; } -/* - * Save this microcode patch. It will be loaded early when a CPU is - * hot-added or resumes. - */ -static void save_mc_for_early(struct ucode_cpu_info *uci, u8 *mc, unsigned int size) -{ - /* Synchronization during CPU hotplug. */ - static DEFINE_MUTEX(x86_cpu_microcode_mutex); - - mutex_lock(&x86_cpu_microcode_mutex); - - save_microcode_patch(mc, size); - - mutex_unlock(&x86_cpu_microcode_mutex); -} - static bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; @@ -718,12 +702,8 @@ static enum ucode_state generic_load_mic vfree(uci->mc); uci->mc = (struct microcode_intel *)new_mc; - /* - * If early loading microcode is supported, save this mc into - * permanent memory. So it will be loaded early when a CPU is hot added - * or resumes. - */ - save_mc_for_early(uci, new_mc, new_mc_size); + /* Save for CPU hotplug */ + save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, new_rev, uci->cpu_sig.rev); From patchwork Thu Aug 10 18:37:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134145 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp611899vqi; Thu, 10 Aug 2023 11:40:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHFzSh9K4RlQAzXcNOBEyxLFtNWWubIfP+J9Eiq2roWoj0O3XJM2T08tKnpgWQk2uR3ZRQd X-Received: by 2002:a05:6808:6343:b0:39e:b985:b47e with SMTP id eb3-20020a056808634300b0039eb985b47emr3314739oib.36.1691692840375; Thu, 10 Aug 2023 11:40:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691692840; cv=none; d=google.com; s=arc-20160816; b=NuuRjWZhSa6cFclfROJqUyBzzFMLin1DNprSANsvr2d8OvB1XPkIC+viMhK7sdoZHe Db6dJ7TJhTs6eebplxs+3a4YsNxUnFFkx2NVbutP4xs0HUZ/XL//rOlFNomc7w2BzRUq YT0FQd4RsFwwo+ZyAqeyfYBkuPDD2wLNzxTy/osnl2RtWz4I4DoHT2zpAnl1q1ilaRtu YBHrUdIuraR8QZsBa+sgyZA8muWZQxAHenHipepJaDbWiVkuv7GnOORn57hnuKDF+FbB U1VZw9vf3PCByL3xefNZ4zicbrKy/g5MlOsv7oUmfhKi7l5NcktDv/f7xZ+fbG+aHqSk 0qqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=b/ELWliFBPnNte8vlpVCfRTqinp+om6shCPvsMqFYso=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=QuNAyT+7RN9rolvE/0wP++ZSEIHoqLrkL1j6bqvKJolbd5O1BBjBLentgzspdtQXZ2 NqCuuILYV+eAKGRZx1hEOxIJD6RTH19XfckxbntLmuCW23wgL9QFexVYp/icFnFEd3zp kA8Kd1JnO1gEEqPPmF3ZzAMpnIpMD8+zFmSyvv2HhW3Fx0y+noL1GrCgJFKsB3H94prk 1JGdjJAyssRKuYeQGSQ5GyE7+dB84Qe3Oo8uZAjha85iuObxt/J/EUTc6nQGGc+cQ1lK UalhsP39zpLyxlXzHX8gkZAy/QryF9oAwfUdsA/pjFyofsrRe8zi8TGqyWcv7uu5qJPh CIjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tIDqRKts; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kacb0RkV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -247,22 +247,16 @@ static void save_microcode_patch(void *d intel_ucode_patch = (struct microcode_intel *)p; } -/* - * Get microcode matching with BSP's model. Only CPUs with the same model as - * BSP can stay in the platform. - */ -static struct microcode_intel * -scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) +/* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ +static struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; - while (size) { - if (size < sizeof(struct microcode_header_intel)) - break; - + for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); @@ -270,27 +264,19 @@ scan_microcode(void *data, size_t size, intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - size -= mc_size; - - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, - uci->cpu_sig.pf)) { - data += mc_size; + if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - } /* BSP scan: Check whether there is newer microcode */ if (save && cur_rev >= mc_header->rev) - goto next; + continue; /* Save scan: Check whether there is newer or matching microcode */ if (save && cur_rev != mc_header->rev) - goto next; + continue; patch = data; cur_rev = mc_header->rev; - -next: - data += mc_size; } if (size) From patchwork Thu Aug 10 18:37:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134198 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp647776vqi; Thu, 10 Aug 2023 12:50:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJ3+e1bYi53tnRiKZflnt2YWLu9swF8JTyWPmQhE3+d4NkuLjNwSP7nGo1iAWSfrLAIsXh X-Received: by 2002:a2e:9b45:0:b0:2b6:a22b:42dc with SMTP id o5-20020a2e9b45000000b002b6a22b42dcmr2888ljj.16.1691697044420; Thu, 10 Aug 2023 12:50:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691697044; cv=none; d=google.com; s=arc-20160816; b=NxA+5YH75/P/7d6Y1Q9Zt89W+BJHnzhgfsH49dpFwYhDmnCnm1SCGjQ/IGHfaah5o9 GQ+D4XQ5deWFaauENJ9FN7neE1migCsucQ49Xgr0jt+KtKNfNGqpigQrqNirJW79Rmsc okXyqutNnVE7i/5lSst0wAJU3bYvkpDbhdpPUmN1QynvMErkFaRqorErCltRj45BU7ZL RfT131JKiNtFq0m0+QufVqoDRskWR3lw54QDTr251Sin6ZOJ+H0asmfD81j7tpDrTUhY LvZpMDpFFaXlF7owYGriP2+vzobsEGCFaq4V7BJYZVaBA0/0v6bkBVmJjsKOZI9+zbb7 slDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=uWV1AnK66aJ45IpQqDrjl0snIk0PFjfM1jJpRITU7kE=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=jaQ9MFBA3dHf2EjR42oW/3qjQTWfvey4DiTL+sdJXS7OSVRAGXhP7FLyWQ9QaN6yCX O6LZEC3zs9j4wb6za+joNN54m58HaGyH5YA4ICMbQq4BCGfS7vapt7TSQj9TMgXhdAPT LFcde6UEpZDmGHBa7+lZsqWcP2AtFG/QNrVbCgP0UseYURulyvttOnBAsdYPAUEziADP Lj+rRBi3nVGaK/KfZ9ufoopkzAr0yZXzp+jK1qVAKr6r2ieJYcn6jAcnEU6FQfkDJ4vP g9gdcZqT2ktq6Vq5J4yC+IZRBG7o2LgOSNHQKuSVU6mwQR1tOIBL2s3OH3lzxt1AyIO+ wBzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=VjB4d83+; dkim=neutral (no key) header.i=@linutronix.de header.b=ehzq3ip8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 47 ++++++++++++---------------------- 1 file changed, 17 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -212,19 +212,6 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) -{ - struct microcode_header_intel *mc_hdr = mc; - - if (mc_hdr->rev <= new_rev) - return 0; - - return intel_find_matching_signature(mc, csig, cpf); -} - static void save_microcode_patch(void *data, unsigned int size) { struct microcode_header_intel *p; @@ -617,14 +604,12 @@ static enum ucode_state apply_microcode_ return ret; } -static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) +static enum ucode_state read_ucode_intel(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; - enum ucode_state ret = UCODE_OK; - int new_rev = uci->cpu_sig.rev; + int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - unsigned int csig, cpf; while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; @@ -641,6 +626,7 @@ static enum ucode_state generic_load_mic pr_err("error! Bad data in microcode data file (totalsize too small)\n"); break; } + data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); @@ -663,16 +649,17 @@ static enum ucode_state generic_load_mic break; } - csig = uci->cpu_sig.sig; - cpf = uci->cpu_sig.pf; - if (has_newer_microcode(mc, csig, cpf, new_rev)) { - vfree(new_mc); - new_rev = mc_header.rev; - new_mc = mc; - new_mc_size = mc_size; - mc = NULL; /* trigger new vmalloc */ - ret = UCODE_NEW; - } + if (cur_rev >= mc_header.rev) + continue; + + if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + continue; + + vfree(new_mc); + cur_rev = mc_header.rev; + new_mc = mc; + new_mc_size = mc_size; + mc = NULL; } vfree(mc); @@ -692,9 +679,9 @@ static enum ucode_state generic_load_mic save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); + cpu, cur_rev, uci->cpu_sig.rev); - return ret; + return UCODE_NEW; } static bool is_blacklisted(unsigned int cpu) @@ -743,7 +730,7 @@ static enum ucode_state request_microcod kvec.iov_base = (void *)firmware->data; kvec.iov_len = firmware->size; iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size); - ret = generic_load_microcode(cpu, &iter); + ret = read_ucode_intel(cpu, &iter); release_firmware(firmware); From patchwork Thu Aug 10 18:37:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp646671vqi; Thu, 10 Aug 2023 12:48:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGwpdX5tXTO2wQDd9cZQ1rY9Fe5cTP1f6X7NO3niJfGtUdWZiRGh0nIT4K4Pr7MYyiDy0fp X-Received: by 2002:aa7:cf16:0:b0:523:27c:3564 with SMTP id a22-20020aa7cf16000000b00523027c3564mr2974161edy.18.1691696901416; Thu, 10 Aug 2023 12:48:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691696901; cv=none; d=google.com; s=arc-20160816; b=yuSgGe5VB+Wv8+DG/C+6ceYtw0Olv2bM9uTEuA20iN7v1GDSoIKdPBOvv4iwzF699D 55F9SdmSWdke76EvEeROs/fdH0HaJkhCIrcYrCY5FAfMKmzeld2sabo5FFzswpodsOf+ MTQkb5vm7IRJWtAlkSeDClwrr3SNeM0z4s7LnOSeh3ofK/u6VasWtbrcKxXLAE0QYWKp ou4DXmSgA4jY4V+Ywq1R42w2q2TjWJnhK8Yc2nyfoQg8yhSDIFxy/GaHC0JzwEfV1ezR eZVbC7qMa0bqImlCd0MJC4CHMCrLrtOgODV1LJ/M/JPJsAFFTkFw6mk5W/j4H6mA/l2v zmjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/uSyU9DUMvRJ3IasEYHJrt1TCtvswyOQyFstq2a1UwI=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=OUnIUk9tXQxleTR/viUAtT7pav0Yeu3X96pgXXuUNytbEjGjZB5783uK6v22t+A8dV RLiRSyEXIaqtJM8X/vhsqv1ghG7DEEJybNPUXK+4Tz9JceFiUVMJWKXEFw17Xj14Wpz3 sNbCtZ1qpV7sb7iDhooLCIhQ0u/C8JSpoEhOBihii6oJ/5+MZKJxXhM12P/fDepMJXlg yMBybCAtrtxX742CurqUDAITD6FBS6JYbCuQ0jlut9od+62RnpSkRsFPwihcQWkMY93x 225/hm9g6v8sc8+V7e3kZZwgmBdZm5bT8EmpZu5Phi/pr+j+Ui/6pTmkiGgR1gdWwBVI VwOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FoxF7GUZ; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="S/ysyttf"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Rename generic_load_microcode() as that Intel specific function is not generic at all. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 82 +++++++++++++--------------------- 1 file changed, 33 insertions(+), 49 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -36,7 +36,7 @@ static const char ucode_path[] = "kernel static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core __ro_after_init; +static unsigned int llc_size_per_core __ro_after_init; int intel_cpu_collect_info(struct ucode_cpu_info *uci) { @@ -275,37 +275,10 @@ static struct microcode_intel *scan_micr return patch; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) -{ - unsigned int eax = 1, ebx, ecx = 0, edx; - struct firmware fw; - char name[30]; - - if (IS_ENABLED(CONFIG_X86_32)) - return false; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - sprintf(name, "intel-ucode/%02x-%02x-%02x", - x86_family(eax), x86_model(eax), x86_stepping(eax)); - - if (firmware_request_builtin(&fw, name)) { - cp->size = fw.size; - cp->data = (void *)fw.data; - return true; - } - - return false; -} - static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, - new_rev, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } #ifdef CONFIG_X86_32 @@ -399,6 +372,28 @@ static int apply_microcode_early(struct return 0; } +static bool load_builtin_intel_microcode(struct cpio_data *cp) +{ + unsigned int eax = 1, ebx, ecx = 0, edx; + struct firmware fw; + char name[30]; + + if (IS_ENABLED(CONFIG_X86_32)) + return false; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + sprintf(name, "intel-ucode/%02x-%02x-%02x", + x86_family(eax), x86_model(eax), x86_stepping(eax)); + + if (firmware_request_builtin(&fw, name)) { + cp->size = fw.size; + cp->data = (void *)fw.data; + return true; + } + return false; +} + int __init save_microcode_in_initrd_intel(void) { struct ucode_cpu_info uci; @@ -490,25 +485,16 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci, true); } -/* Accessor for microcode pointer */ -static struct microcode_intel *ucode_get_patch(void) -{ - return intel_ucode_patch; -} - void reload_ucode_intel(void) { - struct microcode_intel *p; struct ucode_cpu_info uci; intel_cpu_collect_info(&uci); - p = ucode_get_patch(); - if (!p) + uci.mc = intel_ucode_patch; + if (!uci.mc) return; - uci.mc = p; - apply_microcode_early(&uci, false); } @@ -546,8 +532,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - /* Look for a newer patch in our cache: */ - mc = ucode_get_patch(); + mc = intel_ucode_patch; if (!mc) { mc = uci->mc; if (!mc) @@ -738,18 +723,17 @@ static enum ucode_state request_microcod } static struct microcode_ops microcode_intel_ops = { - .request_microcode_fw = request_microcode_fw, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .request_microcode_fw = request_microcode_fw, + .collect_cpu_info = collect_cpu_info, + .apply_microcode = apply_microcode_intel, }; -static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) +static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) { u64 llc_size = c->x86_cache_size * 1024ULL; do_div(llc_size, c->x86_max_cores); - - return (int)llc_size; + llc_size_per_core = (unsigned int)llc_size; } struct microcode_ops * __init init_intel_microcode(void) @@ -762,7 +746,7 @@ struct microcode_ops * __init init_intel return NULL; } - llc_size_per_core = calc_llc_size_per_core(c); + calc_llc_size_per_core(c); return µcode_intel_ops; } From patchwork Thu Aug 10 18:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134146 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp611980vqi; Thu, 10 Aug 2023 11:40:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHRq3Z5MW8KfcEnX3yS0TciEcoidTMECwdwaBvzfTtAqMk8K+iSuhW7hPGTTPk9Jh8ErZUD X-Received: by 2002:a17:902:ab45:b0:1b9:cb8b:3bd3 with SMTP id ij5-20020a170902ab4500b001b9cb8b3bd3mr2873349plb.31.1691692849868; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id li14-20020a170903294e00b001b80500f5b8si1795543plb.323.2023.08.10.11.40.35; Thu, 10 Aug 2023 11:40:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tyegCHnL; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235921AbjHJSi1 (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235922AbjHJSiH (ORCPT ); Thu, 10 Aug 2023 14:38:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49BED2D4A for ; Thu, 10 Aug 2023 11:37:49 -0700 (PDT) Message-ID: <20230810160805.765194207@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692667; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZFRMFzgOpNSYcs1HlmeI6jZPToCyvM4ul9GaIvD1IMg=; b=tyegCHnLUXL2vy/2z0pH1U4qIOyt8zo7A5NfwCS9sPoT93eggmezItUAefyKiZZ4ghdnCH n/o21RNBETU0XaUUUHVnuwRTg5Th6ppiANOhNaPieuAXhIh1EUbd4jY/8dwQutqL1Srlru E0I5Ev0Nq9lCWiEnweym2ZMz0USOdZpnrhhHOF95IjnFvw9bwQbuTxB7gvvs0vf5cRrkWs AvRMgqt+OHSE4pfKJlfZIENSmmJswutEyNFVYtkXyE8J+PT7rR1DhsT2DziI0qCCyOHXQJ vozWZ7MFGm8TghIpbhokBd/FyCcHOkcmGUx5GQnBASjeV/iTD6aqJlvE2t2Rwg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692667; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZFRMFzgOpNSYcs1HlmeI6jZPToCyvM4ul9GaIvD1IMg=; b=KthiAOxj/iA4QIR9upDFQ0mQJtjA0lh8zEL8I7tQadrc+hSNt8OS+6DYh78KMD3qkDroA8 cPysuIJT4U0xbxAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 14/30] x86/microcode/intel: Simplify early loading References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:46 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773868521956475664 X-GMAIL-MSGID: 1773868521956475664 From: Thomas Gleixner The early loading code is overly complicated: - It scans the builtin/initrd for microcode not only on the BSP, but also on all APs during early boot and then later in the boot process it scans again to duplicate and save the microcode before initrd goes away. That's a pointless exercise because this can be simply done before bringing up the APs when the memory allocator is up and running. - Saving the microcode from within the scan loop is completely non-obvious and a left over of the microcode cache. This can be done at the call site now which makes it obvious. Rework the code so that only the BSP scans the builtin/initrd microcode once during early boot and save it away in an early initcall for later use. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 arch/x86/kernel/cpu/microcode/intel.c | 191 +++++++++++++------------------ arch/x86/kernel/cpu/microcode/internal.h | 2 3 files changed, 86 insertions(+), 111 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -207,10 +207,6 @@ static int __init save_microcode_in_init int ret = -EINVAL; switch (c->x86_vendor) { - case X86_VENDOR_INTEL: - if (c->x86 >= 6) - ret = save_microcode_in_initrd_intel(); - break; case X86_VENDOR_AMD: if (c->x86 >= 0x10) ret = save_microcode_in_initrd_amd(cpuid_eax(1)); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,7 +33,7 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch __read_mostly; +static struct microcode_intel *ucode_patch_va __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -212,31 +212,34 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -static void save_microcode_patch(void *data, unsigned int size) +static void update_ucode_pointer(struct microcode_intel *mc) { - struct microcode_header_intel *p; - - kfree(intel_ucode_patch); - intel_ucode_patch = NULL; - - p = kmemdup(data, size, GFP_KERNEL); - if (!p) - return; + kfree(ucode_patch_va); /* - * Save for early loading. On 32-bit, that needs to be a physical - * address as the APs are running from physical addresses, before - * paging has been enabled. + * Save the virtual address for early loading on 64bit + * and for eventual free on late loading. + * + * On 32-bit, that needs to store the physical address too as the + * APs are loading before paging has been enabled. */ - if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p); + ucode_patch_va = mc; +} + +static void save_microcode_patch(struct microcode_intel *patch) +{ + struct microcode_intel *mc; + + mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + if (mc) + update_ucode_pointer(mc); else - intel_ucode_patch = (struct microcode_intel *)p; + pr_err("Unable to allocate microcode memory\n"); } /* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ -static struct microcode_intel *scan_microcode(void *data, size_t size, - struct ucode_cpu_info *uci, bool save) +static __init struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; @@ -254,25 +257,15 @@ static struct microcode_intel *scan_micr if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - /* BSP scan: Check whether there is newer microcode */ - if (save && cur_rev >= mc_header->rev) - continue; - - /* Save scan: Check whether there is newer or matching microcode */ - if (save && cur_rev != mc_header->rev) + /* Check whether there is newer microcode */ + if (cur_rev >= mc_header->rev) continue; patch = data; cur_rev = mc_header->rev; } - if (size) - return NULL; - - if (save && patch) - save_microcode_patch(patch, mc_size); - - return patch; + return size ? NULL : patch; } static void print_ucode_info(int old_rev, int new_rev, unsigned int date) @@ -327,14 +320,14 @@ static inline void print_ucode(int old_r } #endif -static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; mc = uci->mc; if (!mc) - return 0; + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -360,7 +353,7 @@ static int apply_microcode_early(struct rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + return UCODE_ERROR; uci->cpu_sig.rev = rev; @@ -369,10 +362,10 @@ static int apply_microcode_early(struct else print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); - return 0; + return UCODE_UPDATED; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) +static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; struct firmware fw; @@ -394,108 +387,96 @@ static bool load_builtin_intel_microcode return false; } -int __init save_microcode_in_initrd_intel(void) +static __init struct microcode_intel *get_ucode_from_cpio(struct ucode_cpu_info *uci) { - struct ucode_cpu_info uci; + bool use_pa = IS_ENABLED(CONFIG_X86_32); + const char *path = ucode_path; struct cpio_data cp; - /* - * initrd is going away, clear patch ptr. We will scan the microcode one - * last time before jettisoning and save a patch, if found. Then we will - * update that pointer too, with a stable patch address to use when - * resuming the cores. - */ - intel_ucode_patch = NULL; + /* Paging is not yet enabled on 32bit! */ + if (IS_ENABLED(CONFIG_X86_32)) + path = (const char *)__pa_nodebug(ucode_path); + /* Try built-in microcode first */ if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(path, use_pa); if (!(cp.data && cp.size)) - return 0; + return NULL; - intel_cpu_collect_info(&uci); + intel_cpu_collect_info(uci); - scan_microcode(cp.data, cp.size, &uci, true); - return 0; + return scan_microcode(cp.data, cp.size, uci); } +static struct microcode_intel *ucode_early_pa __initdata; + /* - * @res_patch, output: a pointer to the patch we found. + * Invoked from an early init call to save the microcode blob which was + * selected during early boot when mm was not usable. The microcode must be + * saved because initrd is going away. It's an early init call so the APs + * just can use the pointer and do not have to scan initrd/builtin firmware + * again. */ -static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) +static int __init save_microcode_from_cpio(void) { - static const char *path; - struct cpio_data cp; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - path = ucode_path; - use_pa = false; - } - - /* try built-in microcode first */ - if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(path, use_pa); - - if (!(cp.data && cp.size)) - return NULL; + struct microcode_intel *mc; - intel_cpu_collect_info(uci); + if (!ucode_early_pa) + return 0; - return scan_microcode(cp.data, cp.size, uci, false); + mc = __va((void *)ucode_early_pa); + save_microcode_patch(mc); + return 0; } +early_initcall(save_microcode_from_cpio); +/* Load microcode on BSP from CPIO */ void __init load_ucode_intel_bsp(void) { - struct microcode_intel *patch; struct ucode_cpu_info uci; - patch = __load_ucode_intel(&uci); - if (!patch) + uci.mc = get_ucode_from_cpio(&uci); + if (!uci.mc) return; - uci.mc = patch; + if (apply_microcode_early(&uci, true) != UCODE_UPDATED) + return; - apply_microcode_early(&uci, true); + if (IS_ENABLED(CONFIG_X86_64)) { + /* Store the physical address as KASLR happens after this. */ + ucode_early_pa = (struct microcode_intel *)__pa_nodebug(uci.mc); + } else { + struct microcode_intel **uce; + + /* Physical address pointer required for 32-bit */ + uce = (struct microcode_intel **)__pa_nodebug(&ucode_early_pa); + /* uci.mc is the physical address of the microcode blob */ + *uce = uci.mc; + } } +/* Load microcode on AP bringup */ void load_ucode_intel_ap(void) { - struct microcode_intel *patch, **iup; struct ucode_cpu_info uci; + /* Must use physical address on 32bit as paging is not yet enabled */ + uci.mc = ucode_patch_va; if (IS_ENABLED(CONFIG_X86_32)) - iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); - else - iup = &intel_ucode_patch; - - if (!*iup) { - patch = __load_ucode_intel(&uci); - if (!patch) - return; - - *iup = patch; - } - - uci.mc = *iup; + uci.mc = (struct microcode_intel *)__pa_nodebug(uci.mc); - apply_microcode_early(&uci, true); + if (uci.mc) + apply_microcode_early(&uci, true); } +/* Reload microcode on resume */ void reload_ucode_intel(void) { - struct ucode_cpu_info uci; - - intel_cpu_collect_info(&uci); + struct ucode_cpu_info uci = { .mc = ucode_patch_va, }; - uci.mc = intel_ucode_patch; - if (!uci.mc) - return; - - apply_microcode_early(&uci, false); + if (uci.mc) + apply_microcode_early(&uci, false); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) @@ -532,7 +513,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = intel_ucode_patch; + mc = ucode_patch_va; if (!mc) { mc = uci->mc; if (!mc) @@ -657,11 +638,11 @@ static enum ucode_state read_ucode_intel if (!new_mc) return UCODE_NFOUND; - vfree(uci->mc); - uci->mc = (struct microcode_intel *)new_mc; - /* Save for CPU hotplug */ - save_microcode_patch(new_mc, new_mc_size); + save_microcode_patch((struct microcode_intel *)new_mc); + uci->mc = ucode_patch_va; + + vfree(new_mc); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, cur_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -172,13 +172,11 @@ static inline int get_totalsize(void *mc void load_ucode_intel_bsp(void); void load_ucode_intel_ap(void); -int save_microcode_in_initrd_intel(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(void) { } static inline void load_ucode_intel_ap(void) { } -static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } static inline void reload_ucode_intel(void) { } static inline struct microcode_ops *init_intel_microcode(void) { return NULL; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t62-20020a638141000000b005638dc9751asi1995287pgd.73.2023.08.10.12.17.56; Thu, 10 Aug 2023 12:18:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="B/8KLpQb"; dkim=neutral (no key) header.i=@linutronix.de header.b=cf1Qav5F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235938AbjHJSic (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235939AbjHJSiL (ORCPT ); Thu, 10 Aug 2023 14:38:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59BBA2D6A for ; Thu, 10 Aug 2023 11:37:54 -0700 (PDT) Message-ID: <20230810160805.820089154@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692668; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oSYfLPVAEKLCJDbK3ZycsrF15tTYnGwu79YnPv4mZKw=; b=B/8KLpQbuMWO+LvmF9cNWuXYj1zGFG1HIP84of6JxLmX2E5zt93ZrSIuVTdeDr+aqgSavI +JgIidaZ6v5dXq54c67QieyPKAfP0GK6XsTDGZjgTrTivHMc2SlnuR3gf5OVs0yVnUUvUV Udh6KStg/tfbYaHBj1En6DoIWv2QjI4wjMBsGGpwu7yoOO8h0hEZQDtHyxhgY0lJthDf4t lFjborFKjLC3LYPbtmZcIpiouIPpjbDm00XCCcd3fGfJzm3yfS7BHTkSrI2roKnHCnDdIy brxaF+yfeB4A4mZZAjNPpjXXXSCFDqo0nen2Xbdmh16ZlkoJSgpWEE3lLH0Jrg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692668; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oSYfLPVAEKLCJDbK3ZycsrF15tTYnGwu79YnPv4mZKw=; b=cf1Qav5FAt+S1+JW9szRZVMoitsJsAU4pksiWwmnm99/+JS44/EXVC1tcg1G7CbZ2TMdQ+ HKNH4uHfNiiiAKDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 15/30] x86/microcode/intel: Save the microcode only after a successful late-load References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:48 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870895957035331 X-GMAIL-MSGID: 1773870895957035331 From: Thomas Gleixner There are situations where the late microcode is loaded into memory, but is not applied: 1) The rendevouz fails 2) The microcode is rejected by the CPUs If any of this happens then the pointer which was updated at firmware load time is stale and subsequent CPU hotplug operations either fail to update or create inconsistent microcode state. Save the loaded microcode in a separate pointer from with the late load is attempted and when successful, update the hotplug pointer accordingly via a new micrcode_ops callback. Remove the pointless fallback in the loader to a microcode pointer which is never populated. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 ++++ arch/x86/kernel/cpu/microcode/intel.c | 30 +++++++++++++++--------------- arch/x86/kernel/cpu/microcode/internal.h | 1 + 3 files changed, 20 insertions(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -443,6 +443,10 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + + if (microcode_ops->finalize_late_load) + microcode_ops->finalize_late_load(ret); + if (!ret) { pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -34,6 +34,7 @@ static const char ucode_path[] = "kernel /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; +static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -517,12 +518,9 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = ucode_patch_va; - if (!mc) { - mc = uci->mc; - if (!mc) - return UCODE_NFOUND; - } + mc = ucode_patch_late; + if (!mc) + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -642,15 +640,7 @@ static enum ucode_state read_ucode_intel if (!new_mc) return UCODE_NFOUND; - /* Save for CPU hotplug */ - save_microcode_patch((struct microcode_intel *)new_mc); - uci->mc = ucode_patch_va; - - vfree(new_mc); - - pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, cur_rev, uci->cpu_sig.rev); - + ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; } @@ -707,10 +697,20 @@ static enum ucode_state request_microcod return ret; } +static void finalize_late_load(int result) +{ + if (!result) + save_microcode_patch(ucode_patch_late); + + vfree(ucode_patch_late); + ucode_patch_late = NULL; +} + static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_intel, + .finalize_late_load = finalize_late_load, }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,6 +31,7 @@ struct microcode_ops { */ enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Thu Aug 10 18:37:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134147 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp612453vqi; Thu, 10 Aug 2023 11:41:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFpvINgUBnaiOieey5uIqrhSlfKUmWz7lv8yer2HZ2IPhtPIhwoQRNYkIEzOLoVNt1xK92i X-Received: by 2002:a2e:8ed9:0:b0:2b9:ad7d:a144 with SMTP id e25-20020a2e8ed9000000b002b9ad7da144mr2760151ljl.11.1691692906100; Thu, 10 Aug 2023 11:41:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691692906; cv=none; d=google.com; s=arc-20160816; b=nCNdwwa+hdJEQh+VuwT606OrwiW5VdxrSEK/F7HQO7YQRTyqhM/sVHhfIL3b9TTlu0 DAZ0XLwOfIwnxmraZJZ9ePcpG/ZPp/f8g9aqIye104taBmPNmpW/K0EU+RjrcCXhJ876 hwF7NNfpiCatpGj5LG/LnUffXMy4Ark5OjtUww3+T0e5Fu5HX80wl3cb0YhK6Njq22UM qniwNPyBvzbbu4QxVgq4Qetsgxssql42b4Nmagn7h3DKtJt9BW/hlVb3n1N0TmTxG6CT +CWzZTJrMDPOBuSlfokE2GY0NGKTTHMQAK+tlb8X2CEwo3R6bNeRSsWtBatwzoO042UT uxjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=HpjZz3joiv1/p3KpDArr5GSQpKRsQ6zE6sK4hsYD7vw=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=lHj80LxR5ixOQO0AwjOgK7OvZ2CJb2pWTZ553BQ/3sbk4SfZI0l8k7E9Jn/W2ytmb0 IFLBvL+A0WERZCxpT4wMp9mfFYyVh66m2BPGLNgczpR6pIhG4rruXYzm0QTc3N4ihIOK IxNdgf5tBwT8W/6bI83ns8xpUkSHVudDLAECJWE34VSERTuzf73HOCV7iss0wWfGqpbG /u4AgpwM58WmwhkcwkH7W75RJye2Z8JpfOQBPZLIhUkl6C00J1g3KB3LxzYL6wiWPYRI MjV8/oPTpmXZ3k+EVkIdBmoqwL3yd/DJChcASYMUZNr4S7gmU/dz4Be3/aTd73CqyBNe agXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=RaL3eagM; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i25-20020a17090671d900b0099283fccb49si2120479ejk.232.2023.08.10.11.41.21; Thu, 10 Aug 2023 11:41:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=RaL3eagM; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235860AbjHJSil (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235858AbjHJSiO (ORCPT ); Thu, 10 Aug 2023 14:38:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D59F35AE for ; Thu, 10 Aug 2023 11:37:59 -0700 (PDT) Message-ID: <20230810160805.875358976@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692670; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HpjZz3joiv1/p3KpDArr5GSQpKRsQ6zE6sK4hsYD7vw=; b=RaL3eagMftpdaXHcoae8toc0LFTWXiR6FbcqY5rin6RFTKH94F7NWiiI1eKo8aVAZS0Z1l bPDMoVdKjWjNdzUot6bUZQlenrhqe6osYtf949ZyyCuIwO6ZMS07NX5W+rNG5/dbtY8L27 1Oh4h3IJQVfxk6AaGAJ2PSOO/oK+3Y/cnnaaaNJeH7YjoQ+nPG/8aJYJd2cfj5IqvIi25i KX9mdfBpoIYvPLodrnTKgcn7sfflfKOhIUwdtIfONGLUwgUHcbGZzT5UJc76D4YDo5IH+P SczJolpY/gq07IiiHs3yVLoDNkl5OcgCBDvIpCB2jjZC8vrzTPandOXdOa0XAg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692670; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=HpjZz3joiv1/p3KpDArr5GSQpKRsQ6zE6sK4hsYD7vw=; b=iNvZVVc+/sVAXpRDUgv2DlEPQQIAyqQRMXlvvEmoGFuc4ua90FGQkHDe/JbjccjLqkdq/N cqlM21G5ZNLmDLDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 16/30] x86/microcode/intel: Switch to kvmalloc() References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:49 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773868580922815316 X-GMAIL-MSGID: 1773868580922815316 From: Thomas Gleixner Microcode blobs are getting larger and might soon reach the kmalloc() limit. Switch over kvmalloc(). 32-bit has to stay with kmalloc() as it needs physically contiguous memory because the early loading runs before paging is enabled, so there is a sanity check added to ensure that. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 55 +++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 23 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -215,7 +214,7 @@ EXPORT_SYMBOL_GPL(intel_microcode_sanity static void update_ucode_pointer(struct microcode_intel *mc) { - kfree(ucode_patch_va); + kvfree(ucode_patch_va); /* * Save the virtual address for early loading on 64bit @@ -229,13 +228,18 @@ static void update_ucode_pointer(struct static void save_microcode_patch(struct microcode_intel *patch) { - struct microcode_intel *mc; + unsigned int size = get_totalsize(&patch->hdr); + struct microcode_intel *mc = NULL; + + if (IS_ENABLED(CONFIG_X86_64)) + mc = kvmemdup(patch, size, GFP_KERNEL); + else + mc = kmemdup(patch, size, GFP_KERNEL); - mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); if (mc) update_ucode_pointer(mc); else - pr_err("Unable to allocate microcode memory\n"); + pr_err("Unable to allocate microcode memory size: %u\n", size); } /* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ @@ -586,36 +590,34 @@ static enum ucode_state read_ucode_intel if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) { pr_err("error! Truncated or inaccessible header in microcode data file\n"); - break; + goto fail; } mc_size = get_totalsize(&mc_header); if (mc_size < sizeof(mc_header)) { pr_err("error! Bad data in microcode data file (totalsize too small)\n"); - break; + goto fail; } - data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); - break; + goto fail; } /* For performance reasons, reuse mc area when possible */ if (!mc || mc_size > curr_mc_size) { - vfree(mc); - mc = vmalloc(mc_size); + kvfree(mc); + mc = kvmalloc(mc_size, GFP_KERNEL); if (!mc) - break; + goto fail; curr_mc_size = mc_size; } memcpy(mc, &mc_header, sizeof(mc_header)); data = mc + sizeof(mc_header); if (!copy_from_iter_full(data, data_size, iter) || - intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) { - break; - } + intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) + goto fail; if (cur_rev >= mc_header.rev) continue; @@ -623,25 +625,32 @@ static enum ucode_state read_ucode_intel if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - vfree(new_mc); + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; new_mc_size = mc_size; mc = NULL; } - vfree(mc); + if (iov_iter_count(iter)) + goto fail; - if (iov_iter_count(iter)) { - vfree(new_mc); - return UCODE_ERROR; + if (IS_ENABLED(CONFIG_X86_32) && new_mc && is_vmalloc_addr(new_mc)) { + pr_err("Microcode too large for 32-bit mode\n"); + goto fail; } + kvfree(mc); if (!new_mc) return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; + +fail: + kvfree(mc); + kvfree(new_mc); + return UCODE_ERROR; } static bool is_blacklisted(unsigned int cpu) @@ -700,9 +709,9 @@ static enum ucode_state request_microcod static void finalize_late_load(int result) { if (!result) - save_microcode_patch(ucode_patch_late); - - vfree(ucode_patch_late); + update_ucode_pointer(ucode_patch_late); + else + kvfree(ucode_patch_late); ucode_patch_late = NULL; } From patchwork Thu Aug 10 18:37:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134170 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp632482vqi; Thu, 10 Aug 2023 12:18:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHpmJu7Ibjt2wx2zcrMmsUXBlH7KO9xDOgY4HBDVAyaCzT+A1j0+lGjYzloK86e/OzkRNos X-Received: by 2002:a17:90a:85:b0:269:12a5:c1df with SMTP id a5-20020a17090a008500b0026912a5c1dfmr3815549pja.3.1691695114147; Thu, 10 Aug 2023 12:18:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691695114; cv=none; d=google.com; s=arc-20160816; b=w+QhWHjFMrS3PlmuZnLoK3FfLoNp3bCj+bLUsGrX+TrxqM670AwsyCtw7LiOgThxbz 7TsDYeYdcPtWp6NLfgl5fdf1fVz55pNFc2tVTlPvLld4shU6FV3Qmi+6R6MkKMWQC244 2/Zcd79xDaLwZe6em2yvZnA6eAoybOzBr6P5/bBSXwCGLdNDuFk2VbhJwQrV/Tb0xKJd J7kaV/TxTbOOw9pxsaCkXtrOzKCnFfktIbgF9H/tA0xelx28DdTbkNKG6Wbe+i7rM0AH 5fZ4nYw3HIoDV3niN/y0A5toyvijIqXj2RO/gs+Yr7yGi2i6wGHDbtyVh5/nBK42MUEy KQuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=RyAZdhYUiy48Y/XZU7T04DGYjgBzGOlb8fG6vAh+kH8=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=G+Fk0h0MxMzOMMLki+8cAfL+pNLLDiYlReA9p8kBPahgUsB/rYXVOD1ByUN636pMRb NwGkQ4nf3+dYp7R1P+U+C2Yqnej7RG/JbC68JZAjZ9fCIZXmBs4i0mfqwUm0ne/Jv7YZ vY89APUFRk0lst+CWaR7xIIGXsMLdVhW/A5Yv89rdGhVFq18lW+om7cYhLq61AT6EmbW UtQfz5Jvdxqa7m0gZK4BTctt1GIhoYh230+sHCBDnJoM4DMuL4gzf3q5jfIoZSZjH2l2 Ea4fVD7SpFVhTJCskC002HLaGH9mZrEWRZnk02L6tptxFpeLsUOd5A0mEbXHkdttjcYu q82w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=objlsPC5; dkim=neutral (no key) header.i=@linutronix.de header.b=aNLvWxAC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 13-20020a17090a098d00b00268273fffc0si4153257pjo.99.2023.08.10.12.18.19; Thu, 10 Aug 2023 12:18:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=objlsPC5; dkim=neutral (no key) header.i=@linutronix.de header.b=aNLvWxAC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235797AbjHJSiw (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235722AbjHJSiV (ORCPT ); Thu, 10 Aug 2023 14:38:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95BC92D76 for ; Thu, 10 Aug 2023 11:38:04 -0700 (PDT) Message-ID: <20230810160805.934494281@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyAZdhYUiy48Y/XZU7T04DGYjgBzGOlb8fG6vAh+kH8=; b=objlsPC5h9djIldT3K9DGzT6gg0Gle0YRmjhie3pkoZHJ2J+liU8y+mBf3odMvKlaCy5UI Y6+thqLLndVAKigGdlGRI5Baokm5s9+H+SO9Q9akkF+UzY74KD1CP6K4fkWlqazTlPSWc9 ixvambj9dX8vLV/+ghEs8p2bzTofBgsDRc93C1EfBVpXuIc2UNXYyGQexDqaAlbV9/G5CR XGJ556PQWbWZVehUtfUZyUIapN4+fXVbZWmV1M6Aqkz2y4hjTmOGg7h0wityLnG5qQ19qF Ectzb7jJvOvohZH3H3kCIzf3b7TzJTNq24Pg6DF6Jd3YpFX+AdqGvcNrpFKVrg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyAZdhYUiy48Y/XZU7T04DGYjgBzGOlb8fG6vAh+kH8=; b=aNLvWxACY/b8sKvBkd5MAE6FupxaDbd0VrSDoAmdtpxcs4HLLKIrJiwdEyiKY/BjIQ/eXW 9LztDo1ftqSkDlBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 17/30] x86/microcode/intel: Unify microcode apply() functions References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:51 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,PDS_OTHER_BAD_TLD, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870895971963654 X-GMAIL-MSGID: 1773870895971963654 Deduplicate the early and late apply() functions. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 106 +++++++++++----------------------- 1 file changed, 36 insertions(+), 70 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -325,12 +325,11 @@ static inline void print_ucode(int old_r } #endif -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static enum ucode_state apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev; + u32 rev; - mc = uci->mc; if (!mc) return UCODE_NFOUND; @@ -339,14 +338,12 @@ static enum ucode_state apply_microcode_ * operation - when the other hyperthread has updated the microcode * already. */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - uci->cpu_sig.rev = rev; + *cur_rev = intel_get_microcode_revision(); + if (*cur_rev >= mc->hdr.rev) { + uci->cpu_sig.rev = *cur_rev; return UCODE_OK; } - old_rev = rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -361,13 +358,23 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; uci->cpu_sig.rev = rev; + return UCODE_UPDATED; +} - if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); - else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, bool early) +{ + struct microcode_intel *mc = uci->mc; + enum ucode_state ret; + u32 cur_rev; - return UCODE_UPDATED; + ret = apply_microcode(uci, mc, &cur_rev); + if (ret == UCODE_UPDATED) { + if (early) + print_ucode(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + else + print_ucode_info(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + } + return ret; } static __init bool load_builtin_intel_microcode(struct cpio_data *cp) @@ -508,70 +515,29 @@ static int collect_cpu_info(int cpu_num, return 0; } -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc = ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; - - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() != cpu)) - return UCODE_ERROR; - - mc = ucode_patch_late; - if (!mc) - return UCODE_NFOUND; + u32 cur_rev; - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - ret = UCODE_OK; - goto out; - } - - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev = intel_get_microcode_revision(); - - if (rev != mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); + if (WARN_ON_ONCE(smp_processor_id() != cpu)) return UCODE_ERROR; - } - if (bsp && rev != prev_rev) { - pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + ret = apply_microcode(uci, mc, &cur_rev); + if (ret != UCODE_UPDATED && ret != UCODE_OK) + return ret; + + if (!cpu && uci->cpu_sig.rev != cur_rev) { + pr_info("Updated to revision 0x%x, date = %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev = rev; } - ret = UCODE_UPDATED; - -out: - uci->cpu_sig.rev = rev; - c->microcode = rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode = rev; + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; return ret; } @@ -718,7 +684,7 @@ static void finalize_late_load(int resul static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, }; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qo21-20020a170907213500b0098cf3eaee47si2093277ejb.689.2023.08.10.12.55.49; Thu, 10 Aug 2023 12:56:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=I1tvp3sQ; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234557AbjHJSis (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235854AbjHJSiO (ORCPT ); Thu, 10 Aug 2023 14:38:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B51EF35AD for ; Thu, 10 Aug 2023 11:37:58 -0700 (PDT) Message-ID: <20230810160805.990936778@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692673; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Rab/GTu2nZ+oA1azvFmHvo6TFMlBo033l6ZZymTgpxs=; b=I1tvp3sQgBxkVj1XMQUfPcR79u9hZ/wT2F3k3w6fILe0jcuIPUUb1mMp1BiefG/PKBhXj9 LqXQSTXWKzLsS6FjeiQxa32Z0UrkHGKbG3tvJr78EFjzPKqbV5Ek4xJxHzgrdyqCh3I9t6 NsGMSjTK93pJy1car6PA7Lla2bBDnWD/51xfhGBBMSecEyL8C1GOXSchnl8b0GkHxKJA1l LDoNyGid1MFsrpB0XR7Uol06xc4PVyAOAhm7a1b2c0dSO0aEqFI3pFuh7ilzF9QCSIPAnU Ea+e3B5fnUiDrDmh/Y8YXvf6V4W68WzZQwvEL55PotCunuHYsokDp/Z26h4UyQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692673; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Rab/GTu2nZ+oA1azvFmHvo6TFMlBo033l6ZZymTgpxs=; b=CKWtb0eoHJ4lTsVc7w/GvCKfFUNq6P8Ta+r+Sj9zC8hDbDyMh5B8drInP8IWAQwqRMeEYN 9VdZztY7xfAy6rCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 18/30] x86/microcode: Handle "nosmt" correctly References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:52 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773873265533489311 X-GMAIL-MSGID: 1773873265533489311 From: Thomas Gleixner On CPUs where microcode loading is not NMI safe the SMT sibling which is parked in one of the play_dead() variants, these parked CPUs still react on NMIs. So if a NMI hits while the primary thread updates the microcode the resulting behaviour is undefined. The default play_dead() implementation on modern CPUs is using MWAIT, which is not guaranteed to be safe against an microcode update which affects MWAIT. Take the cpus_booted_once_mask into account to detect this case and refuse to load late if the vendor specific driver does not advertise that late loading is NMI safe. AMD stated that this is safe, so mark the AMD driver accordingly. This requirement will be partially lifted in later changes. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 2 - arch/x86/kernel/cpu/microcode/amd.c | 9 +++-- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------ arch/x86/kernel/cpu/microcode/internal.h | 13 +++---- 4 files changed, 44 insertions(+), 31 deletions(-) --- --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1314,7 +1314,7 @@ config MICROCODE config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n - depends on MICROCODE + depends on MICROCODE && SMP help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -909,10 +909,11 @@ static void microcode_fini_cpu_amd(int c } static struct microcode_ops microcode_amd_ops = { - .request_microcode_fw = request_microcode_amd, - .collect_cpu_info = collect_cpu_info_amd, - .apply_microcode = apply_microcode_amd, - .microcode_fini_cpu = microcode_fini_cpu_amd, + .request_microcode_fw = request_microcode_amd, + .collect_cpu_info = collect_cpu_info_amd, + .apply_microcode = apply_microcode_amd, + .microcode_fini_cpu = microcode_fini_cpu_amd, + .nmi_safe = true, }; struct microcode_ops * __init init_amd_microcode(void) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -326,23 +326,6 @@ static struct platform_device *microcode */ #define SPINUNIT 100 /* 100 nsec */ -static int check_online_cpus(void) -{ - unsigned int cpu; - - /* - * Make sure all CPUs are online. It's fine for SMT to be disabled if - * all the primary threads are still online. - */ - for_each_present_cpu(cpu) { - if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { - pr_err("Not all CPUs online, aborting microcode update.\n"); - return -EINVAL; - } - } - - return 0; -} static atomic_t late_cpus_in; static atomic_t late_cpus_out; @@ -459,6 +442,35 @@ static int microcode_reload_late(void) return ret; } +/* + * Ensure that all required CPUs which are present and have been booted + * once are online. + * + * To pass this check, all primary threads must be online. + * + * If the microcode load is not safe against NMI then all SMT threads + * must be online as well because they still react on NMI when they are + * soft-offlined and parked in one of the play_dead() variants. So if a + * NMI hits while the primary thread updates the microcode the resulting + * behaviour is undefined. The default play_dead() implementation on + * modern CPUs is using MWAIT, which is also not guaranteed to be safe + * against a microcode update which affects MWAIT. + */ +static bool ensure_cpus_are_online(void) +{ + unsigned int cpu; + + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + if (!cpu_online(cpu)) { + if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { + pr_err("CPU %u not online\n", cpu); + return false; + } + } + } + return true; +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) @@ -474,9 +486,10 @@ static ssize_t reload_store(struct devic cpus_read_lock(); - ret = check_online_cpus(); - if (ret) + if (!ensure_cpus_are_online()) { + ret = -EBUSY; goto put; + } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -20,18 +20,17 @@ enum ucode_state { struct microcode_ops { enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); - void (*microcode_fini_cpu)(int cpu); /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. + * The generic 'microcode_core' part guarantees that the callbacks + * below run on a target cpu when they are being called. * See also the "Synchronization" section in microcode_core.c. */ - enum ucode_state (*apply_microcode)(int cpu); - int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); - void (*finalize_late_load)(int result); + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); + unsigned int nmi_safe : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Thu Aug 10 18:37:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp645112vqi; Thu, 10 Aug 2023 12:44:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVoaUZqjz9yDj8a/pYcCa6RIQwly+BJUdIbM8sRSkx3EHbgaNFljzh0GNhtbQ8gowDcVfM X-Received: by 2002:a05:6000:1ca:b0:317:f70b:3156 with SMTP id t10-20020a05600001ca00b00317f70b3156mr3132610wrx.28.1691696686027; Thu, 10 Aug 2023 12:44:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691696686; cv=none; d=google.com; s=arc-20160816; b=ADDm4EWDvWnSgQCYDQFoA8QvfSs1+EuygziXZO9SZoAFc2LG17lLfg/cU0daGTOTev 6hDgzAiSQm2Kh92+Clscmfp0vheLbnB7UjdWytqAQh44wrMZlvnRAhx5C7R3YmHCjf55 yLjP7mE+PMfc22jiLEQmRpvbo6prR4uohd2PR70USmKK52y1vb5JO3x0E/6wwcG5MA3f FhczpoTDo033z0nHkhOgEOHTiScE/DGwwBiNCsVMsFXxBssQ65dfoSQ7DGbMxlFmdeD8 u9yUPOy4SLY+Qsban/BdDWxC6x/XAzXCY3phCGaN9hGdox1qYlFGtqL+bRTsHVakk3aE 6gXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=hlx8DLPpIxj4vSRut/3Ez+T3yk2mTuvjS8O2HCgQ/IyPUaAjwDUZkS+E7VJ9OuP1b/ TlqAfm8Z8HC12UOBJGzgSEjEa1mRl88VpaENLEUVJvYGw36qDwzlboojzxZZqk688b7X ho4OQfOo8LTXBaF+q+goxrcRYbpWeAQ8wbpemBA1msFaLiD35A5JYxA98UROZEdaWrcN agMEeh+0HXIztUliGcJ5Jk1FXbAnyPJ/AuUXXXrbAXtWvjAZ9XwBD21y8FJhASB3wmJr KHuwu/rgFagmASfobfHmtMcdhZk1CCM7TDwhQu/PX6cB2f2uBX2nyfy2/kh1g4/DWHhP omUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hfrWNLOe; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z10-20020a170906714a00b00991f3517cbdsi2265876ejj.1.2023.08.10.12.44.20; Thu, 10 Aug 2023 12:44:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hfrWNLOe; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235920AbjHJSjB (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235680AbjHJSi0 (ORCPT ); Thu, 10 Aug 2023 14:38:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F20E230DE for ; Thu, 10 Aug 2023 11:38:08 -0700 (PDT) Message-ID: <20230810160806.045993293@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692674; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; b=hfrWNLOegUu4KFmmwtUdNxRRybdEpP40zi+zNifw/u7YhrlTyhYln9MRheJssnIsYwKGyZ 54kuHgELMhgTvWRZxZm8oBzH7f1TaSCbHQf/p7qrionCMxiHtDAYb6rSIWKCgn0CQtYetN 381sTQUk64k2jzNZxgJIqOYMEPY+B1oooRW2pLaXPAt1UlWXLVxUylJcTTeyHnPzL1PkJI bsy1Ly21NOvL/slioHOJ4Jkqu6AJJD6RIbXsIN0D37suB6usAsuCVROzg4llKMJQQqx1Vl rQ31lunOk7BQBxz2g5HXFP7oxHCS6mfpezlyB18tw+8eB3hDcFbJTRgIJgdvAw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692674; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qicvq4u13+GKL+4eW6ZEQQqFYpQClLZfFC5XYmTA1Qw=; b=PnsBdyNWZmGwqsq3lrJu4HlEKmnNvODRRntf8X6FMLk/xD0/y1JAa6TwPifvJ2gsAqh4LM 3T5eNkpQziSmB1BQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 19/30] x86/microcode: Clarify the late load logic References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:54 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773872543919618779 X-GMAIL-MSGID: 1773872543919618779 From: Thomas Gleixner reload_store() is way too complicated. Split the inner workings out and make the following enhancements: - Taint the kernel only when the microcode was actually updated. If. e.g. the rendevouz fails, then nothing happened and there is no reason for tainting. - Return useful error codes Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -434,11 +434,11 @@ static int microcode_reload_late(void) pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); microcode_check(&prev_info); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); } else { pr_info("Reload failed, current microcode revision: 0x%x\n", boot_cpu_data.microcode); } - return ret; } @@ -471,40 +471,35 @@ static bool ensure_cpus_are_online(void) return true; } +static int ucode_load_late_locked(void) +{ + int ret; + + if (!ensure_cpus_are_online()) + return -EBUSY; + + ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); + if (ret != UCODE_NEW) + return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; + return microcode_reload_late(); +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { - enum ucode_state tmp_ret = UCODE_OK; - int bsp = boot_cpu_data.cpu_index; unsigned long val; - ssize_t ret = 0; + ssize_t ret; ret = kstrtoul(buf, 0, &val); if (ret || val != 1) return -EINVAL; cpus_read_lock(); - - if (!ensure_cpus_are_online()) { - ret = -EBUSY; - goto put; - } - - tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); - if (tmp_ret != UCODE_NEW) - goto put; - - ret = microcode_reload_late(); -put: + ret = ucode_load_late_locked(); cpus_read_unlock(); - if (ret == 0) - ret = size; - - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - - return ret; + return ret ? : size; } static DEVICE_ATTR_WO(reload); From patchwork Thu Aug 10 18:37:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134148 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp613182vqi; Thu, 10 Aug 2023 11:43:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHlleOxnlmjd5GrhqKsHrpmcPz/70v8x2ezM3Ae867mfl2uJUmViEA6mxxYnxxNCsPNqzGg X-Received: by 2002:aa7:dd02:0:b0:522:3a89:a7bc with SMTP id i2-20020aa7dd02000000b005223a89a7bcmr2407463edv.42.1691693000036; Thu, 10 Aug 2023 11:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691693000; cv=none; d=google.com; s=arc-20160816; b=AUR/5SvGHoE/72T23ZgX/mqeSvuvUQuMhRzcLy+4qctE+SudrCslfTX5favalTaw+N q2/ZkKqUFaWBGu6xDsDpe2EiGTqD9m3EvnaVD1RrF6l4DCtMN2EEwThe1yjkwR3bYC73 wYoj/k6AYiiCfmdnaEZDTdhaBFvoVZS5TyRMFx8JsGx6wQZpzdDoQsqyZaD90Q1FJ1Oo blQ6HXCYas6cZQ6DDSMhgdJ1DMaQdFASXZUO99g5z5kZxjuanK+7Zlh2PeirX3HuQ5eW sBw1dSaqsI0zpwzbftDuTFe8hxwmddxnW2lHf2+xhzHSFLcOUa9vLdJvgyZO/neGYaqT /vDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=j1NjM0tSSkY7Jz8TMRXQNjWPLs/9txZHgpkL9Qd3+CsrMnegS648LewW6hm7ZggaV2 JVm+YeqFFGE6Frw8rd9rJ7N9+z/0ZAOkjuRCqIyZ40fCw+3zT3lkk3VqxrO8aYQ3PflU mHme23yxHOixmL8K5mM14YisIMYZsS2wE6Ire5wQGspYDP7KG43xMzTw4ZnpXPh+VqRb b97cPN7jL+eEQhnSBSwKVM9P/igMo9gNvWf/zJjBtBOJZ7xKv3mRamn5YVNrY32rERrZ fa/mS8EkUOTW9MBoPQgIzJ0TD2Ni4CVP0i3BZsaVa8+aUyNz1hNvYFBzitOTWKk1ib0B drGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UAjkdYMi; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b6-20020aa7d486000000b00523220e5c18si2039930edr.638.2023.08.10.11.42.55; Thu, 10 Aug 2023 11:43:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UAjkdYMi; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235230AbjHJSiz (ORCPT + 99 others); Thu, 10 Aug 2023 14:38:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235893AbjHJSiW (ORCPT ); Thu, 10 Aug 2023 14:38:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AB4530C7 for ; Thu, 10 Aug 2023 11:38:06 -0700 (PDT) Message-ID: <20230810160806.103791682@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; b=UAjkdYMii7C+JL70axRtF22S7GqkjgMyjVYk1NPlMMDWj2yIVVY+btcQ+PGNZg8JOQ+dpF Gc28czrsf5hMuIDheHQbIKpN/JtG7VUX5TW3VjohEIkbOoZv3s3KdoSml65VOSVHy9A2uy pHZRDoZSgHh3vzz3a1A1AtwK8ykOAhA3XaMpKwpXGBt4upAjtSkwIAB98kjdeqtWRXzhSU Jv6Jn80Dr0V+JuXKopLzLCE0112K+QELqvTEeMEbWfMC+vlLcphegZ7+xy463N4XQ5P4lZ 8oHyUdgDR2M+zf9pUBkkRkOspMAenADadGWXTW+AHHeLzweP2HFbbfGl+iyZ7Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/mf0toaJNTepRqxmdRBH+YrhPsSto1ib/DfMaTt6vf0=; b=DVrOz3cOohcHSque6Fewmr1QsvJQ9sfVGQbHSzfV/ZaoqAFGZ3DHnD8MSZg2zXg/jatNPu Qs7Vaudgzrxm5kAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 20/30] x86/microcode: Sanitize __wait_for_cpus() References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:55 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773868678873023122 X-GMAIL-MSGID: 1773868678873023122 From: Thomas Gleixner The code is too complicated for no reason: - The return value is pointless as this is a strict boolean. - It's way simpler to count down from num_online_cpus() and check for zero. - The timeout argument is pointless as this is always one second. - Touching the NMI watchdog every 100ns does not make any sense, neither does checking every 100ns. This is really not a hotpath operation. Preload the atomic counter with the number of online CPUs and simplify the whole timeout logic. Delay for one microsecond and touch the NMI watchdog once per millisecond. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 41 ++++++++++++++--------------------- 1 file changed, 17 insertions(+), 24 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,31 +324,24 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ -#define SPINUNIT 100 /* 100 nsec */ +static atomic_t late_cpus_in, late_cpus_out; - -static atomic_t late_cpus_in; -static atomic_t late_cpus_out; - -static int __wait_for_cpus(atomic_t *t, long long timeout) +static bool wait_for_cpus(atomic_t *cnt) { - int all_cpus = num_online_cpus(); - - atomic_inc(t); - - while (atomic_read(t) < all_cpus) { - if (timeout < SPINUNIT) { - pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", - all_cpus - atomic_read(t)); - return 1; - } + unsigned int timeout; - ndelay(SPINUNIT); - timeout -= SPINUNIT; + WARN_ON_ONCE(atomic_dec_return(cnt) < 0); - touch_nmi_watchdog(); + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (!atomic_read(cnt)) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); } - return 0; + /* Prevent the late comers to make progress and let them time out */ + atomic_inc(cnt); + return false; } /* @@ -366,7 +359,7 @@ static int __reload_late(void *info) * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_in)) return -1; /* @@ -389,7 +382,7 @@ static int __reload_late(void *info) } wait_for_siblings: - if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_out)) panic("Timeout during microcode update!\n"); /* @@ -416,8 +409,8 @@ static int microcode_reload_late(void) pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); - atomic_set(&late_cpus_out, 0); + atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Thu Aug 10 18:37:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134172 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp632685vqi; Thu, 10 Aug 2023 12:18:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHG7EYlyNNmsIowRKIvUzXNmUXHqMb8O59LR9cldRsT1duuA1RypQ8Wg870el8UK5P58xy X-Received: by 2002:a05:6a00:398c:b0:66c:6766:7373 with SMTP id fi12-20020a056a00398c00b0066c67667373mr3184539pfb.23.1691695133257; Thu, 10 Aug 2023 12:18:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691695133; cv=none; d=google.com; s=arc-20160816; b=0wlYepzsnSslJTiQa7Uh9IAJuEbnV1oUv4m4IYO4FyCrIliqyS535+uzW7mDEyEHQ+ Ukxko2PVrrIaC7yjqGuJlpxjKpwRXW9bfcI3b+buYG7R4vsPMQIHNgcz7zYq3f1iyhB3 Ac0ZGszXr3g5k2PBN1ESPwEMc7bbrECwywdEp9o4UZ1Qt7aLPN3XAxueLX9KCJMpPTQv e0DkB3Q3hk1kBAp+S2Vp/HumguXuxZ9XxoTSo7m4lJu8cOqycfdIcRMOmEi/YdwpA19I n9AMmMI6hK6Bm6Y8oqYaNLkthco0JX41cShJVb77Qz7wWRQPqTTtantuXRQrsaBp4Rmn GmFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=mlb/ZMtns93MVBnUHhWY0qQSORk37/j+VOBz1xgJd2aMR4ccGzKpODBwkHw9q6Emi2 n6yoWCmHFbe69pn53o5SsU00Y51mC1iEbIt33oE05GZrqFndXmNcOrSpxA2XGsGlynWv W9elzZG3NkQuKzoGw4v4cue3e+xIZORJS9XHlIw2pD3BmoNAbXIB5WH8Xb8DrFk7dy56 s2Sjt0cDhR0JxH3AUFn04eGWOP5vJFn7uXr/GoM79sRSoMhAu7Q0KlcI1n32ZS62tsUu RdQA5yURo7wJjKEe2Os7IPbqgYiX4iW5/lUXzHBOhRJUF7Fv2Xjz/lovakxsh6WMi89k CfyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=jWBI8F5o; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t62-20020a638141000000b005638dc9751asi1995287pgd.73.2023.08.10.12.18.40; Thu, 10 Aug 2023 12:18:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=jWBI8F5o; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235046AbjHJSjC (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235766AbjHJSi3 (ORCPT ); Thu, 10 Aug 2023 14:38:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C4F930E5 for ; Thu, 10 Aug 2023 11:38:12 -0700 (PDT) Message-ID: <20230810160806.164799931@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; b=jWBI8F5o6zbGFRWlgo8gxOe91PUCTu3tc5OSvW1vfk7yMuTqyqi1VBzbHPVpJRKE5wOj+K bzjSXtQRM/gblXh7O42yM367uHkbuRUas5zz4I+BhwbVFXdprRCYz4qI3UUGOcZIPSHffC XH/o0zA4ZYBaaq2PrFrcB7lQUlxwKkxT17noqZ8wjvwfWQ6bX20CrigskV0F6xvJX+4LOW mp8KyDJ23/Imw2+rK5Aowji9KQFcaiTwlzzaTBDPlHGAy4Zd+Mnm6RVRJ0knQdA5VY6wBA VukKZPjqydQCsMTVXwk7kNrQEU7+ku99RMVfccriXU7mCh2l/MW9MByDFfQjLw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2kqLUw1a4gV9FrIDWZ/O+PSOOuBOB0W9vRdpe8yDcXg=; b=EZ7VF7x91ea0u8MPqXzi1WUoffIdwLpTUGPs/g2wZNRb8P1dVfBL+/kmD8YLi7QYPT2kHp /3U/yYOIalyz4wCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 21/30] x86/microcode: Add per CPU result state References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:57 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870916433798658 X-GMAIL-MSGID: 1773870916433798658 From: Thomas Gleixner The microcode rendevouz is purely acting on global state, which does not allow to analyze fails in a coherent way. Introduce per CPU state where the results are written into, which allows to analyze the return codes of the individual CPUs. Initialize the state when walking the cpu_present_mask in the online check to avoid another for_each_cpu() loop. Enhance the result print out with that. The structure is intentionally named ucode_ctrl as it will gain control fields in subsequent changes. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 108 ++++++++++++++++++------------- arch/x86/kernel/cpu/microcode/internal.h | 1 2 files changed, 65 insertions(+), 44 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,6 +324,11 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +struct ucode_ctrl { + enum ucode_state result; +}; + +static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, late_cpus_out; static bool wait_for_cpus(atomic_t *cnt) @@ -344,23 +349,19 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } -/* - * Returns: - * < 0 - on error - * 0 - success (no update done or microcode was updated) - */ -static int __reload_late(void *info) +static int ucode_load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); - enum ucode_state err; - int ret = 0; + enum ucode_state ret; /* * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (!wait_for_cpus(&late_cpus_in)) - return -1; + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return 0; + } /* * On an SMT system, it suffices to load the microcode on one sibling of @@ -369,17 +370,11 @@ static int __reload_late(void *info) * loading attempts happen on multiple threads of an SMT core. See * below. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - err = microcode_ops->apply_microcode(cpu); - else + if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) goto wait_for_siblings; - if (err >= UCODE_NFOUND) { - if (err == UCODE_ERROR) { - pr_warn("Error reloading microcode on CPU %d\n", cpu); - ret = -1; - } - } + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); wait_for_siblings: if (!wait_for_cpus(&late_cpus_out)) @@ -391,19 +386,18 @@ static int __reload_late(void *info) * per-cpu cpuinfo can be updated with right microcode * revision. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - err = microcode_ops->apply_microcode(cpu); + if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) + return 0; - return ret; + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + return 0; } -/* - * Reload microcode late on all CPUs. Wait for a sec until they - * all gather together. - */ -static int microcode_reload_late(void) +static int ucode_load_late_stop_cpus(void) { - int old = boot_cpu_data.microcode, ret; + unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); @@ -418,26 +412,47 @@ static int microcode_reload_late(void) */ store_cpu_caps(&prev_info); - ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + stop_machine_cpuslocked(ucode_load_cpus_stopped, NULL, cpu_online_mask); + + /* Analyze the results */ + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + switch (per_cpu(ucode_ctrl.result, cpu)) { + case UCODE_UPDATED: updated++; break; + case UCODE_TIMEOUT: timedout++; break; + case UCODE_OK: siblings++; break; + default: failed++; break; + } + } if (microcode_ops->finalize_late_load) - microcode_ops->finalize_late_load(ret); + microcode_ops->finalize_late_load(!updated); - if (!ret) { - pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); - microcode_check(&prev_info); - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - } else { - pr_info("Reload failed, current microcode revision: 0x%x\n", - boot_cpu_data.microcode); + if (!updated) { + /* Nothing changed. */ + if (!failed && !timedout) + return 0; + pr_err("Microcode update failed: %u CPUs failed %u CPUs timed out\n", + failed, timedout); + return -EIO; } - return ret; + + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("Microcode load: updated on %u primary CPUs with %u siblings\n", updated, siblings); + if (failed || timedout) { + pr_err("Microcode load incomplete. %u CPUs timed out or failed\n", + num_online_cpus() - (updated + siblings)); + } + pr_info("Microcode revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); + microcode_check(&prev_info); + + return updated + siblings == num_online_cpus() ? 0 : -EIO; } /* - * Ensure that all required CPUs which are present and have been booted - * once are online. + * This function does two things: + * + * 1) Ensure that all required CPUs which are present and have been booted + * once are online. * * To pass this check, all primary threads must be online. * @@ -448,9 +463,12 @@ static int microcode_reload_late(void) * behaviour is undefined. The default play_dead() implementation on * modern CPUs is using MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. + * + * 2) Initialize the per CPU control structure */ -static bool ensure_cpus_are_online(void) +static bool ucode_setup_cpus(void) { + struct ucode_ctrl ctrl = { .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -460,6 +478,8 @@ static bool ensure_cpus_are_online(void) return false; } } + /* Initialize the per CPU state */ + per_cpu(ucode_ctrl, cpu) = ctrl; } return true; } @@ -468,13 +488,13 @@ static int ucode_load_late_locked(void) { int ret; - if (!ensure_cpus_are_online()) + if (!ucode_setup_cpus()) return -EBUSY; ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); if (ret != UCODE_NEW) return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; - return microcode_reload_late(); + return ucode_load_late_stop_cpus(); } static ssize_t reload_store(struct device *dev, --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -16,6 +16,7 @@ enum ucode_state { UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, + UCODE_TIMEOUT, }; struct microcode_ops { From patchwork Thu Aug 10 18:37:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134187 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp641966vqi; Thu, 10 Aug 2023 12:38:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHZ9hgFBykk3S8lHZnEUJ2wMWSm8pvTehqpZ8ek24Lst8U/Mgv6RHWIsyyiaW2wMnRZu69A X-Received: by 2002:a17:902:d48a:b0:1b0:3ab6:5140 with SMTP id c10-20020a170902d48a00b001b03ab65140mr3741986plg.4.1691696281888; Thu, 10 Aug 2023 12:38:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691696281; cv=none; d=google.com; s=arc-20160816; b=PcOj/FWchKsJIOJaAkhUSiarib9tZkLPktoxK6XCCWP7vd4MYAqivGWHC1n7lYkJh7 lWEYRPEVZHqfaFKkANq+7ClZRq/N72ruzsOKQF45Ef//sCTLq7AAgBISBgT/uCrzGfTd 3cNMDQHGCvvDae0sNMMhTiTsCAHVxkPjgRwSmqS68LoEJ7i95LqFLiXQf5oFk46Si7bo fbXdxnyQS/SPuV1/jabnQDU0mcR9o4HP1NgjR4ilEUGvMSHSnOokAnxRnBOkSw2lxGde ScGpg6EM/1Xz5GJ92NQO3gsx3D5gmLwVmRo8n5EWNgclsoZmScRQQPIHyAqx1prtIwbF 66sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=cxNkz+vqZpI5dXtzaG1+R0H//409GWJPUy2opxP9bZOWDXYWBCsAkMV+m/EHe7yZ6p GrJK1f9i26Q9IjzaE10QyzC3K9NbZDs5LM4br8jH8vIGDw48F9hDSpc9DxpCwdTHaO3+ SOFXDUAyQF6NrlV6FLuOYSoSCEJF8EM0syBxuWXAkw15R3gZJEBFa1Z/nkM4I7+beoed XB8jFhA9xE8vn8XDbFXrt1YOU+nwvH9MAZctLU1mexVHEVFIDo3I0l3T6N9kJHlwYSon o9+YO/+Xu1SyDqLHvEDYhKIYCOlNrUeYnTYc+w/zAdW3QAR9zRMwzxiL04JZNxECo3si BuoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YwdxmrVI; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=j7AbLqrH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l3-20020a170902f68300b001aadba392c1si1996291plg.464.2023.08.10.12.37.46; Thu, 10 Aug 2023 12:38:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YwdxmrVI; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=j7AbLqrH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235311AbjHJSjP (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235996AbjHJSil (ORCPT ); Thu, 10 Aug 2023 14:38:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 175433A8D for ; Thu, 10 Aug 2023 11:38:19 -0700 (PDT) Message-ID: <20230810160806.222037973@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692679; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; b=YwdxmrVIawd2/tEOB/OcmWdiIdlO5T27/VUCnn1PqNODTt7cNKcTWe01bXLz3HAFwMHIgV iJMi4AU2Jhn9rCi+9Vf11m/Lky7rQDyC/ebdF9Zn+5ozAe7PrnDt4OUJCi/YrM7RjXtzdd Ual4qeE6canEBwI3tisTgNRCK4S1KXukxb8InWnrA7kREgQqvZBFUpr55hw+jidkU2AsDW H2pGqjWGlgA/ZHPj71jbX1t9xTr2HWnvXTJwSo8drxqoelxE0SW1OZL/WO7BjxPmkfwfwn 4+Ovf3iAwNJ/MhZQDW4IQYxzaJs6jaqDRHjLTEyUIQLaaKN9I+oNDCdj1eG0lg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692679; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gvgWHgk38J3qGADoq/3qmkZUlBXc3nLuAkYAzeigZSY=; b=j7AbLqrH79qZK7uB3sVUmkBzri0ksIZc28OGMFu266vzzyspGkosRR7aIePBmBMflTFEAS In77FyU3+1IiSBBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 22/30] x86/microcode: Add per CPU control field References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:58 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773872120423271677 X-GMAIL-MSGID: 1773872120423271677 From: Thomas Gleixner Add a per CPU control field to ucode_ctrl and define constants for it: SCTRL_WAIT indicates that the CPU needs to spinwait with timeout SCTRL_APPLY indicates that the CPU needs to invoke the microcode_apply() callback SCTRL_DONE indicates that the CPU can proceed without invoking the microcode_apply() callback. In theory this could be a global control field, but a global control does not cover the following case: 15 primary CPUs load microcode successfully 1 primary CPU fails and returns with an error code With global control the sibling of the failed CPU would either try again or the whole operation would be aborted with the consequence that the 15 siblings do not invoke the apply path and end up with inconsistent software state. The result in dmesg would be inconsistent too. There are two additional fields added and initialized: ctrl_cpu and secondaries. ctrl_cpu is the CPU number of the primary thread for now, but with the upcoming uniform loading at package or system scope this will be one CPU per package or just one CPU. Secondaries hands the control CPU a CPU mask which will be required to release the secondary CPUs out of the wait loop. Preparatory change for implementing a properly split control flow for primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,8 +324,16 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +enum sibling_ctrl { + SCTRL_WAIT, + SCTRL_APPLY, + SCTRL_DONE, +}; + struct ucode_ctrl { + enum sibling_ctrl ctrl; enum ucode_state result; + unsigned int ctrl_cpu; }; static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); @@ -468,7 +476,7 @@ static int ucode_load_late_stop_cpus(voi */ static bool ucode_setup_cpus(void) { - struct ucode_ctrl ctrl = { .result = -1, }; + struct ucode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -478,7 +486,15 @@ static bool ucode_setup_cpus(void) return false; } } - /* Initialize the per CPU state */ + + /* + * Initialize the per CPU state. This is core scope for now, + * but prepared to take package or system scope into account. + */ + if (topology_is_primary_thread(cpu)) + ctrl.ctrl_cpu = cpu; + else + ctrl.ctrl_cpu = cpumask_first(topology_sibling_cpumask(cpu)); per_cpu(ucode_ctrl, cpu) = ctrl; } return true; From patchwork Thu Aug 10 18:38:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp664883vqi; Thu, 10 Aug 2023 13:20:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFfZSIxt9V+9vDVkmsMPCNh/yIVlF1Kca/nHYhy671M/BMbMh+lh2d/c+YLsS1zzIUNloFy X-Received: by 2002:a05:6a21:a106:b0:140:a0dc:c834 with SMTP id aq6-20020a056a21a10600b00140a0dcc834mr89919pzc.24.1691698833105; Thu, 10 Aug 2023 13:20:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691698833; cv=none; d=google.com; s=arc-20160816; b=YrzJonv7nD+yCKfGiPfzWEKamlE0Bs1YZDcaLYAAwx3e2SiRjhXCKi9yVE74MssZHK MboGUx/ueMkbkPr1LGjAT2gP/F3CuqmD60IyGo2iTN77FRHc4mCccvYdvmBKE2iCBhYi qRE28ZNjBhKAeYYasIBtsgLguZP1TlRz/Lmx3pABOPb0Srym6JPSXoo5UqrCc17h5VqS Qxb70uhcNOacRNwnzNFstWCwvCsYcyDRG3LXdPC6YcDZFTqgxCd+p8zg1vQQriXL+7JH tba/mBeBBe0bFbI/RQGkWMrMWgp+VLYXsuLsf6uOIVWdXUovT23B7+vXMXY7cYnZWhRs NaSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=OUyiI3+SVR+dXUwfonGYLh32WqGBInCwbPLk26dnQuyOAi7FRtT7tQNXrYYzrYGEX/ KwM7Jrain+eZCii72wJ+p8POrwXKOOcmbSbd9fAqIimPQ/LN1roG2PipnyCHj9/pLPp0 u2rXteDX88Xm9GgUS2k0max2cG/3RMPMuHK7OgsV4GqHFZ50eyt6356N2kOZ+WuJRNLP s3K9ml/+3oEDYQH7/KBwjDQe6OpFKf894Mdw9Q4ap72yLOMWfWEV4DqMMJHwsE+tUMY6 S7IcPncFt+9hxmDQOw0+RdKUuzAIrYU79g/XOZHWfbBr0iRS86gY4FKiRfE9+99VWGH+ DNgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=BK8zvgyb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bk13-20020a056a02028d00b00565342e3c47si2115394pgb.501.2023.08.10.13.20.15; Thu, 10 Aug 2023 13:20:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=BK8zvgyb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236006AbjHJSjR (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235884AbjHJSis (ORCPT ); Thu, 10 Aug 2023 14:38:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 399AD3593 for ; Thu, 10 Aug 2023 11:38:21 -0700 (PDT) Message-ID: <20230810160806.278309863@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; b=BK8zvgybjP1VRz8owhKpmUoYJTaY2grbwTSp63RtJ0jjHrgah88eWcH2X2OAt++AkS597K LQ7KmkGrUVfCC0hnQkcwoqGPurswG0bT/4+f/C8eqMQxXqcPEi3PhKiwuFhGi72jwcl93f d6t+aEwD7fXSKl33KKCeAD48QMQHXpv9ObCIsooWtWm7W7fSkTzlqaiNgooNNrDrxw0/p7 vlO6uM2x9BGwQHWICw7kJY2cXJbGHPXRXYnA3quDVo6AZc0XtDDRxsWrLYUdEmVGs4NR5d 99zAVTDCJDb31c/DtHaVxptyrhI4pMQxYN/MNxNuK36wGmJdKy5bgHlVJxa7Xw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tcStbJBYGm1S6mX3lupmzFXgqW4kHxxe4AHt7jQaeKc=; b=Pef8bkf9YkrSQw6MIti7Z4Ea3arQVLoWmn6JV/mxbUiLzAyIiGcaY+xhpUdox206SY61F8 zlDbK7DGnrhGHiDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 23/30] x86/microcode: Provide new control functions References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:00 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773874795428910481 X-GMAIL-MSGID: 1773874795428910481 From: Thomas Gleixner The current all in one code is unreadable and really not suited for adding future features like uniform loading with package or system scope. Provide a set of new control functions which split the handling of the primary and secondary CPUs. These will replace the current rendevouz all in one function in the next step. This is intentionally a separate change because diff makes an complete unreadable mess otherwise. So the flow separates the primary and the secondary CPUs into their own functions, which use the control field in the per CPU ucode_ctrl struct. primary() secondary() wait_for_all() wait_for_all() apply_ucode() wait_for_release() release() apply_ucode() Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 86 +++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -357,6 +357,92 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } +static bool wait_for_ctrl(void) +{ + unsigned int timeout; + + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); + } + return false; +} + +static __maybe_unused void ucode_load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + /* Initial rendevouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return; + } + + /* + * Wait for primary threads to complete. If one of them hangs due + * to the update, there is no way out. This is non-recoverable + * because the CPU might hold locks or resources and confuse the + * scheduler, watchdogs etc. There is no way to safely evacuate the + * machine. + */ + if (!wait_for_ctrl()) + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + + /* + * If the primary succeeded then invoke the apply() callback, + * otherwise copy the state from the primary thread. + */ + if (this_cpu_read(ucode_ctrl.ctrl) == SCTRL_APPLY) + ret = microcode_ops->apply_microcode(cpu); + else + ret = per_cpu(ucode_ctrl.result, ctrl_cpu); + + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); +} + +static __maybe_unused void ucode_load_primary(unsigned int cpu) +{ + struct cpumask *secondaries = topology_sibling_cpumask(cpu); + enum sibling_ctrl ctrl; + enum ucode_state ret; + unsigned int sibling; + + /* Initial rendevouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + return; + } + + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + + /* + * If the update was successful, let the siblings run the apply() + * callback. If not, tell them it's done. This also covers the + * case where the CPU has uniform loading at package or system + * scope implemented but does not advertise it. + */ + if (ret == UCODE_UPDATED || ret == UCODE_OK) + ctrl = SCTRL_APPLY; + else + ctrl = SCTRL_DONE; + + for_each_cpu(sibling, secondaries) { + if (sibling != cpu) + per_cpu(ucode_ctrl.ctrl, sibling) = ctrl; + } +} + static int ucode_load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); From patchwork Thu Aug 10 18:38:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134196 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp647734vqi; Thu, 10 Aug 2023 12:50:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFpa3k0PaNXmOo7c6iLpI3ON8Ecs/fWiNRSEyemBqkwnpjwg9cROVZSpIz+JdNWSGs3FbMf X-Received: by 2002:ac2:5e2b:0:b0:4f8:5ab0:68c4 with SMTP id o11-20020ac25e2b000000b004f85ab068c4mr2178493lfg.59.1691697036598; Thu, 10 Aug 2023 12:50:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691697036; cv=none; d=google.com; s=arc-20160816; b=MJ81c/9YGlcpaOxJI34oKoX2EgsXyRxBm6z1Ad83pPnigAduPxCohAh5StbUPmNJyD zxVVr3f1GNTJww4XB/Xj3tof2832b1wnIdLkF4SNBjI2tkI7LyMRPsnN2IjYzklk8YiU /KuzGNgwo+umlzc3v/BQ2KFY9RFhk0jhWx5AsMPCFrouumDwaDAWUdJXAZ7g89xdAHJn pA3VQuhfivg2YRF9bWLIAZ1yI6A9tQifclAE5r+Ou7HuirUdCULAEud4jr66gfmKLjCr ji3/WtkIjXxv556KxMu/qg1oBl0yyL8xreVW5ADLsnAk14lchPk0Km2B5IGX95Am7bHk pLUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=Va6N3M6Yr7nPv1VxTwCUGXk6EsNzaMVI4f+y1Tpz0ol3WDHxmFOOPUzCc3CQRUA8Y5 3xjHcbmba/YO3ZS9WwR4Lloiq8AH53a/udJK+zB7lfLUtUbJKUJYoGf6kPktzx6OPFAY hiNPX7KYmJOC1M3LNNqL+cs9MLlZ+o3SSepvZiTJyav6w/ISUOUagYPcDp4tEqeO2giP 2q9/l8RxUSyFNTJPwzS/Dp/TD3mTJl6SSe6caeAnf81Nd8bhh08viJ7wBSh7IZYG2BwR haj3rLAEEGvlSeZiy9t1xOI5anD3/lrC8uTyWUJA7uZHp64GpAYIHZ1NczeVPSWoMGTL 4J0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=cHjg8Qth; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h12-20020a50ed8c000000b005233fa16a39si2045599edr.123.2023.08.10.12.50.13; Thu, 10 Aug 2023 12:50:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=cHjg8Qth; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235815AbjHJSjZ (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235627AbjHJSi7 (ORCPT ); Thu, 10 Aug 2023 14:38:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECBBE3A99 for ; Thu, 10 Aug 2023 11:38:24 -0700 (PDT) Message-ID: <20230810160806.335674426@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; b=cHjg8QthTSVTOfwEITGEyETVFB0t1CwQJ8m9sRkLw3T0b5maZiQYdXwp/dsj3Cl1BeZ9P3 1ikXUGnv+05gnoPkWsv5Y29ANYnNwSQBVJCp2xBofhgsuX9/DCUZZJ0CLAffFUNluClZBZ NqDK/iswRgJXk8UJEXHU5gJZv3+zbCHw1+BVc9WQ2MeHOFqHz71pssJEMi/AkdaV5xz5nJ vVAemGsuepKo0WRfEX6iqWu3K9x1/6sK5zl8ChZ6HDS4OMKAnK5OD4WPI4lAspR2W8cePQ KcqhikfHHetaGgpaDhWrre9S8HugJu8H4wfcFOodJFHdh63NSmvhU63u+R7tTA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tBiZyVFg2RByesw9s33ESky6BK8jMzTV8d/B5WDIvI8=; b=5MIJrm3DvfbIko5yI4LNpL2PwBahiCjQIRi28+gWAdks7ZhE2sBoozIuCcxzAj8/3/UjXi lsBpuEXO0lA81+AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 24/30] x86/microcode: Replace the all in one rendevouz handler References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:01 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773872911732358178 X-GMAIL-MSGID: 1773872911732358178 From: Thomas Gleixner with a new handler which just separates the control flow of primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 51 ++++++----------------------------- 1 file changed, 9 insertions(+), 42 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -337,7 +337,7 @@ struct ucode_ctrl { }; static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); -static atomic_t late_cpus_in, late_cpus_out; +static atomic_t late_cpus_in; static bool wait_for_cpus(atomic_t *cnt) { @@ -371,7 +371,7 @@ static bool wait_for_ctrl(void) return false; } -static __maybe_unused void ucode_load_secondary(unsigned int cpu) +static void ucode_load_secondary(unsigned int cpu) { unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); enum ucode_state ret; @@ -407,7 +407,7 @@ static __maybe_unused void ucode_load_se this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); } -static __maybe_unused void ucode_load_primary(unsigned int cpu) +static void ucode_load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -445,46 +445,14 @@ static __maybe_unused void ucode_load_pr static int ucode_load_cpus_stopped(void *unused) { - int cpu = smp_processor_id(); - enum ucode_state ret; - - /* - * Wait for all CPUs to arrive. A load will not be attempted unless all - * CPUs show up. - * */ - if (!wait_for_cpus(&late_cpus_in)) { - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return 0; - } - - /* - * On an SMT system, it suffices to load the microcode on one sibling of - * the core because the microcode engine is shared between the threads. - * Synchronization still needs to take place so that no concurrent - * loading attempts happen on multiple threads of an SMT core. See - * below. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - goto wait_for_siblings; + unsigned int cpu = smp_processor_id(); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); - -wait_for_siblings: - if (!wait_for_cpus(&late_cpus_out)) - panic("Timeout during microcode update!\n"); - - /* - * At least one thread has completed update on each core. - * For others, simply call the update to make sure the - * per-cpu cpuinfo can be updated with right microcode - * revision. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - return 0; + if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + ucode_load_primary(cpu); + else + ucode_load_secondary(cpu); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); + /* No point to wait here. The CPUs will all wait in stop_machine(). */ return 0; } @@ -498,7 +466,6 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); - atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Thu Aug 10 18:38:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134149 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp614123vqi; Thu, 10 Aug 2023 11:45:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFFKlwVw6U/2kbmylyL5ihnmGVNTbbVwqUtCYnwvEDUCCZq/2gGH4bChS1fHQcfVFgXB+5r X-Received: by 2002:a17:907:1dee:b0:98d:1f6a:fd47 with SMTP id og46-20020a1709071dee00b0098d1f6afd47mr2895439ejc.76.1691693109533; Thu, 10 Aug 2023 11:45:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691693109; cv=none; d=google.com; s=arc-20160816; b=JrkDLUcCsSjSvaap7y7gwFNkVwUE8Pu1LOmhjqOK770CLSMpp4fmdWVZAJHnya69kn G4zrijBM2q8yrEXiDkJkrv+VAwMdFbRkvo8NEofuJrigp1afmaZLco0b8vg6cKHf1Nu+ 5JxqIyh7b4ee5o/AdOQ6OUAwgAJCrTjO7r1LyNxxxU40X/vjiJ9vANiOCpcGBPJLEd8G olTjqE8Zl9YpK7aev10nz5yMhWUCzC5a+x8WrT20wuYHAdlyBl9YU2qqPD/ObRB0Ynv5 pJQMJMlo/ijjqKJt7kBGwaq9Zl3bVF7o1pFXqH9bXLupbR0faRSaiMXyVXsdAF3PjCg1 nDig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=U6Q/Iq8+DIojIyZFEw1VWVmhyDeuqbI0eLU8eGojt5M=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=ax8sgDE4xVYBCObeRyku0Cd0wzAl7ob9KT2RFuaGPZvUJFrTOjO+xL+XPNIfc7w6Pq dIGGG3eg4EJaQ5KhFv3RuSqkJPLnpyNnXAVdY/vutK+nIeQaFzXv73Wzi2NNVMiUHnvy GdlALJmDuMash+mxuY8JGx6KvZxYi5WYHbTN08OfaOTeHfJLx77kB2gH+YahhIuknw0E QYl6WyfK+H1Kl0YsJZybxHqgFif/Vbl42ZDEv8hQJDz3FCeNBLcAoidCaFnycf6+I53Z H+jCIXuT2DBYlYGde8IRf2Z79rKNJs1n1UztmP7Lwx3uDJSaTwKvgC0WVPaO2q42ivea AHCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=MX4tsTwk; dkim=neutral (no key) header.i=@linutronix.de header.b="5bPI/tfY"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id pw21-20020a17090720b500b0099298837776si1866905ejb.629.2023.08.10.11.44.41; Thu, 10 Aug 2023 11:45:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=MX4tsTwk; dkim=neutral (no key) header.i=@linutronix.de header.b="5bPI/tfY"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235924AbjHJSj2 (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235750AbjHJSjB (ORCPT ); Thu, 10 Aug 2023 14:39:01 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0A432D57 for ; Thu, 10 Aug 2023 11:38:29 -0700 (PDT) Message-ID: <20230810160806.391887806@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=U6Q/Iq8+DIojIyZFEw1VWVmhyDeuqbI0eLU8eGojt5M=; b=MX4tsTwk1iKTOdT3hHt/FFPLZ1KJXE89rgzIrWWzPOscnT3IGW6Y9WPD4hYxTXVuoWU/K9 a5SFwlhqyDnENmvcpC3KETFmzM7JaPncRwsIMn/745kFMU0vRtXiOjwT1Ao9tABpQAQK+Q 4YcZn9dpuKHQoY6sh1HZ167rjL0vysZyLm2Qm5eNd7t4GFVWt6mJVyUoSFOdOO2IctR63V V6U9qKHSGSFYjqmODBCxvaTitRh21wiWjFm0DEYJI2HWdTfpr2BMokbgZtdKGwsR1rUypb TZviRLstl5TwE51NMZveGLgYaemdhYgM4br4UI0RvDqOXaoBxPvi0vSE+pTJRg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=U6Q/Iq8+DIojIyZFEw1VWVmhyDeuqbI0eLU8eGojt5M=; b=5bPI/tfYNRqWnxgsMO3Kha9gRvcDmt/WRprqS3mgs56kiKRg+iGAkq2egJ9QwJc8jCjf+i gZ1gQ3fbYX1GcjAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 25/30] x86/microcode: Rendezvous and load in NMI References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:03 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773868793844742484 X-GMAIL-MSGID: 1773868793844742484 From: Thomas Gleixner stop_machine() does not prevent the spin-waiting sibling from handling an NMI, which is obviously violating the whole concept of rendezvous. Implement a static branch right in the beginning of the NMI handler which is NOOPed except when enabled by the late loading mechanism. The later loader enables the static branch before stop_machine() is invoked. Each CPU has an nmi_enable in its control structure which indicates whether the CPU should go into the update routine. This is required to bridge the gap between enabling the branch and actually being at the point where it makes sense. Each CPU which arrives in the stopper thread function sets that flag and issues a self NMI right after that. If the NMI function sees the flag clear, it returns. If it's set it clears the flag and enters the rendezvous. This is safe against a real NMI which hits in between setting the flag and sending the NMI to itself. The real NMI will be swallowed by the microcode update and the self NMI will then let stuff continue. Otherwise this would end up with a spurious NMI. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 12 ++++++++ arch/x86/kernel/cpu/microcode/core.c | 42 ++++++++++++++++++++++++++++--- arch/x86/kernel/cpu/microcode/intel.c | 1 arch/x86/kernel/cpu/microcode/internal.h | 3 +- arch/x86/kernel/nmi.c | 4 ++ 5 files changed, 57 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -78,4 +78,16 @@ void show_ucode_info_early(void); static inline void show_ucode_info_early(void) { } #endif /* !CONFIG_CPU_SUP_INTEL */ +bool microcode_nmi_handler(void); + +#ifdef CONFIG_MICROCODE_LATE_LOADING +DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); +static __always_inline bool microcode_nmi_handler_enabled(void) +{ + return static_branch_unlikely(µcode_nmi_handler_enable); +} +#else +static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } +#endif + #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include +#include #include #include #include @@ -334,8 +336,10 @@ struct ucode_ctrl { enum sibling_ctrl ctrl; enum ucode_state result; unsigned int ctrl_cpu; + bool nmi_enabled; }; +DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); static atomic_t late_cpus_in; @@ -349,7 +353,8 @@ static bool wait_for_cpus(atomic_t *cnt) if (!atomic_read(cnt)) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } /* Prevent the late comers to make progress and let them time out */ @@ -365,7 +370,8 @@ static bool wait_for_ctrl(void) if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } return false; @@ -443,7 +449,7 @@ static void ucode_load_primary(unsigned } } -static int ucode_load_cpus_stopped(void *unused) +static bool microcode_update_handler(void) { unsigned int cpu = smp_processor_id(); @@ -452,7 +458,29 @@ static int ucode_load_cpus_stopped(void else ucode_load_secondary(cpu); - /* No point to wait here. The CPUs will all wait in stop_machine(). */ + touch_nmi_watchdog(); + return true; +} + +bool microcode_nmi_handler(void) +{ + if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + return false; + + this_cpu_write(ucode_ctrl.nmi_enabled, false); + return microcode_update_handler(); +} + +static int ucode_load_cpus_stopped(void *unused) +{ + if (microcode_ops->use_nmi) { + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + } else { + /* Just invoke the handler directly */ + microcode_update_handler(); + } return 0; } @@ -473,8 +501,14 @@ static int ucode_load_late_stop_cpus(voi */ store_cpu_caps(&prev_info); + if (microcode_ops->use_nmi) + static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + stop_machine_cpuslocked(ucode_load_cpus_stopped, NULL, cpu_online_mask); + if (microcode_ops->use_nmi) + static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { switch (per_cpu(ucode_ctrl.result, cpu)) { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -698,6 +698,7 @@ static struct microcode_ops microcode_in .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, + .use_nmi = IS_ENABLED(CONFIG_X86_64), }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,7 +31,8 @@ struct microcode_ops { enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); - unsigned int nmi_safe : 1; + unsigned int nmi_safe : 1, + use_nmi : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -343,6 +344,9 @@ static noinstr void default_do_nmi(struc instrumentation_begin(); + if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) + goto out; + handled = nmi_handle(NMI_LOCAL, regs); __this_cpu_add(nmi_stats.normal, handled); if (handled) { From patchwork Thu Aug 10 18:38:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134163 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp627235vqi; Thu, 10 Aug 2023 12:09:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEwzfvAw150pWjb9U1TkSPKAm1HnZZ0Gzv7bBLarnLXnhYpo4wSYiBXoX2qTNJi7pSXZ4HT X-Received: by 2002:a05:6a20:3c8a:b0:13d:7432:ed63 with SMTP id b10-20020a056a203c8a00b0013d7432ed63mr3803251pzj.8.1691694563686; Thu, 10 Aug 2023 12:09:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691694563; cv=none; d=google.com; s=arc-20160816; b=fvii+Kd2hkKWWsYiCNzdZfUvpFn9okFLm9f4UNqvxjbA+QnUuA6VSAWWW1TiQ2Vx0o Mt8G4Zf/CoMxgJRnGRWvOI8oeeaeDCqRwutLesN+OIpsOmHp5fxydXYW2V2YNksyhP0o D+okRLPK720MXFZPUvOzk5w+0S6tC5aq/vYEYYqW8l+6zQQA/1F/tjfTcHNiAUaDANqv 5WsqsC1WOZlSxl8THh2kwqSzHF2bgeKWWvY4cJ+PH4muRwGK8NQ/noXidQBgAaRbTSPD igaLq93TBfO5hARGy2AaYGzDqMsVgris2rA12KdmTntw3bqegGFlxhapzyzPLRi9bY+d Hi7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=POJRl7gnDifJX3Op+Oih89hPO2f1i7lhi58ZHatrrsn05j+23kBMpRuIaaqc+Xh1Q9 sc23cYMJjSK/wouo8d8npF3nf7pzQ5onjYL7s30RXFtnY+XkKxwncoVridRkxosS9qlK 3caNBKyRQ5+j12GipZjMcC1hC5RDUbicKMf7c4q0B/996R5/mRpIGQ+5uc5/B/JFEQOH 2sspOs+cqzz3XLBYL3K+4pAvtIIiIrIl04jpngi/2weMrMwzlqcnTjqJdpI97U6NHT7o GfHldKoTmNlysmE7o0NLT1WdmdNVfC+dc53hgRrOjG5swgeMjlIdlbmcWJ20bsfxN6/c K7Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UoMEb13z; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p4-20020a63c144000000b00563e747d762si1989336pgi.545.2023.08.10.12.09.10; Thu, 10 Aug 2023 12:09:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UoMEb13z; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235980AbjHJSjE (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235981AbjHJSih (ORCPT ); Thu, 10 Aug 2023 14:38:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CAB930EE for ; Thu, 10 Aug 2023 11:38:13 -0700 (PDT) Message-ID: <20230810160806.448579267@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; b=UoMEb13z1iIfcG1HxMNULfGgCW7G8+4pEeVO4MIwtPOtKO1aeU3hk5835cOR+dqrXPVoKa ZNdB2wY9FXyO1xTTp2X+6pt31zF6iMeyf+eh0N347ZbZymXkrJDVDhs9K9XlQI6HvP7khf DivoRtMU690pNx0Zd77q4YSnPDQwshVY3r0AVGYo80HtpEUGK/dwMp8ovgrOpCTqwEJDMH KAne6ggysiy/CfOi1x0HbtBqqNWP9QnLs9ZBLa4SJyN37MO3oEXH83Fou/seJFdP3fU6Bq /Ct7JTuYHEz7frojIPNKMi4nSVD2KobC75Lo6v1qjeR8IjF3BT6aYRJ1jbHURQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OBavvuIISB6T38J3QGPcFo0zGeBzWsPn/MsQxWfrjc4=; b=NThdgOj0hzdmLQU5HH/sOIdU4tN+LxK4eizs1XjMH12ptzdvuAezr+YcdW7gX0199RnR+T c5MBpQD74Iyxt3Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 26/30] x86/microcode: Protect against instrumentation References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:04 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870318866736753 X-GMAIL-MSGID: 1773870318866736753 From: Thomas Gleixner The wait for control loop in which the siblings are waiting for the microcode update on the primary thread must be protected against instrumentation as instrumentation can end up in #INT3, #DB or #PF, which then returns with IRET. That IRET reenables NMI which is the opposite of what the NMI rendezvouz is trying to achieve. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 112 ++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 28 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -341,53 +341,65 @@ struct ucode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); +static unsigned int loops_per_usec; static atomic_t late_cpus_in; -static bool wait_for_cpus(atomic_t *cnt) +static noinstr bool wait_for_cpus(atomic_t *cnt) { - unsigned int timeout; + unsigned int timeout, loops; - WARN_ON_ONCE(atomic_dec_return(cnt) < 0); + WARN_ON_ONCE(raw_atomic_dec_return(cnt) < 0); for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (!atomic_read(cnt)) + if (!raw_atomic_read(cnt)) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % 1000)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } /* Prevent the late comers to make progress and let them time out */ - atomic_inc(cnt); + raw_atomic_inc(cnt); return false; } -static bool wait_for_ctrl(void) +static noinstr bool wait_for_ctrl(void) { - unsigned int timeout; + unsigned int timeout, loops; for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + if (raw_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % 1000)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } return false; } -static void ucode_load_secondary(unsigned int cpu) +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr bool ucode_load_secondary_wait(unsigned int ctrl_cpu) { - unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); - enum ucode_state ret; - /* Initial rendevouz to ensure that all CPUs have arrived */ if (!wait_for_cpus(&late_cpus_in)) { - pr_err_once("Microcode load: %d CPUs timed out\n", - atomic_read(&late_cpus_in) - 1); this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return; + return false; } /* @@ -397,9 +409,33 @@ static void ucode_load_secondary(unsigne * scheduler, watchdogs etc. There is no way to safely evacuate the * machine. */ - if (!wait_for_ctrl()) - panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + if (wait_for_ctrl()) + return true; + + instrumentation_begin(); + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + instrumentation_end(); +} +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr void ucode_load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = raw_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + if (!ucode_load_secondary_wait(ctrl_cpu)) { + instrumentation_begin(); + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + instrumentation_end(); + return; + } + + /* Primary thread completed. Allow to invoke instrumentable code */ + instrumentation_begin(); /* * If the primary succeeded then invoke the apply() callback, * otherwise copy the state from the primary thread. @@ -411,6 +447,7 @@ static void ucode_load_secondary(unsigne this_cpu_write(ucode_ctrl.result, ret); this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + instrumentation_end(); } static void ucode_load_primary(unsigned int cpu) @@ -449,25 +486,43 @@ static void ucode_load_primary(unsigned } } -static bool microcode_update_handler(void) +static noinstr bool microcode_update_handler(void) { - unsigned int cpu = smp_processor_id(); + unsigned int cpu = raw_smp_processor_id(); - if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + if (raw_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) { + instrumentation_begin(); ucode_load_primary(cpu); - else + instrumentation_end(); + } else { ucode_load_secondary(cpu); + } + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + return true; } -bool microcode_nmi_handler(void) +/* + * Protection against instrumentation is required for CPUs which are not + * safe against an NMI which is delivered to the secondary SMT sibling + * while the primary thread updates the microcode. Instrumentation can end + * up in #INT3, #DB and #PF. The IRET from those exceptions reenables NMI + * which is the opposite of what the NMI rendevouz is trying to achieve. + * + * The primary thread is safe versus instrumentation as the actual + * microcode update handles this correctly. It's only the sibling code + * path which must be NMI safe until the primary thread completed the + * update. + */ +bool noinstr microcode_nmi_handler(void) { - if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) return false; - this_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.nmi_enabled, false); return microcode_update_handler(); } @@ -494,6 +549,7 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* * Take a snapshot before the microcode update in order to compare and From patchwork Thu Aug 10 18:38:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134171 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp632536vqi; Thu, 10 Aug 2023 12:18:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF5bpAQ+6mGHflj0pA56Bl2s8I79gelBKG6iVhKdYkv9C8wgKF3FNkqnhtY0oDmRDF9C9rj X-Received: by 2002:a05:6a20:7fa9:b0:13e:23bc:f4cc with SMTP id d41-20020a056a207fa900b0013e23bcf4ccmr4431268pzj.37.1691695118613; Thu, 10 Aug 2023 12:18:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691695118; cv=none; d=google.com; s=arc-20160816; b=O0VSqlnzDe4S11jSqg8QepK0jCPmtDMy1i5Ut9D19/Ay0F8y06MQficVe0FvPptZbG 8dzwyWMtrXMYjiQ0kx5ibl98kAex3nINk2Utr5tw2ej34owHe2Yg4B0h+FbkM5ertkra riKftcwRK7rgmuP8aM2GGMAAaidQEbjTCuAKgUPdAEFjr5PKcZI6mbYv3k1Xhm2Yrmhb AqOqy3goH1O9FKUt0kLbUrm3IOb4FGU0ePaoV+IV3eA695Wb3bUrJZPMrCmUK9njfnv3 9dBYUOFLRSUPSojAXCSwKEcutKy6iF8ErgO5S3NQrGyhoeOv5qrpIAzHXeghQuF/Tl0D xSUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=KXmWi+498NlTG+8QbtY9G0BWF4sNUEz4Qvdk7zq0Ox4=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=BqCi2IVLJwd7vWpREsSy4/mDoGL4CVBFO6MIJESWvP/LFN670SczvNYCMQ864Mfi6H ZoXe9rV9ZLMByVYysGjwqf/SQ+7NcmaciUSw1j+gZPD83VpEtWWFJ7N7qxS3E5ZzkfLU 0l3FEs+Bn4wSZhwTKAyErnwNZLarkatXjkqIo05+PMmsBIkwKaEK5sCuJS+7wE9kES/s 30hd0UuQQaHmA30DzdIistc6/6asAut5r+snFme/PttuNwv89NETXKi10iy3V05OGfev eadr2b5OignD7saG2mnfvhEhJ3vCBGvPMKvJWaZ/a0nUSZpt2aHvFo99nafn9Hi7Abpv W7Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=2yfFPqVq; dkim=neutral (no key) header.i=@linutronix.de header.b=MYXcUVgo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t70-20020a638149000000b005579d6bdf7esi1957542pgd.856.2023.08.10.12.18.02; Thu, 10 Aug 2023 12:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=2yfFPqVq; dkim=neutral (no key) header.i=@linutronix.de header.b=MYXcUVgo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235987AbjHJSji (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235958AbjHJSjM (ORCPT ); Thu, 10 Aug 2023 14:39:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F2D3AB7 for ; Thu, 10 Aug 2023 11:38:35 -0700 (PDT) Message-ID: <20230810160806.506010083@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KXmWi+498NlTG+8QbtY9G0BWF4sNUEz4Qvdk7zq0Ox4=; b=2yfFPqVqwC1UiB2xLp4JD4uI//CEWRSXljATSIrPMMRU9OCUMS3NKxgEnWpp+sNqTy7BYN WN35mdONac/s+MlFJGRw34qku9KLT58+vfjJ9ul9OwWrx5UpOGLKGyfkXb8xkPQyJaCNkD GfcKWv4DIpaLlD/CWcJKtvdHssdU2yJvFF+tMYmXEDeOWmGhSzySpKKK93XLdioBUzCNJ/ JwiEp6HQ3KsI5iV1ek5McY5nUMHJP76z6aYBAJ/4Rarsj6w91nbS3kRzi6A3O8wjCzDw2U j9m3FUpcE4qCaCywul71XanbvrNIuNZWcSTS+kTfRQQo+1/j9zpPCiUDPg3liw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KXmWi+498NlTG+8QbtY9G0BWF4sNUEz4Qvdk7zq0Ox4=; b=MYXcUVgor8U2LoMdsSSnv3y9xcLW/xFpVjjRNP88uPjFXxta9KQ6qcWlaWn6e08c32ZVJx zO3m/y0HiW5DwmCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 27/30] x86/apic: Provide apic_force_nmi_on_cpu() References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:06 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870900928273073 X-GMAIL-MSGID: 1773870900928273073 From: Thomas Gleixner When SMT siblings are soft-offlined and parked in one of the play_dead() variants they still react on NMI, which is problematic on affected Intel CPUs. The default play_dead() variant uses MWAIT on modern CPUs, which is not guaranteed to be safe when updated concurrently. Right now late loading is prevented when not all SMT siblings are online, but as they still react on NMI, it is possible to bring them out of their park position into a trivial rendevouz handler. Provide a function which allows to do that. I does sanity checks whether the target is in the cpus_booted_once_mask and whether the APIC driver supports it. Mark X2APIC and XAPIC as capable, but exclude 32bit and the UV and NUMACHIP variants as that needs feedback from the relevant experts. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 +++++ arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/ipi.c | 9 ++++++++- arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + 5 files changed, 17 insertions(+), 1 deletion(-) --- diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 98c32aa5963a..e219e6c62138 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -301,6 +301,9 @@ struct apic { enum apic_delivery_modes delivery_mode; bool dest_mode_logical; + /* Allows to send an NMI to an "offline" CPU which hangs in *play_dead() */ + bool nmi_to_offline_cpu; + u32 (*calc_dest_apicid)(unsigned int cpu); /* ICR related functions */ @@ -505,6 +508,8 @@ extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *r extern int default_cpu_present_to_apicid(int mps_cpu); extern int default_check_phys_apicid_present(int phys_apicid); +void apic_send_nmi_to_offline_cpu(unsigned int cpu); + #endif /* CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_SMP diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c index 8f72b4351c9f..4340f471e6a6 100644 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -138,6 +138,7 @@ static struct apic apic_flat __ro_after_init = { .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = default_inquire_remote_apic, @@ -229,6 +230,7 @@ static struct apic apic_physflat __ro_after_init = { .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = default_inquire_remote_apic, diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 2a6509e8c840..6ee6cce4423a 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -95,8 +95,15 @@ void native_send_call_func_ipi(const struct cpumask *mask) apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } +void apic_send_nmi_to_offline_cpu(unsigned int cpu) +{ + if (WARN_ON_ONCE(!apic->nmi_to_offline_cpu)) + return; + if (WARN_ON_ONCE(!cpumask_test_cpu(cpu, &cpus_booted_once_mask))) + return; + apic->send_IPI(cpu, NMI_VECTOR); +} #endif /* CONFIG_SMP */ - static inline int __prepare_ICR2(unsigned int mask) { return SET_XAPIC_DEST_FIELD(mask); diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c index b2b2b7f3e03f..685437a98463 100644 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -264,6 +264,7 @@ static struct apic apic_x2apic_cluster __ro_after_init = { .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = NULL, diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 896bc41cb2ba..d5e44cb7e15f 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -188,6 +188,7 @@ static struct apic apic_x2apic_phys __ro_after_init = { .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .inquire_remote_apic = NULL, From patchwork Thu Aug 10 18:38:07 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y8-20020a17090264c800b001a99b9d767csi1843727pli.166.2023.08.10.12.16.23; Thu, 10 Aug 2023 12:16:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=s3LYbmCZ; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235884AbjHJSjk (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236062AbjHJSjO (ORCPT ); Thu, 10 Aug 2023 14:39:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4292C35A2 for ; Thu, 10 Aug 2023 11:38:38 -0700 (PDT) Message-ID: <20230810160806.562016788@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Hn+I0jWNRcrSAQ6j91XI3AhzctFZihPnBqZSW4sFnhs=; b=s3LYbmCZCWV/aebU6xsyzw+cST03tzghgZ5v90gdRerNahKEKkKhTNkJ9RxfP6760dQIzj aXg3kB/Bn0q/F0qk2E4L3QscarxOIlUgj+RBiH//yUDftIkzUd+azUXfrZfo5lOJuJqnG6 OXgGTNvmcB2eyJZLEaaeAssa/CCIK+3Xro0j28dXyA2X3EJP7EsOBPrJ3KFnCQ9iq9pNrn gfm/LEXdkSHz1LcDxqEcfzqb3Vm0fNtrgXFoT47Whs/RkgdPSgmqfuCsgjCzhb0NX5QEUf UpxgE9F9xsHdzXYLI+DnmD4X1LLs+2kAz/pp0LN38JdmGI77bTmQ3YPqegg7xA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Hn+I0jWNRcrSAQ6j91XI3AhzctFZihPnBqZSW4sFnhs=; b=X7faGnpZCRNEZtdmFVSQ0Dj38oAWkRV1imL/i/mZP2gCLzHoE3TwmrOfLbZCJbHeAJnIrD 0TznnJbC6dE9vGAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 28/30] x86/microcode: Handle "offline" CPUs correctly References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:07 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870774278620855 X-GMAIL-MSGID: 1773870774278620855 From: Thomas Gleixner Offline CPUs need to be parked in a safe loop when microcode update is in progress on the primary CPU. Currently offline CPUs are parked in 'mwait_play_dead()', and for Intel CPUs, its not a safe instruction, because 'mwait' instruction can be patched in the new microcode update that can cause instability. - Adds a new microcode state 'UCODE_OFFLINE' to report status on per-cpu basis. - Force NMI on the offline CPUs. Wakeup offline CPUs while the update is in progress and then return them back to 'mwait_play_dead()' after microcode update is complete. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 1 arch/x86/kernel/cpu/microcode/core.c | 112 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 1 arch/x86/kernel/nmi.c | 5 + 4 files changed, 113 insertions(+), 6 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -79,6 +79,7 @@ static inline void show_ucode_info_early #endif /* !CONFIG_CPU_SUP_INTEL */ bool microcode_nmi_handler(void); +void microcode_offline_nmi_handler(void); #ifdef CONFIG_MICROCODE_LATE_LOADING DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -341,8 +341,9 @@ struct ucode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct ucode_ctrl, ucode_ctrl); +static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; -static atomic_t late_cpus_in; +static cpumask_t cpu_offline_mask; static noinstr bool wait_for_cpus(atomic_t *cnt) { @@ -450,7 +451,7 @@ static noinstr void ucode_load_secondary instrumentation_end(); } -static void ucode_load_primary(unsigned int cpu) +static void __ucode_load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -486,6 +487,67 @@ static void ucode_load_primary(unsigned } } +static bool ucode_kick_offline_cpus(unsigned int nr_offl) +{ + unsigned int cpu, timeout; + + for_each_cpu(cpu, &cpu_offline_mask) { + /* Enable the rendevouz handler and send NMI */ + per_cpu(ucode_ctrl.nmi_enabled, cpu) = true; + apic_send_nmi_to_offline_cpu(cpu); + } + + /* Wait for them to arrive */ + for (timeout = 0; timeout < (USEC_PER_SEC / 2); timeout++) { + if (atomic_read(&offline_in_nmi) == nr_offl) + return true; + udelay(1); + } + /* Let the others time out */ + return false; +} + +static void ucode_release_offline_cpus(void) +{ + unsigned int cpu; + + for_each_cpu(cpu, &cpu_offline_mask) + per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE; +} + +static void ucode_load_primary(unsigned int cpu) +{ + unsigned int nr_offl = cpumask_weight(&cpu_offline_mask); + bool proceed = true; + + /* Kick soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + proceed = ucode_kick_offline_cpus(nr_offl); + + /* If the soft-offlined CPUs did not respond, abort */ + if (proceed) + __ucode_load_primary(cpu); + + /* Unconditionally release soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + ucode_release_offline_cpus(); +} + +/* + * Minimal stub rendevouz handler for soft-offlined CPUs which participate + * in the NMI rendevouz to protect against a concurrent NMI on affected + * CPUs. + */ +void noinstr microcode_offline_nmi_handler(void) +{ + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) + return; + raw_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.result, UCODE_OFFLINE); + raw_atomic_inc(&offline_in_nmi); + wait_for_ctrl(); +} + static noinstr bool microcode_update_handler(void) { unsigned int cpu = raw_smp_processor_id(); @@ -542,6 +604,7 @@ static int ucode_load_cpus_stopped(void static int ucode_load_late_stop_cpus(void) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; @@ -549,6 +612,7 @@ static int ucode_load_late_stop_cpus(voi pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&offline_in_nmi, 0); loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* @@ -571,6 +635,7 @@ static int ucode_load_late_stop_cpus(voi case UCODE_UPDATED: updated++; break; case UCODE_TIMEOUT: timedout++; break; case UCODE_OK: siblings++; break; + case UCODE_OFFLINE: offline++; break; default: failed++; break; } } @@ -582,6 +647,13 @@ static int ucode_load_late_stop_cpus(voi /* Nothing changed. */ if (!failed && !timedout) return 0; + + nr_offl = cpumask_weight(&cpu_offline_mask); + if (offline < nr_offl) { + pr_warn("%u offline siblings did not respond.\n", + nr_offl - atomic_read(&offline_in_nmi)); + return -EIO; + } pr_err("Microcode update failed: %u CPUs failed %u CPUs timed out\n", failed, timedout); return -EIO; @@ -615,19 +687,49 @@ static int ucode_load_late_stop_cpus(voi * modern CPUs is using MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. * - * 2) Initialize the per CPU control structure + * As soft-offlined CPUs still react on NMIs, the SMT sibling + * restriction can be lifted when the vendor driver signals to use NMI + * for rendevouz and the APIC provides a mechanism to send an NMI to a + * soft-offlined CPU. The soft-offlined CPUs are then able to + * participate in the rendezvouz in a trivial stub handler. + * + * 2) Initialize the per CPU control structure and create a cpumask + * which contains "offline"; secondary threads, so they can be handled + * correctly by a control CPU. */ static bool ucode_setup_cpus(void) { struct ucode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; + bool allow_smt_offline; unsigned int cpu; + allow_smt_offline = microcode_ops->nmi_safe || + (microcode_ops->use_nmi && apic->nmi_to_offline_cpu); + + cpumask_clear(&cpu_offline_mask); + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + /* + * Offline CPUs sit in one of the play_dead() functions + * with interrupts disabled, but they still react on NMIs + * and execute arbitrary code. Also MWAIT being updated + * while the offline CPU sits there is not necessarily safe + * on all CPU variants. + * + * Mark them in the offline_cpus mask which will be handled + * by CPU0 later in the update process. + * + * Ensure that the primary thread is online so that it is + * guaranteed that all cores are updated. + */ if (!cpu_online(cpu)) { - if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { - pr_err("CPU %u not online\n", cpu); + if (topology_is_primary_thread(cpu) || !allow_smt_offline) { + pr_err("CPU %u not online, loading aborted\n", cpu); return false; } + cpumask_set_cpu(cpu, &cpu_offline_mask); + per_cpu(ucode_ctrl, cpu) = ctrl; + continue; } /* --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -17,6 +17,7 @@ enum ucode_state { UCODE_NFOUND, UCODE_ERROR, UCODE_TIMEOUT, + UCODE_OFFLINE, }; struct microcode_ops { --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -502,8 +502,11 @@ DEFINE_IDTENTRY_RAW(exc_nmi) if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) raw_atomic_long_inc(&nsp->idt_calls); - if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) + if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) { + if (microcode_nmi_handler_enabled()) + microcode_offline_nmi_handler(); return; + } if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { this_cpu_write(nmi_state, NMI_LATCHED); From patchwork Thu Aug 10 18:38:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp672807vqi; Thu, 10 Aug 2023 13:35:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFeIefn/0j3VdeMmaMmtVBlXpF74aBeJf+Fi7oDwIFx9n21bwH429hCt254E8hcWmft0xht X-Received: by 2002:a05:6a21:9997:b0:134:9f4e:623f with SMTP id ve23-20020a056a21999700b001349f4e623fmr132962pzb.14.1691699738464; Thu, 10 Aug 2023 13:35:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691699738; cv=none; d=google.com; s=arc-20160816; b=LyzSyeg+d8Um7CrzwMxI0K8zQWpsGZYYW/eiS5HdXwSyu0mxkvdSymb4rkPJajS2t3 05447hDkMF5TAhKCCO4b7TX3VyBJ/YBB5CQhdp5C3f1x8v/RCNKxxeaEZ10iaPWU7t9T ux+ZcRg04Tn8wVuFq8/QVVriS1/SLikxCJ1aEAcb19/pgBtnNY+CVIUEnyZTEoelzJLW qWanLeUNuX7pNbKUWS0kmhVMvwz7PCdwXiHZrqA/MuChscVTzKKBIekXFKlRbiEG0GJb MnuUNCefbbbs6XptwHocDvOxqBx9owqbF2Np2kF+fV4GnJn2s/Kqd4o0e/vazC105LVR xJMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Z7KbmMx78RiCnQSNzQlpS4iiGDKDv18v+/y7YeQCrsU=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=zCpHk+27UB3k1QBB+jLHwJaRYwgdENQVKTvB1A3/1SMEC4eP7brm02oqpik6ntQT3i SIKfRTpF0Ovja1ljonSLAt6yforsA+zmUKpQZcPEx6vLGfd6AO7vtwiTo0p9kLAo5riG udDpZfVrSKY/HYNK6BSAArpyZNoSRkJBMXmKcVxciNYjXNvI+SUqaB6Ha/E/MyxKheHN 4hcmHeiBrAaSJzOVDwruiVsUgJ8XTo19SUMN/jjwPBFFP4QtsEHm4dqn+b0O1PFqReH7 juWWfi865mJl3Ty9D+G94oanJCVOkhlTpz24qxib3subXWb75Z/x//X2AdUUA0FovcnR 8rBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=QB7+Fc9k; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b10-20020a170903228a00b001bb993ef74dsi2028603plh.461.2023.08.10.13.35.25; Thu, 10 Aug 2023 13:35:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=QB7+Fc9k; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235776AbjHJSjN (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235787AbjHJSij (ORCPT ); Thu, 10 Aug 2023 14:38:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25AAB30FD for ; Thu, 10 Aug 2023 11:38:15 -0700 (PDT) Message-ID: <20230810160806.617422055@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692689; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Z7KbmMx78RiCnQSNzQlpS4iiGDKDv18v+/y7YeQCrsU=; b=QB7+Fc9kIrbu0Z8GI3SDZ7NrDKsg+b0E+BaX+vlaIzDril5hto000netPXJN7Gtvop5xeu Q7+WME3gTAZPBq5or9PInDY6O9O6dgVI0eK6EeMU8peJMhSF00ZNRLbHgllWKovEXkhBDV KvEnbq0EU/7DUGBH3MOP9I3rVOu9jw8umYSEeK4sWc7+mndMUFutjlKhlun7tt9STJeQOZ XWepnJtN9pYjryo+cA5oerSpyiLYnB74kUzEP8/U0YxoiuR4j1LmLL02Q8GO+GEP21fNyI hbMghh7/3P/bpQ17pXzP/nISU0mNED35rtjmkTM23lQbtjkgK4pvtuhisNY9/g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692689; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Z7KbmMx78RiCnQSNzQlpS4iiGDKDv18v+/y7YeQCrsU=; b=LpNecU2mZ8qtOXfQKZElHFCbw71CsKIFiJkBu3CIfqa24bLiMfQVcfXr0PO61yoYRYKLY6 orntZrRKgKTqdNDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 29/30] x86/microcode: Prepare for minimal revision check References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:09 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773875745104377566 X-GMAIL-MSGID: 1773875745104377566 From: Thomas Gleixner Applying microcode late can be fatal for the running kernel when the update changes functionality which is in use already in a non-compatible way, e.g. by removing a CPUID bit. There is no way for admins which do not have access to the vendors deep technical support to decide whether late loading of such a microcode is safe or not. Intel has added a new field to the microcode header which tells the minimal microcode revision which is required to be active in the CPU in order to be safe. Provide infrastructure for handling this in the core code and a command line switch which allows to enforce it. If the update is considered safe the kernel is not tainted and the annoying warning message not emitted. If it's enforced and the currently loaded microcode revision is not safe for late loading then the load is aborted. Signed-off-by: Thomas Gleixner --- Documentation/admin-guide/kernel-parameters.txt | 5 ++++ arch/x86/Kconfig | 23 ++++++++++++++++++- arch/x86/kernel/cpu/microcode/amd.c | 3 ++ arch/x86/kernel/cpu/microcode/core.c | 29 ++++++++++++++++++------ arch/x86/kernel/cpu/microcode/intel.c | 3 ++ arch/x86/kernel/cpu/microcode/internal.h | 3 ++ 6 files changed, 58 insertions(+), 8 deletions(-) --- --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3239,6 +3239,11 @@ mga= [HW,DRM] + microcode.force_minrev= [X86] + Format: + Enable or disable the microcode minimal revision + enforcement for the runtime microcode loader. + min_addr=nn[KMG] [KNL,BOOT,IA-64] All physical memory below this physical address is ignored. --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1320,7 +1320,28 @@ config MICROCODE_LATE_LOADING is a tricky business and should be avoided if possible. Just the sequence of synchronizing all cores and SMT threads is one fragile dance which does not guarantee that cores might not softlock after the loading. Therefore, - use this at your own risk. Late loading taints the kernel too. + use this at your own risk. Late loading taints the kernel unless the + microcode header indicates that it is safe for late loading via the + minimal revision check. This minimal revision check can be enforced on + the kernel command line with "microcode.minrev=Y". + +config MICROCODE_LATE_FORCE_MINREV + bool "Enforce late microcode loading minimal revision check" + default n + depends on MICROCODE_LATE_LOADING + help + To prevent that users load microcode late which modifies already + in use features, newer microcodes have a minimum revision field + in the microcode header, which tells the kernel which minimum + revision must be active in the CPU to safely load that new microcode + late into the running system. If disabled the check will not + be enforced but the kernel will be tainted when the minimal + revision check fails. + + This minimal revision check can also be controlled via the + "microcode.minrev" parameter on the kernel command line. + + If unsure say Y. config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -880,6 +880,9 @@ static enum ucode_state request_microcod enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; + if (force_minrev) + return UCODE_NFOUND; + if (c->x86 >= 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,6 +46,9 @@ static struct microcode_ops *microcode_ops; static bool dis_ucode_ldr = true; +bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV); +module_param(force_minrev, bool, S_IRUSR | S_IWUSR); + bool initrd_gone; /* @@ -601,15 +604,17 @@ static int ucode_load_cpus_stopped(void return 0; } -static int ucode_load_late_stop_cpus(void) +static int ucode_load_late_stop_cpus(bool is_safe) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); + if (!is_safe) { + pr_err("Late microcode loading without minimal revision check.\n"); + pr_err("You should switch to early loading, if possible.\n"); + } atomic_set(&late_cpus_in, num_online_cpus()); atomic_set(&offline_in_nmi, 0); @@ -659,7 +664,9 @@ static int ucode_load_late_stop_cpus(voi return -EIO; } - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + if (!is_safe || failed || timedout) + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("Microcode load: updated on %u primary CPUs with %u siblings\n", updated, siblings); if (failed || timedout) { pr_err("Microcode load incomplete. %u CPUs timed out or failed\n", @@ -753,9 +760,17 @@ static int ucode_load_late_locked(void) return -EBUSY; ret = microcode_ops->request_microcode_fw(0, µcode_pdev->dev); - if (ret != UCODE_NEW) - return ret == UCODE_NFOUND ? -ENOENT : -EBADFD; - return ucode_load_late_stop_cpus(); + + switch (ret) { + case UCODE_NEW: + case UCODE_NEW_SAFE: + break; + case UCODE_NFOUND: + return -ENOENT; + default: + return -EBADFD; + } + return ucode_load_late_stop_cpus(ret == UCODE_NEW_SAFE); } static ssize_t reload_store(struct device *dev, --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -549,6 +549,9 @@ static enum ucode_state read_ucode_intel int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; + if (force_minrev) + return UCODE_NFOUND; + while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -13,6 +13,7 @@ struct device; enum ucode_state { UCODE_OK = 0, UCODE_NEW, + UCODE_NEW_SAFE, UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, @@ -36,6 +37,8 @@ struct microcode_ops { use_nmi : 1; }; +extern bool force_minrev; + extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); From patchwork Thu Aug 10 18:38:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 134162 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp627044vqi; Thu, 10 Aug 2023 12:09:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGcRxC5Z0DyW5DMgQ4yXs2gKCjZX1rFuYioOxbis17NU+5OWuLnv9t9bkTN04aA/NQOHszp X-Received: by 2002:a17:903:32d2:b0:1b5:5162:53bd with SMTP id i18-20020a17090332d200b001b5516253bdmr4176875plr.33.1691694543717; Thu, 10 Aug 2023 12:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691694543; cv=none; d=google.com; s=arc-20160816; b=VlhcHiqOkY5kYfGEN+FoE6MyfSEXda+dx6CaJzVCiR3cAtj9L3LmMuPZwF6a1krJ0N 3/Q1iPeo5enTRw2JgylH3NucDKviNZUrzosH8lKztyRrRIsXzTmW/F0F29OmQpH8qYCp UPVSe8LWHmejF+q7EeSUMxCc0sZZTHYgWgPO3iL/y/ArWPw8YRM8UjKO1Q0UrXFPDTBX 8UoE4zbd7dQ4uhBheXD94VuP8HYyzyt60cDAGZvqjcxmZXrHFGpAwfBG6T5g46vaQXFP vDbJFRpFBmDpOPbvblaTyzJIbGRpVIh1k/NoqHYypAS9P+Mz95Yug4CdXZ/Og48+pV+s vZCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=3lYQlOiULzlkk8uy1CdZGv00yUq/3gqaEE0fHgw8dHk=; fh=Vp72a/EEov1VOHpGPkCjAnDQEmhhYrQPa+PSfT8H2jQ=; b=UIWCAtYh7GOgnMxuFQOocAfnkbk4pvp8HoyAr/ofZv5Y4JYRupbFQN3p8cBBOvQ5wX Ubdh3ozs1RbZOn6eKC6ZkGPbXfA3cHPrwpFEvW+1cGntAnQjRgPPU4vjLUgml4gbdnQ6 qj8vQiX94qSnJW7/0cxN7wQU4x5rT6aSPl410dPAZdIZTZpNRbj+qgW7Xj4vr3jU1Qou vL70e093vSJumwOm4lMhwGZYqyvaUXDmBr7njtECt30N0k/lMP93EQ28lhicngWmV9/E cuwhnIKyHOPjAAH4gotmP48wsYGv5LSLw8y8B0tEO4KVe21W+3ghmK06u2DtG+c4GWbw JRew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=vNDF27F0; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ik7-20020a170902ab0700b001bb9c2bc8aasi1400545plb.401.2023.08.10.12.08.49; Thu, 10 Aug 2023 12:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=vNDF27F0; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236082AbjHJSjm (ORCPT + 99 others); Thu, 10 Aug 2023 14:39:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235880AbjHJSjO (ORCPT ); Thu, 10 Aug 2023 14:39:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EA7035A9 for ; Thu, 10 Aug 2023 11:38:39 -0700 (PDT) Message-ID: <20230810160806.672814197@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3lYQlOiULzlkk8uy1CdZGv00yUq/3gqaEE0fHgw8dHk=; b=vNDF27F0PgtTGttJQyprBbtQAZ+ihF+rygIj9so9I+UieBFzGbpzwXnlJDK9a0MbmO7U4Y 3RRPR9uqmxA4PugUzeZqPxdpSIAMAZxSTjP/RckZpC/dB/YnctxANs78hV82qku7cHqj+q KSBvPXdZobg7Onqy+d5FmPlN82U1quC33abF72P8WW6rosb4H0jvib5i0QMAkK9TEw5I9P J7G3ePwn1tiLfYeOJtPk4JDO9Z6GPkv55JaZOVW8dxRuMB0ZCFUug2n6mWp04RGv586Oib 5LlIOzA6gK8K2Enga4pIGQz04496HfsUgbVkjPbeCJqqDClhkXIL34VzS6m8Nw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3lYQlOiULzlkk8uy1CdZGv00yUq/3gqaEE0fHgw8dHk=; b=bB04/IZ1ok0RDxGkvYGW+X4BAiWvFJRnEMeCIkxJ7F3ngS9PLRsU9hYGR34wUbxMJx4zvn wS8bnXeHywC+57Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 30/30] x86/microcode/intel: Add a minimum required revision for late-loads References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:38:10 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773870297723693523 X-GMAIL-MSGID: 1773870297723693523 From: Ashok Raj In general users don't have the necessary information to determine whether late loading of a new microcode version is safe and does not modify anything which the currently running kernel uses already, e.g. removal of CPUID bits or behavioural changes of MSRs. To address this issue, Intel has added a "minimum required version" field to a previously reserved field in the microcode header. Microcode updates should only be applied if the current microcode version is equal to, or greater than this minimum required version. Thomas made some suggestions on how meta-data in the microcode file could provide Linux with information to decide if the new microcode is suitable candidate for late loading. But even the "simpler" option requires a lot of metadata and corresponding kernel code to parse it, so the final suggestion was to add the 'minimum required version' field in the header. When microcode changes visible features, microcode will set the minimum required version to its own revision which prevents late loading. Old microcode blobs have the minimum revision field always set to 0, which indicates that there is no information and the kernel considers it as unsafe. This is a pure OS software mechanism. The hardware/firmware ignores this header field. For early loading there is no restriction because OS visible features are enumerated after the early load and therefor a change has no effect. The check is always enabled, but by default not enforced. It can be enforced via Kconfig or kernel command line. If enforced, the kernel refuses to load microcode with a minium required version field which is zero or when the currently loaded microcode revision is smaller than the minimum required revision. If not enforced the load happens independent of the revision check to stay compatible with the existing behaviour, but it influences the decision whether the kernel is tainted or not. If the check signals that the late load itself, then the kernel is not tainted. [ tglx: Massaged changelog and fixed up the implementation ] Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 3 +- arch/x86/kernel/cpu/microcode/intel.c | 37 ++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -36,7 +36,8 @@ struct microcode_header_intel { unsigned int datasize; unsigned int totalsize; unsigned int metasize; - unsigned int reserved[2]; + unsigned int min_req_ver; + unsigned int reserved; }; struct microcode_intel { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -542,16 +542,40 @@ static enum ucode_state apply_microcode_ return ret; } +static bool ucode_validate_minrev(struct microcode_header_intel *mc_header) +{ + int cur_rev = boot_cpu_data.microcode; + + /* + * When late-loading, ensure the header declares a minimum revision + * required to perform a late-load. The previously reserved field + * is 0 in older microcode blobs. + */ + if (!mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Microcode header does not specify a required min version\n"); + return false; + } + + /* + * Check whether the minimum revision specified in the header is either + * greater or equal to the current revision. + */ + if (cur_rev < mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Current revision 0x%x too old\n", cur_rev); + pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver); + return false; + } + return true; +} + static enum ucode_state read_ucode_intel(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; + bool is_safe, new_is_safe = false; int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - if (force_minrev) - return UCODE_NFOUND; - while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; @@ -594,10 +618,15 @@ static enum ucode_state read_ucode_intel if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; + is_safe = ucode_validate_minrev(&mc_header); + if (force_minrev && !is_safe) + continue; + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; new_mc_size = mc_size; + new_is_safe = is_safe; mc = NULL; } @@ -614,7 +643,7 @@ static enum ucode_state read_ucode_intel return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; - return UCODE_NEW; + return new_is_safe ? UCODE_NEW_SAFE : UCODE_NEW; fail: kvfree(mc);