From patchwork Thu Aug 18 22:03:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 618 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp552911pxh; Thu, 18 Aug 2022 15:07:02 -0700 (PDT) X-Google-Smtp-Source: AA6agR4QTpmiqDEAKY5pHt61gS9v38vIh74sf/D39zALUEjKQLBMwB/er7lWgjnCg17Y/cMir37D X-Received: by 2002:a17:906:4fd3:b0:733:8be:24f8 with SMTP id i19-20020a1709064fd300b0073308be24f8mr3114015ejw.767.1660860422498; Thu, 18 Aug 2022 15:07:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860422; cv=none; d=google.com; s=arc-20160816; b=wUqvgHo0cX8mpJ2dU/L2WWB88T4hwrYjDmpGszfIu1+cJIEs2w6XYa2aymhlC1Ryyj efwuLVEeSi82Ma1NVEtahzThNgnUO40wC6rB7SYgf9LJ/QxP8TZSuzenXKGehTCJgd80 BwfcbSbTnCUSwfppp0XtSfCHVLxG53pNXznPfv30iL2nZWHHBIZK4kVktAx/WPcPEeEx 2r44VKgBkEMzHrVjKA7Lw1qW1r0cF4eofUBAsQVI7FQSRSg5Eq9BBPEQEJfe1mJtUDGs +sOEwI4uIEYN4IJmyrOZpULITNECzhsWbIqWfxASKI5DLIwpezXseVNFz97HxxnS5ilI YSYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=TFDQKPHJQlq06reLYXcFEUo7/qFywDFpqa3CN1UvkBQ=; b=YGED5T51IUP15PXOozcrD7rYnoeZ41fuifngLDHztBvAA65zxCGfXVpVKoXrme/b2N h5pstXF1iQg8EcuZwhe3cNgeO2WmcSoHjftPLySKJlEW+VQ6OLZyCHW/sotVe0+AbIJC 2bAZVl7iEdUYeQaTJeLGxvcoi/LKjMv89GbWsLkafJL69nNy1njHnckysXJCytlwIMbR yTEhoCA0wh8xWfz51jMh9ZPsqFDOIoYaDItXGQAn6Go8unQeCgoSy8gFPgmoStodqrbd 4bshVkPwHJka/jjiji62gT/wlJfu0wOwUCPL3B1Uj1qBIDPXjmSYzZLDr+avWid4cWBi 7i5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ycA87Old; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sa25-20020a1709076d1900b0072b44b630absi1991097ejc.867.2022.08.18.15.07.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:07:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ycA87Old; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6AA7B3858403 for ; Thu, 18 Aug 2022 22:06:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6AA7B3858403 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860368; bh=TFDQKPHJQlq06reLYXcFEUo7/qFywDFpqa3CN1UvkBQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=ycA87OldY+Xg7GPety/on1Mjj9dvkDHZ+XLAANypwVWzeV99/JalYID4NTrLZBcP2 Og6AWRMhHlaTeOinHr2CxMK5RZgag+PVHM++JHiCNJH8vNGEnc3XL7nq9ADdNYiduV tuilcDZSo8/fxi9OuorWIpOY+RMv+HTB8zrdWbuo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 1F175385842F for ; Thu, 18 Aug 2022 22:04:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1F175385842F Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwH001624 for ; Thu, 18 Aug 2022 15:04:03 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:03 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:01 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 3900E3F7070; Thu, 18 Aug 2022 15:04:01 -0700 (PDT) To: Subject: [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md Date: Thu, 18 Aug 2022 15:03:44 -0700 Message-ID: <1660860233-11175-2-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 1qt5KQPxJE5scZ-2oZgk7wbfCuhlCF7x X-Proofpoint-GUID: 1qt5KQPxJE5scZ-2oZgk7wbfCuhlCF7x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538378376641686?= X-GMAIL-MSGID: =?utf-8?q?1741538378376641686?= From: Andrew Pinski This moves the iterators out from riscv.md to iterators.md like most modern backends. I have not moved the iterators from the other .md files yet. OK? Build and tested on riscv64-linux-gnu and riscv32-linux-gnu. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/riscv.md (GPR): Move to new file. (P, X, BR): Likewise. (MOVE32, MOVE64, SHORT): Likewise. (HISI, SUPERQI, SUBX): Likewise. (ANYI, ANYF, SOFTF): Likewise. (size, load, default_load): Likewise. (softload, store, softstore): Likewise. (reg, fmt, ifmt, amo): Likewise. (UNITMODE, HALFMODE): Likewise. (RINT, rint_pattern, rint_rm): Likewise. (QUIET_COMPARISON, quiet_pattern, QUIET_PATTERN): Likewise. (any_extend, any_shiftrt, any_shift): Likewise. (any_bitwise): Likewise. (any_div, any_mod): Likewise. (any_gt, any_ge, any_lt, any_le): Likewise. (u, su): Likewise. (optab, insn): Likewise. * config/riscv/iterators.md: New file. --- gcc/config/riscv/iterators.md | 212 ++++++++++++++++++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 gcc/config/riscv/iterators.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md new file mode 100644 index 00000000000..351aa7f3cea --- /dev/null +++ b/gcc/config/riscv/iterators.md @@ -0,0 +1,212 @@ +;; Iterators for the machine description for RISC-V +;; Copyright (C) 2011-2022 Free Software Foundation, Inc. + +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +;; ------------------------------------------------------------------- +;; Mode Iterators +;; ------------------------------------------------------------------- + +;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated +;; from the same template. +(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) + +;; This mode iterator allows :P to be used for patterns that operate on +;; pointer-sized quantities. Exactly one of the two alternatives will match. +(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) + +;; Likewise, but for XLEN-sized quantities. +(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) + +;; Branches operate on XLEN-sized quantities, but for RV64 we accept +;; QImode values so we can force zero-extension. +(define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")]) + +;; 32-bit moves for which we provide move patterns. +(define_mode_iterator MOVE32 [SI]) + +;; 64-bit modes for which we provide move patterns. +(define_mode_iterator MOVE64 [DI DF]) + +;; Iterator for sub-32-bit integer modes. +(define_mode_iterator SHORT [QI HI]) + +;; Iterator for HImode constant generation. +(define_mode_iterator HISI [HI SI]) + +;; Iterator for QImode extension patterns. +(define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) + +;; Iterator for hardware integer modes narrower than XLEN. +(define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")]) + +;; Iterator for hardware-supported integer modes. +(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) + +;; Iterator for hardware-supported floating-point modes. +(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") + (DF "TARGET_DOUBLE_FLOAT") + (HF "TARGET_ZFH")]) + +;; Iterator for floating-point modes that can be loaded into X registers. +(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) + + +;; ------------------------------------------------------------------- +;; Mode attributes +;; ------------------------------------------------------------------- + + +;; This attribute gives the length suffix for a sign- or zero-extension +;; instruction. +(define_mode_attr size [(QI "b") (HI "h")]) + +;; Mode attributes for loads. +(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (HF "flh") (DF "fld")]) + +;; Instruction names for integer loads that aren't explicitly sign or zero +;; extended. See riscv_output_move and LOAD_EXTEND_OP. +(define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")]) + +;; Mode attribute for FP loads into integer registers. +(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")]) + +;; Instruction names for stores. +(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") (SF "fsw") (DF "fsd")]) + +;; Instruction names for FP stores from integer registers. +(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")]) + +;; This attribute gives the best constraint to use for registers of +;; a given mode. +(define_mode_attr reg [(SI "d") (DI "d") (CC "d")]) + +;; This attribute gives the format suffix for floating-point operations. +(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")]) + +;; This attribute gives the integer suffix for floating-point conversions. +(define_mode_attr ifmt [(SI "w") (DI "l")]) + +;; This attribute gives the format suffix for atomic memory operations. +(define_mode_attr amo [(SI "w") (DI "d")]) + +;; This attribute gives the upper-case mode name for one unit of a +;; floating-point mode. +(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")]) + +;; This attribute gives the integer mode that has half the size of +;; the controlling mode. +(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) + +;; ------------------------------------------------------------------- +;; Code Iterators +;; ------------------------------------------------------------------- + +;; This code iterator allows signed and unsigned widening multiplications +;; to use the same template. +(define_code_iterator any_extend [sign_extend zero_extend]) + +;; This code iterator allows the two right shift instructions to be +;; generated from the same template. +(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) + +;; This code iterator allows the three shift instructions to be generated +;; from the same template. +(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) + +;; This code iterator allows the three bitwise instructions to be generated +;; from the same template. +(define_code_iterator any_bitwise [and ior xor]) + +;; This code iterator allows unsigned and signed division to be generated +;; from the same template. +(define_code_iterator any_div [div udiv mod umod]) + +;; This code iterator allows unsigned and signed modulus to be generated +;; from the same template. +(define_code_iterator any_mod [mod umod]) + +;; These code iterators allow the signed and unsigned scc operations to use +;; the same template. +(define_code_iterator any_gt [gt gtu]) +(define_code_iterator any_ge [ge geu]) +(define_code_iterator any_lt [lt ltu]) +(define_code_iterator any_le [le leu]) + +;; ------------------------------------------------------------------- +;; Code Attributes +;; ------------------------------------------------------------------- + + +;; expands to an empty string when doing a signed operation and +;; "u" when doing an unsigned operation. +(define_code_attr u [(sign_extend "") (zero_extend "u") + (gt "") (gtu "u") + (ge "") (geu "u") + (lt "") (ltu "u") + (le "") (leu "u")]) + +;; is like , but the signed form expands to "s" rather than "". +(define_code_attr su [(sign_extend "s") (zero_extend "u")]) + +;; expands to the name of the optab for a particular code. +(define_code_attr optab [(ashift "ashl") + (ashiftrt "ashr") + (lshiftrt "lshr") + (div "div") + (mod "mod") + (udiv "udiv") + (umod "umod") + (ge "ge") + (le "le") + (gt "gt") + (lt "lt") + (ior "ior") + (xor "xor") + (and "and") + (plus "add") + (minus "sub")]) + +;; expands to the name of the insn that implements a particular code. +(define_code_attr insn [(ashift "sll") + (ashiftrt "sra") + (lshiftrt "srl") + (div "div") + (mod "rem") + (udiv "divu") + (umod "remu") + (ior "or") + (xor "xor") + (and "and") + (plus "add") + (minus "sub")]) + +;; ------------------------------------------------------------------- +;; Int Iterators. +;; ------------------------------------------------------------------- + +;; Iterator and attributes for floating-point rounding instructions. +(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND]) +(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")]) +(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")]) + +;; Iterator and attributes for quiet comparisons. +(define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET]) +(define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")]) +(define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") (UNSPEC_FLE_QUIET "LE")]) + From patchwork Thu Aug 18 22:03:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 616 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp552284pxh; Thu, 18 Aug 2022 15:05:57 -0700 (PDT) X-Google-Smtp-Source: AA6agR47almINnoJ7/d9PcjgvaeZcXPn7lHofbUD79cY2JWNYdiS9yCIBzutOQ6KeEaMyZkhKnTY X-Received: by 2002:a17:907:6295:b0:703:92b8:e113 with SMTP id nd21-20020a170907629500b0070392b8e113mr3124972ejc.594.1660860357375; Thu, 18 Aug 2022 15:05:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860357; cv=none; d=google.com; s=arc-20160816; b=d7gd3r6rQ8iBF9eG95TV2ir/mOQphZ9kDTpzeyI1MAvhVaEJ43PO9KJ1BNGbpEBVC8 3a/DFhGggJffc0bcJ94WrF0PTJa76BkJZlWNFavmrDFNohAxvt6cuE0GiPjV1zGiDaxN iRt7NHclGdjdvUgB6M1n0vPnDXHyFwuc7xJOmp5nGvzLb63/1GEwbggrEE8OL8jFsevP 1kOW/E77uXdOjLvI1/UzchRL4CYnMU/A63LgfDeNw+O3L8M2RXi4OdtwmpEX96ElGgya 1foXeA0kXms0NOi1pLVPo20vW4VXyYR+5cSc60i48LEODimVDCbaczkasbDHlc3IdPi+ yV+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=5N9rB8xC6CNrDR2irZokWAZawnWHvGM2mMNYx/6qX74=; b=fxRv/46xG+CW9d3QlcDUeAlwV86Cckp/FJZR7nVME2IluCsieeYXdYa1KbsvAeW9E9 inojBI5bhvC/M9l1qY18i0Gv4MvwfcIjW9R8HbiqZE/as8XulqNCfCoKgmMXLlad6aXz a2FoaAVBy3WVG28njrCJJdsJnGwsUADTrMQirUnlootomuptm+ToGjyNkl7DBIzyxrRo HGsV2A0083ucOGUDtew5WM+iiGId5PduiQ7+Z006F1H+coP8PUze8cQKyEr2SFEHK/RP ZuA4I5l4qwphifciUduMkw2CJE1ChvGMVgEQ78BwRA+OrmP/X2U9OkTOMvnd1EgYoFkd J5lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=G4QSv14p; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hq10-20020a1709073f0a00b007308bf614f7si2257967ejc.512.2022.08.18.15.05.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:05:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=G4QSv14p; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE33238582B6 for ; Thu, 18 Aug 2022 22:05:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE33238582B6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860309; bh=5N9rB8xC6CNrDR2irZokWAZawnWHvGM2mMNYx/6qX74=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=G4QSv14pO36JhqPh7w1rm4Ecf5y4iXYcFmstc6SekXkJ15DN+HCJR7KqrhPHpgIEb jMnymI0rmQqLMaeEuZDfAVKZBDNhhG71KZEnQPerh3y1jfn3h4kyJq8gh4731Hbygk LbrdYSS2f+KV+0nwjyELUQV4Ops9tHHhNtHupTLM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id E29613858292 for ; Thu, 18 Aug 2022 22:04:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E29613858292 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpsQC001638 for ; Thu, 18 Aug 2022 15:04:03 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wm-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:01 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 956953F707D; Thu, 18 Aug 2022 15:04:01 -0700 (PDT) To: Subject: [PATCH 02/10] [RISCV] Move iterators from bitmanip.md to iterators.md Date: Thu, 18 Aug 2022 15:03:45 -0700 Message-ID: <1660860233-11175-3-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: k1PiwkSx-lBcsc_ZkyeIm-o18GKXs58O X-Proofpoint-GUID: k1PiwkSx-lBcsc_ZkyeIm-o18GKXs58O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538309986058890?= X-GMAIL-MSGID: =?utf-8?q?1741538309986058890?= From: Andrew Pinski Just like the previous patch this move all of the iterators of bitmanip.md to iterators.md. All modern backends put the iterators in iterators.md for easier access. OK? Built and tested for riscv32-linux-gnu with --with-arch=rv32imafdc_zba_zbb_zbc_zbs. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/bitmanip.md (bitmanip_bitwise, bitmanip_minmax, clz_ctz_pcna, tbitmanip_optab, bitmanip_insn, shiftm1: Move to ... * config/riscv/iterators.md: Here. --- gcc/config/riscv/bitmanip.md | 25 ------------------------- gcc/config/riscv/iterators.md | 27 ++++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d1570ce8508..3329dd54eb6 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -17,31 +17,6 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -(define_code_iterator bitmanip_bitwise [and ior]) - -(define_code_iterator bitmanip_minmax [smin umin smax umax]) - -(define_code_iterator clz_ctz_pcnt [clz ctz popcount]) - -(define_code_attr bitmanip_optab [(smin "smin") - (smax "smax") - (umin "umin") - (umax "umax") - (clz "clz") - (ctz "ctz") - (popcount "popcount")]) - - -(define_code_attr bitmanip_insn [(smin "min") - (smax "max") - (umin "minu") - (umax "maxu") - (clz "clz") - (ctz "ctz") - (popcount "cpop")]) - -(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) - ;; ZBA extension. (define_insn "*zero_extendsidi2_bitmanip" diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 351aa7f3cea..54590f43193 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -113,6 +113,9 @@ (define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")]) ;; the controlling mode. (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) +; bitmanip mode attribute +(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) + ;; ------------------------------------------------------------------- ;; Code Iterators ;; ------------------------------------------------------------------- @@ -148,11 +151,17 @@ (define_code_iterator any_ge [ge geu]) (define_code_iterator any_lt [lt ltu]) (define_code_iterator any_le [le leu]) +; bitmanip code iterators +(define_code_iterator bitmanip_bitwise [and ior]) + +(define_code_iterator bitmanip_minmax [smin umin smax umax]) + +(define_code_iterator clz_ctz_pcnt [clz ctz popcount]) + ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- - ;; expands to an empty string when doing a signed operation and ;; "u" when doing an unsigned operation. (define_code_attr u [(sign_extend "") (zero_extend "u") @@ -196,6 +205,22 @@ (define_code_attr insn [(ashift "sll") (plus "add") (minus "sub")]) +; bitmanip code attributes +(define_code_attr bitmanip_optab [(smin "smin") + (smax "smax") + (umin "umin") + (umax "umax") + (clz "clz") + (ctz "ctz") + (popcount "popcount")]) +(define_code_attr bitmanip_insn [(smin "min") + (smax "max") + (umin "minu") + (umax "maxu") + (clz "clz") + (ctz "ctz") + (popcount "cpop")]) + ;; ------------------------------------------------------------------- ;; Int Iterators. ;; ------------------------------------------------------------------- From patchwork Thu Aug 18 22:03:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 617 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp552630pxh; Thu, 18 Aug 2022 15:06:35 -0700 (PDT) X-Google-Smtp-Source: AA6agR5LQVkkwHrUN6I7ZGMpFgfGZhm2vKJZtFbvqbP4tQsvF3KCWdvVCDoEN1q601qJuXiDro4m X-Received: by 2002:a05:6402:c45:b0:442:c549:8e6b with SMTP id cs5-20020a0564020c4500b00442c5498e6bmr3708046edb.123.1660860395735; Thu, 18 Aug 2022 15:06:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860395; cv=none; d=google.com; s=arc-20160816; b=XAR6k64reWrPSjsrnSwRswI9U5UxxkwrzkcuLWXfP3ouYoPOKC12F+j+7g0fbpU/uj RH63fQXP0ihmIPfWo0bhC6WDmxSnF8j3SHYVdK+xVCo2F6J0nnBhWH+4yBwaw8nsDaLN HflN3p8si8jhWgYSIGl1TFaAbPVht9ky+rtpUKsOknHRcgAc85y/bdgIKHVnUVaqN6NM kzjbA0jmIRFdWBm81iNStvw8Hs/FleGMB2RvSRJPX3d+BJ4pqORTnjYTPVhFsDj3hhQK 3KzcJxnNMfS9g0cqp8GOFHPSUipUgnXHJPYa2xgqQsf5McleYk+TZ8crB4vcKb0P8B0P nGgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=qNk4uic1z5MX+Xm3WwogfcJONgwLRxn0u9GiIE0CNUg=; b=uw9wAtwKxza4+eAHk7009TBWPFjTzIWMRl0YWSICFnMhMJ/JUQ92Xaf6TTkrK7d3xr UvJKyNjF+uvE/Ilen1AIyihjCLuxvEoj1TJ0G6oB9XaO7dlMtEeLLgALHqXbXwyijCH+ Wx3eOq/QmYVdP+k+DB4xcPMIcLZpVhVs9wJODOBTJEwL5A5fREfDEiY4ytcI0B1gGtTq djRpekeL9V2jyWFJ2bBb6kQnihOAnUh6zDSH10UfHqKT0oN9245nwB/p3P7Wuv3TbIKA lOGp3DWcBlEV7UotfZazseKAwck1NRJuk245PpBRJ4IP9aAnOSdzdxzuDCiYHYxrgpz/ DG/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=tNvMbMzP; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hc10-20020a170907168a00b007311b45e4bcsi2136921ejc.692.2022.08.18.15.06.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:06:35 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=tNvMbMzP; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 711D63858012 for ; Thu, 18 Aug 2022 22:05:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 711D63858012 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860344; bh=qNk4uic1z5MX+Xm3WwogfcJONgwLRxn0u9GiIE0CNUg=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=tNvMbMzPVIK2NfSYtzB8vhmDVlNZbT/tLeUbfFVIGG4Jrz5Yhw24wjyP/wVhyYqwv 3WRbhqM6paEGZiVp2XBFEKBPdwcpc8psLqBTUdk/Us/k621welCTHUxMz059XHq3nn E/x8hKPQ7Jn9MJhZds/JpKK8Y5MXYRy15282toBM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 3FFB63858297 for ; Thu, 18 Aug 2022 22:04:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3FFB63858297 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwJ001624 for ; Thu, 18 Aug 2022 15:04:04 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:02 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id DEF5B3F7084; Thu, 18 Aug 2022 15:04:01 -0700 (PDT) To: Subject: [PATCH 03/10] [RISCV] Move iterators from sync.md to iterators.md Date: Thu, 18 Aug 2022 15:03:46 -0700 Message-ID: <1660860233-11175-4-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mDBLAaE92IDuyo1DN86FukPQu6kio8G2 X-Proofpoint-GUID: mDBLAaE92IDuyo1DN86FukPQu6kio8G2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538350224939587?= X-GMAIL-MSGID: =?utf-8?q?1741538350224939587?= From: Andrew Pinski Like the previous two patches this moves the iterators that are in sync.md to iterators.md. OK? build and tested for riscv64-linux-gnu. gcc/ChangeLog: * config/riscv/sync.md (any_atomic, atomic_optab): Move to ... * config/riscv/iterators.md: Here. --- gcc/config/riscv/iterators.md | 7 +++++++ gcc/config/riscv/sync.md | 4 ---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 54590f43193..6c8a6d2dd59 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -151,6 +151,9 @@ (define_code_iterator any_ge [ge geu]) (define_code_iterator any_lt [lt ltu]) (define_code_iterator any_le [le leu]) +; atomics code iterator +(define_code_iterator any_atomic [plus ior xor and]) + ; bitmanip code iterators (define_code_iterator bitmanip_bitwise [and ior]) @@ -205,6 +208,10 @@ (define_code_attr insn [(ashift "sll") (plus "add") (minus "sub")]) +; atomics code attribute +(define_code_attr atomic_optab + [(plus "add") (ior "or") (xor "xor") (and "and")]) + ; bitmanip code attributes (define_code_attr bitmanip_optab [(smin "smin") (smax "smax") diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 86b41e6b00a..7deb290d9dc 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -27,10 +27,6 @@ (define_c_enum "unspec" [ UNSPEC_MEMORY_BARRIER ]) -(define_code_iterator any_atomic [plus ior xor and]) -(define_code_attr atomic_optab - [(plus "add") (ior "or") (xor "xor") (and "and")]) - ;; Memory barriers. (define_expand "mem_thread_fence" From patchwork Thu Aug 18 22:03:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 615 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp551960pxh; Thu, 18 Aug 2022 15:05:26 -0700 (PDT) X-Google-Smtp-Source: AA6agR5TE22UZXEK3rj/FewhEoWEj4vrFn58nHU6lBewufhByrkXMBlCgrdO2xtPJlasW/DLKgh1 X-Received: by 2002:aa7:cb87:0:b0:43b:e650:6036 with SMTP id r7-20020aa7cb87000000b0043be6506036mr3772612edt.350.1660860326496; Thu, 18 Aug 2022 15:05:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860326; cv=none; d=google.com; s=arc-20160816; b=t3OswuGCeaLQlOuZCgz9b83YfpLR+54QLUgEsAS1do/I1pbYzEfd943z1wIk5YQ1jp 9mHQpwVLFiOrx8wQpyLc8PGUrTTaiBNcNtrElf688hCeuq1ltmnxWmUUc1ambueGVcqp aBtg981moqfmVeyLl1v0Ex1Hz5yceJ/NcCvpsScLBPiN3VEMxli5fxZi4l0kN7sw7fYQ K5HRsRoVIVpoZeD02snOQG8ge7GA6ihLWuyKV4k+SZqwefg/ljqY7LCdNU6RNKhJyPLA lLuRDUXgoq9UuBg0QfVkwRK0pBp4F4NVmHn+5CHdEpnbs4m1JfH+w1ijOX50nWzqpDcF Aeyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=D+onEhYnpOBoYJfZZjToxDSffQ4xQj2cfzTxxivcnFA=; b=DtlQTcYTFzroJGk98sOIBGI30MbSF8LFWUrm4HvwMiNMmM2JHBkrOcx6PHqHviSyIr MMHILuMgnJBrLcLRJ3iMpxP9Xtt6gBDI0JNQh0txuSk9Au1lNsR7ARORkXdaPm4U206H w5MiXws+MBB2EWI5VOKux8Sdq7uhZlhivwmhz+FihOPzOAMDjiIP01C249eO4GK9XAuR +GTFs0pMBIGBeKNDUoWRCmKHKPkbkIirHTuN1+NCRgou9M8S8m0VgT0hBo/PO/LlrrRn 6xhH82jOMjuSEmi2CP7N8z4+Q3OJVJy7o0tw9kddS3hBG/A5rujzVIe0+WTqLVG93UDC gRCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TxRO6OvD; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hb7-20020a170907160700b00731010c202dsi1829011ejc.764.2022.08.18.15.05.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:05:26 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TxRO6OvD; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 744353858004 for ; Thu, 18 Aug 2022 22:04:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 744353858004 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860289; bh=D+onEhYnpOBoYJfZZjToxDSffQ4xQj2cfzTxxivcnFA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=TxRO6OvDza3h/9eiYgAXt79fp+RWw8ap7PDDwYRGWpU9AN0qkz9YL0tMkb0Uv8EH7 j949pPb1RY63UERJg40nEhHf9NkV3lorKBqLBlBNdQd4UXcQ4ksIZFsbk7MyTaQkvG bO8J4i/Fx3/kq7jb+ubQPW/4d/uBWPTjIrvMSRrg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id E0D85385829B for ; Thu, 18 Aug 2022 22:04:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E0D85385829B Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwK001624 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:02 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 2F7993F708C; Thu, 18 Aug 2022 15:04:02 -0700 (PDT) To: Subject: [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too Date: Thu, 18 Aug 2022 15:03:47 -0700 Message-ID: <1660860233-11175-5-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: EBXaQajYPq3MwlvStXheiFz8xFuzsKJZ X-Proofpoint-GUID: EBXaQajYPq3MwlvStXheiFz8xFuzsKJZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538278112703759?= X-GMAIL-MSGID: =?utf-8?q?1741538278112703759?= From: Andrew Pinski To make it easier to find operands modifiers while in the md file, add the list of modifiers to the top of the md file. This is similar to i386 target. OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Make a mention to keep the list in riscv.md in sync with this list. * config/riscv/riscv.md: Add list of modifiers as comments. --- gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/riscv.md | 184 ++++---------------------------------- 2 files changed, 18 insertions(+), 170 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 7c120eaa8e3..189be5e4e6f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3730,7 +3730,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. - 'T' Print shift-index of inverted single-bit mask OP. */ + 'T' Print shift-index of inverted single-bit mask OP. + + Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f4a5ff07fe4..aad2836d179 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -19,6 +19,20 @@ ;; along with GCC; see the file COPYING3. If not see ;; . + +;; Keep this list and the one above riscv_print_operand in sync. +;; The special asm out single letter directives following a '%' are: +;; h -- Print the high-part relocation associated with OP, after stripping +;; any outermost HIGH. +;; R -- Print the low-part relocation associated with OP. +;; C -- Print the integer branch condition for comparison OP. +;; A -- Print the atomic operation suffix for memory model OP. +;; F -- Print a FENCE if the memory model requires a release. +;; z -- Print x0 if OP is zero, otherwise print OP normally. +;; i -- Print i if the operand is not a register. +;; S -- Print shift-index of single-bit mask OP. +;; T -- Print shift-index of inverted single-bit mask OP. + (define_c_enum "unspec" [ ;; Override return address for exception handling. UNSPEC_EH_RETURN @@ -107,6 +121,7 @@ (define_constants (include "predicates.md") (include "constraints.md") +(include "iterators.md") ;; .................... ;; @@ -269,175 +284,6 @@ (define_attr "tune" (define_asm_attributes [(set_attr "type" "multi")]) -;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated -;; from the same template. -(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) - -;; This mode iterator allows :P to be used for patterns that operate on -;; pointer-sized quantities. Exactly one of the two alternatives will match. -(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) - -;; Likewise, but for XLEN-sized quantities. -(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) - -;; Branches operate on XLEN-sized quantities, but for RV64 we accept -;; QImode values so we can force zero-extension. -(define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")]) - -;; 32-bit moves for which we provide move patterns. -(define_mode_iterator MOVE32 [SI]) - -;; 64-bit modes for which we provide move patterns. -(define_mode_iterator MOVE64 [DI DF]) - -;; Iterator for sub-32-bit integer modes. -(define_mode_iterator SHORT [QI HI]) - -;; Iterator for HImode constant generation. -(define_mode_iterator HISI [HI SI]) - -;; Iterator for QImode extension patterns. -(define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) - -;; Iterator for hardware integer modes narrower than XLEN. -(define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")]) - -;; Iterator for hardware-supported integer modes. -(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) - -;; Iterator for hardware-supported floating-point modes. -(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") - (DF "TARGET_DOUBLE_FLOAT") - (HF "TARGET_ZFH")]) - -;; Iterator for floating-point modes that can be loaded into X registers. -(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) - -;; This attribute gives the length suffix for a sign- or zero-extension -;; instruction. -(define_mode_attr size [(QI "b") (HI "h")]) - -;; Mode attributes for loads. -(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") (SF "flw") (DF "fld")]) - -;; Instruction names for integer loads that aren't explicitly sign or zero -;; extended. See riscv_output_move and LOAD_EXTEND_OP. -(define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")]) - -;; Mode attribute for FP loads into integer registers. -(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")]) - -;; Instruction names for stores. -(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") (SF "fsw") (DF "fsd")]) - -;; Instruction names for FP stores from integer registers. -(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")]) - -;; This attribute gives the best constraint to use for registers of -;; a given mode. -(define_mode_attr reg [(SI "d") (DI "d") (CC "d")]) - -;; This attribute gives the format suffix for floating-point operations. -(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")]) - -;; This attribute gives the integer suffix for floating-point conversions. -(define_mode_attr ifmt [(SI "w") (DI "l")]) - -;; This attribute gives the format suffix for atomic memory operations. -(define_mode_attr amo [(SI "w") (DI "d")]) - -;; This attribute gives the upper-case mode name for one unit of a -;; floating-point mode. -(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")]) - -;; This attribute gives the integer mode that has half the size of -;; the controlling mode. -(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) - -;; Iterator and attributes for floating-point rounding instructions. -(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND]) -(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")]) -(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")]) - -;; Iterator and attributes for quiet comparisons. -(define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET]) -(define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")]) -(define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") (UNSPEC_FLE_QUIET "LE")]) - -;; This code iterator allows signed and unsigned widening multiplications -;; to use the same template. -(define_code_iterator any_extend [sign_extend zero_extend]) - -;; This code iterator allows the two right shift instructions to be -;; generated from the same template. -(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) - -;; This code iterator allows the three shift instructions to be generated -;; from the same template. -(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) - -;; This code iterator allows the three bitwise instructions to be generated -;; from the same template. -(define_code_iterator any_bitwise [and ior xor]) - -;; This code iterator allows unsigned and signed division to be generated -;; from the same template. -(define_code_iterator any_div [div udiv mod umod]) - -;; This code iterator allows unsigned and signed modulus to be generated -;; from the same template. -(define_code_iterator any_mod [mod umod]) - -;; These code iterators allow the signed and unsigned scc operations to use -;; the same template. -(define_code_iterator any_gt [gt gtu]) -(define_code_iterator any_ge [ge geu]) -(define_code_iterator any_lt [lt ltu]) -(define_code_iterator any_le [le leu]) - -;; expands to an empty string when doing a signed operation and -;; "u" when doing an unsigned operation. -(define_code_attr u [(sign_extend "") (zero_extend "u") - (gt "") (gtu "u") - (ge "") (geu "u") - (lt "") (ltu "u") - (le "") (leu "u")]) - -;; is like , but the signed form expands to "s" rather than "". -(define_code_attr su [(sign_extend "s") (zero_extend "u")]) - -;; expands to the name of the optab for a particular code. -(define_code_attr optab [(ashift "ashl") - (ashiftrt "ashr") - (lshiftrt "lshr") - (div "div") - (mod "mod") - (udiv "udiv") - (umod "umod") - (ge "ge") - (le "le") - (gt "gt") - (lt "lt") - (ior "ior") - (xor "xor") - (and "and") - (plus "add") - (minus "sub")]) - -;; expands to the name of the insn that implements a particular code. -(define_code_attr insn [(ashift "sll") - (ashiftrt "sra") - (lshiftrt "srl") - (div "div") - (mod "rem") - (udiv "divu") - (umod "remu") - (ior "or") - (xor "xor") - (and "and") - (plus "add") - (minus "sub")]) - ;; Ghost instructions produce no real code and introduce no hazards. ;; They exist purely to express an effect on dataflow. (define_insn_reservation "ghost" 0 From patchwork Thu Aug 18 22:03:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 624 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp554643pxh; Thu, 18 Aug 2022 15:10:01 -0700 (PDT) X-Google-Smtp-Source: AA6agR71EVLrKBI+KOnzUcvCPzUs0vPbYPXiAswKjsy8RloymVdfwTQt0x1sMqjpe+3vXl5Y1uLR X-Received: by 2002:a05:6402:3485:b0:43d:7fe0:74d1 with SMTP id v5-20020a056402348500b0043d7fe074d1mr3768227edc.413.1660860600942; Thu, 18 Aug 2022 15:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860600; cv=none; d=google.com; s=arc-20160816; b=syU4Tn2RY4v42LaiWVJ0VyBH+AXncW8h7ldEECcOu4/5O/DgfA050/kckRWA+Go5wQ yT/1ughxNLS9YzKI+O3MpY9A9gP/BC2RCDy/GOVnUjghe8RTIv4qEA/BDgWdvIhJbwpu vRlCTIBbhp5/ioIMLSZX0GeLz9xHpv4P+StRz3t2BU55q+GRQB4ZOiGZWKCQObqVqwkb EktlVtC/gZp6fI/LMcch9ZZ041yDgpZ9aJM0G6aWi5wK9oBZGkceTRth+vYW3Q/KZcN5 rabbmai2d8FOXgglQPzZZML8NaeD/PYn+s5JTLsVlMualaMG1xhreUvadtWcpVZlYJ/K frRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=AlD7vlW7UeQUOxJGdUzLgSn1CqFE/eVk2C2sj4hHIUk=; b=n6KR+W5ynDwCfadnYNJ9RWKss4Nryb4CPyhboZTDnHZz756YjjK23KvtuEcN75fQbf SmLpVBAh8k7Jyd8hmRCwsMH98xnrAKA9fmYBX6MjDAVlnXfyIsoxCaVB+QK/AASw6YVK N6YdK8Ly7t4o9FMH1Ti2qywJ7budAh8vU7a9zoVvNyFnG/RMfcwWw6CSlvyfN4v2UqPu gQbE6cM3vRLOtRpZDbeLvNBuhumybjpSMjGtxFfuPcgtNaylScp5dvdh5rsiZIAzz9sB QOztbdyMTcR6o3WGMdQcjV0LYZ1J1lcv6m5Bd9DB4pA6SLsvfnE6G47DjAvfppB8bAex jThw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=dn0GkCiR; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cs14-20020a0564020c4e00b004407104243csi1801751edb.153.2022.08.18.15.10.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:10:00 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=dn0GkCiR; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9FBDD3857B82 for ; Thu, 18 Aug 2022 22:09:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9FBDD3857B82 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860540; bh=AlD7vlW7UeQUOxJGdUzLgSn1CqFE/eVk2C2sj4hHIUk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=dn0GkCiRbWY0Bx8LAfFikXwKQxb80vNrNrpfpzuCOncgin4EqjbBHQ631T6GG1QpK kRHVig/AEA3HyF6Nu6yAYunlTNm722m4wwxC7wji55gvfu97oNRJYVXgdyUs5pmL3A X8UbdLvPcf/gRE5UxOcgYjcP5KDkdrbA0WWpgX9o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 3C5E0385829E for ; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3C5E0385829E Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwL001624 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-8 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:02 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 896793F7070; Thu, 18 Aug 2022 15:04:02 -0700 (PDT) To: Subject: [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it Date: Thu, 18 Aug 2022 15:03:48 -0700 Message-ID: <1660860233-11175-6-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Ypbohd731cWvGwfKub-WaEOwzg8BZG04 X-Proofpoint-GUID: Ypbohd731cWvGwfKub-WaEOwzg8BZG04 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538565652272060?= X-GMAIL-MSGID: =?utf-8?q?1741538565652272060?= From: Andrew Pinski To make things easier and more maintainable, we need to add support printing out w if TARGET_64BIT so this patch adds %~ to do that, similar how the x86 backend uses %~ to print out i/f for TARGET_AVX2. We could have chosen any punctuation symbol but ~ looks the closest to w. OK? Build and tested for riscv64-linux-gnu and riscv32-linux-gnu with no regressions. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Handle '~'. (riscv_print_operand_punct_valid_p): New function (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define. * config/riscv/bitmanip.md (si2/clz_ctz_pcnt): Use %~ instead of conditional the pattern on TARGET_64BIT. (rotrsi3): Likewise. (rotlsi3): Likewise. * config/riscv/riscv.md: Add ~ to the list of modifiers. (addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT. (subsi3): Likewise. (negsi2): Likewise. (mulsi3): Likewise. (optab>si3/any_div): Likewise. (*addhi3): Likewise. (si3/any_shift): Likewise. --- gcc/config/riscv/bitmanip.md | 6 +++--- gcc/config/riscv/riscv.cc | 19 +++++++++++++++++++ gcc/config/riscv/riscv.md | 15 ++++++++------- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 3329dd54eb6..ebd6eee1a22 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -143,7 +143,7 @@ (define_insn "si2" [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "w\t%0,%1" : "\t%0,%1"; } + "%~\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) @@ -201,7 +201,7 @@ (define_insn "rotrsi3" (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_ZBB" - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } + "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotrdi3" @@ -225,7 +225,7 @@ (define_insn "rotlsi3" (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotldi3" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 189be5e4e6f..22d0f6d604c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3731,12 +3731,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. 'T' Print shift-index of inverted single-bit mask OP. + '~' Print w if TARGET_64BIT is true; otherwise not print anything. Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) { + /* `~` does not take an operand so op will be null + Check for before accessing op. + */ + if (letter == '~') + { + if (TARGET_64BIT) + fputc('w', file); + return; + } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); @@ -3812,6 +3822,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) } } +/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */ +static bool +riscv_print_operand_punct_valid_p (unsigned char code) +{ + return (code == '~'); +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ static void @@ -5900,6 +5917,8 @@ riscv_init_libfuncs (void) #define TARGET_PRINT_OPERAND riscv_print_operand #undef TARGET_PRINT_OPERAND_ADDRESS #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address +#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P +#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index aad2836d179..30cd07dc6f5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -32,6 +32,7 @@ ;; i -- Print i if the operand is not a register. ;; S -- Print shift-index of single-bit mask OP. ;; T -- Print shift-index of inverted single-bit mask OP. +;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. (define_c_enum "unspec" [ ;; Override return address for exception handling. @@ -312,7 +313,7 @@ (define_insn "addsi3" (plus:SI (match_operand:SI 1 "register_operand" " r,r") (match_operand:SI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -452,7 +453,7 @@ (define_insn "subsi3" (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") (match_operand:SI 2 "register_operand" " r")))] "" - { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; } + "sub%~\t%0,%z1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -568,7 +569,7 @@ (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" " r")))] "" - { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; } + "neg%~\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -613,7 +614,7 @@ (define_insn "mulsi3" (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_MUL" - { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } + "mul%~\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -883,7 +884,7 @@ (define_insn "si3" (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_DIV" - { return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; } + "%i2%~\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -1605,7 +1606,7 @@ (define_insn "*addhi3" (plus:HI (match_operand:HISI 1 "register_operand" " r,r") (match_operand:HISI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "HI")]) @@ -1787,7 +1788,7 @@ (define_insn "si3" operands[2] = GEN_INT (INTVAL (operands[2]) & (GET_MODE_BITSIZE (SImode) - 1)); - return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; + return "%i2%~\t%0,%1,%2"; } [(set_attr "type" "shift") (set_attr "mode" "SI")]) From patchwork Thu Aug 18 22:03:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 619 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp553260pxh; Thu, 18 Aug 2022 15:07:37 -0700 (PDT) X-Google-Smtp-Source: AA6agR49gLbN59FPY2XnBx00OjAznPi0aciY0v/kyt9LvFZgf4cS5MsCnhbl9+e48UbdYiMn6SVq X-Received: by 2002:a05:6402:26cb:b0:43e:6fab:11c6 with SMTP id x11-20020a05640226cb00b0043e6fab11c6mr3619532edd.272.1660860457726; Thu, 18 Aug 2022 15:07:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860457; cv=none; d=google.com; s=arc-20160816; b=st/Nx6P3OCibYwbE69TT5+sRk9pIltNJsw2pfel4e/U0B/dQOxZ1GltvVLJX3aJa2t TMxHwvLp1cE6A08ZlVvCuU23m4GvhemvOFyjGHaEfdU8gYMwY7YW39RJp0J+21scnBAg AXLHgzojaAGXuu2PBuIVnV6nyELO5FoBEvPOFXkjrvopq9k9fdt2ca8dWiphtRM426P/ NfaPx/HAVhBYbsly/JYCM0FVudsBOqUBtLLW5nq+M93VVYRryXd39OegCOtw32Ar2mWW YG6uhpBua2JcJmcCFUZoSa79Ep0BaDoqVQM//dIUbTLipbfOpTNpnPLQKeyJ8IJ0bX2P ESpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=jcHsO5t2ncH2gU2uk0LwBigR/hMVBHBp4DBYPevSOfg=; b=sXe3Xv+Cj83YQ/o3T4P3oh0OD4OQ5+roJd9SiIb9at93H18yxgyCcmtWkr7dETQXLd frr0H5P06iJNIYRxzZsfK5LYeVoG5CShSRYiS0x2230YIDGd9+vO58urSG21By/wFG4G lw05802Z7qNvFspE9ROC1kSryNsn+lMeWspsiUk7vXAmvscryj+/EoUZ7K7nXm1qtfyU dMQoIvhs6clhAn9wHhdWHgiSZ//fWtZXjcJ6ADzS8TozC0EQQ30qVId4fGNHyPmlHxIU KX8mreAPQ46lyQKOVSLzGHYNmqBfVJ9J13nTFX/waByyt42YBjWw5dKvFzmIAyeG3AYE VFLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="d/7x7FUk"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sa14-20020a1709076d0e00b007308e7cd167si1725558ejc.846.2022.08.18.15.07.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:07:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="d/7x7FUk"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A869E385741C for ; Thu, 18 Aug 2022 22:06:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A869E385741C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860401; bh=jcHsO5t2ncH2gU2uk0LwBigR/hMVBHBp4DBYPevSOfg=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=d/7x7FUktGwZ46RwN5hlmR/3teNF7zJRZ2ry6Y1BrNT4KxnrAorVo34hgRGg2zWzn d3hXle28JgU/jO+g/0yKBxJXNKSBUZ7sUv7JbymWOXIJIyaED0wO8aicoMSj0eLB7Y tg1KtE6lXiiGXbPDbug2+K+UvTSHoaeder7DM9TU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 7D0EB3858294 for ; Thu, 18 Aug 2022 22:04:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7D0EB3858294 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqWrD002457 for ; Thu, 18 Aug 2022 15:04:04 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:03 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id DCDC63F707D; Thu, 18 Aug 2022 15:04:02 -0700 (PDT) To: Subject: [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns Date: Thu, 18 Aug 2022 15:03:49 -0700 Message-ID: <1660860233-11175-7-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: UeRTAP2V62vDaaMP3gI6J8MxVzWuIETm X-Proofpoint-GUID: UeRTAP2V62vDaaMP3gI6J8MxVzWuIETm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-14.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538415139466210?= X-GMAIL-MSGID: =?utf-8?q?1741538415139466210?= From: Andrew Pinski This simplifies the code by adding a predicate and a constraint for 1/2/3. The aarch64 backend has a similar predicate called aarch64_shift_imm_ which they use there. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/constraints.md (Ds3): New constraint. * config/riscv/predicates.md (imm123_operand): New predicate. * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand. (*shNadduw): Likewise. --- gcc/config/riscv/bitmanip.md | 8 +++----- gcc/config/riscv/constraints.md | 6 ++++++ gcc/config/riscv/predicates.md | 5 +++++ 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index ebd6eee1a22..73a36f7751b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip" (define_insn "*shNadd" [(set (match_operand:X 0 "register_operand" "=r") (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:QI 2 "imm123_operand" "Ds3")) (match_operand:X 3 "register_operand" "r")))] - "TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" + "TARGET_ZBA" "sh%2add\t%0,%1,%3" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -44,11 +43,10 @@ (define_insn "*shNadduw" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:QI 2 "imm123_operand" "Ds3")) (match_operand 3 "immediate_operand" "")) (match_operand:DI 4 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" "sh%2add.uw\t%0,%1,%4" [(set_attr "type" "bitmanip") diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index bafa4188ccb..61b84875fd9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -54,6 +54,12 @@ (define_constraint "L" (and (match_code "const_int") (match_test "LUI_OPERAND (ival)"))) +(define_constraint "Ds3" + "@internal + 1, 2 or 3 immediate" + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 1, 3)"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 79e0c1d5589..2af7f661d6f 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -244,6 +244,11 @@ (define_predicate "imm5_operand" (and (match_code "const_int") (match_test "INTVAL (op) < 5"))) +;; A const_int for sh1add/sh2add/sh3add +(define_predicate "imm123_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 3)"))) + ;; A CONST_INT operand that consists of a single run of consecutive set bits. (define_predicate "consecutive_bits_operand" (match_code "const_int") From patchwork Thu Aug 18 22:03:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 623 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp554460pxh; Thu, 18 Aug 2022 15:09:38 -0700 (PDT) X-Google-Smtp-Source: AA6agR6mW82JqsEtF8rnIeK3clTzJbJjSaxoJBKvTGl64YRMDiTcR2jYSBFACRxUtkXyWY3HBEfw X-Received: by 2002:a17:906:7e43:b0:738:6395:8d94 with SMTP id z3-20020a1709067e4300b0073863958d94mr3137800ejr.54.1660860578750; Thu, 18 Aug 2022 15:09:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860578; cv=none; d=google.com; s=arc-20160816; b=R+4rrLIgnE0Mp8VJt2Bsur+wsMBai7mZTCsWyAF3le57EUyaIAZ0z7cAlpq/vcRDBo 13NIf0l1mtEY7pi8W7NHxspPX+WYHeEZU8p3wcpn5BbZJy/nxbWOVybXFZlGcTterZmt m+mp3xLT01cKgql6qDHQkcccjz2upKvmBnRP1gSZv7345lwOUGw3/t3phmjfUEZSyv3B MMwCYiRSsUKZFA9acmJPn9ioDJqqr0fgaTOq9FU7mgeUACvBfgCZOzjDsgr90zC75bgf UKINxIfm65n0k0LjtHyxnNTJM2+bWCn6OAnTnKmKpoMLTN7FBpM+1pYw2oMkUNf508oH IR/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=lvefWxPGTwvwU2BC3l40urwWoy2RmcuCSLkkNgIZ9kI=; b=nIEUYQAsCeGTdKnVsuTst46cpg5Zy0xttvkIzMfx22JUiOt3mb9JbUQRhVPSLFDGl3 NNtE0qF9jwp9SvdWuWbnsfCKu9s0WhKmUywxpAw3Vn0kFC43EvLgDh0aNksh6cahSx0s kHhvzf+M4wI/j5YdR+aRGZNsOaHy9dqLreO22FY+TCDwshOUYmNcrQYSLgeAyRaNF88Q YNaPCcUIkMuoH7lXHGM7Dbla1V9JrrN4YYXrvYTD7O1+LtINsakiuUPuSGVVoWa0R0jQ 7+3LfZCLs9PIzSOHFlCxfIRa24bRevFdYAmBBX20fF7MfWy/l/ECZz62vlP4z+JLzWtB z6xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=qRphcudg; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e33-20020a056402332100b0043c891e0f0fsi1916948eda.356.2022.08.18.15.09.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:09:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=qRphcudg; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8CA593857419 for ; Thu, 18 Aug 2022 22:08:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8CA593857419 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860516; bh=lvefWxPGTwvwU2BC3l40urwWoy2RmcuCSLkkNgIZ9kI=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=qRphcudgAJ22AgUWExaMl2xNeUv8uuL/+eclzKr45knaUQDY/S40gcTrFOg3yimxS zareRZteL/V3l00B7Z84cazcMtmECuj2WirwaibKfLKAgehxDLxRJClwM+VMBvPNTn id2aBRbtSEYQfI2BDNxtwp9ZPn30SQEDfwdQGeT4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id AC0003858C74 for ; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AC0003858C74 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwM001624 for ; Thu, 18 Aug 2022 15:04:06 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-10 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:03 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 3AF513F7084; Thu, 18 Aug 2022 15:04:03 -0700 (PDT) To: Subject: [PATCH 07/10] [RISCV] Use a constraint for bset_mask and bset_1_mask Date: Thu, 18 Aug 2022 15:03:50 -0700 Message-ID: <1660860233-11175-8-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Nj8DroVizAVHYv03q6E-zuuyLHfd2Xhl X-Proofpoint-GUID: Nj8DroVizAVHYv03q6E-zuuyLHfd2Xhl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538542083900231?= X-GMAIL-MSGID: =?utf-8?q?1741538542083900231?= From: Andrew Pinski A constraint here just makes it easier to understand what the operands are. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with --with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64). Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/constraints.md (DsS): New constraint. (DsD): New constraint. * config/riscv/iterators.md (shiftm1c): New iterator. * config/riscv/bitmanip.md (*bset_mask): Use shiftm1c. (*bset_1_mask): Likewise. --- gcc/config/riscv/bitmanip.md | 4 ++-- gcc/config/riscv/constraints.md | 12 ++++++++++++ gcc/config/riscv/iterators.md | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 73a36f7751b..d362f526e79 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -273,7 +273,7 @@ (define_insn "*bset_mask" (ior:X (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 2 "register_operand" "r") - (match_operand 3 "" "i")) 0)) + (match_operand 3 "" "")) 0)) (match_operand:X 1 "register_operand" "r")))] "TARGET_ZBS" "bset\t%0,%1,%2" @@ -292,7 +292,7 @@ (define_insn "*bset_1_mask" (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "" "i")) 0)))] + (match_operand 2 "" "")) 0)))] "TARGET_ZBS" "bset\t%0,x0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 61b84875fd9..444870ad060 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -60,6 +60,18 @@ (define_constraint "Ds3" (and (match_code "const_int") (match_test "IN_RANGE (ival, 1, 3)"))) +(define_constraint "DsS" + "@internal + 31 immediate" + (and (match_code "const_int") + (match_test "ival == 31"))) + +(define_constraint "DsD" + "@internal + 63 immediate" + (and (match_code "const_int") + (match_test "ival == 63"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 6c8a6d2dd59..be0d5390307 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -115,6 +115,7 @@ (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) ; bitmanip mode attribute (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) +(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")]) ;; ------------------------------------------------------------------- ;; Code Iterators From patchwork Thu Aug 18 22:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 620 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp553487pxh; Thu, 18 Aug 2022 15:08:03 -0700 (PDT) X-Google-Smtp-Source: AA6agR5cGTVKrHqT1Lgd/6ctlYF0113742fLVzWKbcbPVcE7ah0pDZeQ8R3EKB3VTHXPQ9Lp49gV X-Received: by 2002:a17:907:1c24:b0:731:59f9:1b3f with SMTP id nc36-20020a1709071c2400b0073159f91b3fmr2934249ejc.595.1660860483269; Thu, 18 Aug 2022 15:08:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860483; cv=none; d=google.com; s=arc-20160816; b=c8dq5/tqJghZy9396KVj72D6pIZgKtCdieKX9sKNZCJIXSKPCYdAY17RH0VLCbXQiZ E0emaiKCZU1cNRygBU5QchedjI14HxaX+3/hB2h7DURmmXwCvzaVPrDTZAajz5W2KooF 4GabZgaQpN++yJNKiGP1/CnN/YpIOM5IdKT4QNq/n8H0zQOBa0OoAUAIxQavwnyhWRYb vLBKyFKjEI0emOyLxTVT1nc75Xny2sdHUrmQVQXN4L8kGADDxulcJ79HT6l5SV/8tdro +l47FyMmXHO2Qmlch28rPwxQKCNAoAN8XGCPVARVYo93sbjzBMdQutCjTUif1X8WqHNo zD0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=l7QsV/qgjjSoD6GUBUC9667rlV0nAGLJbAHoSAzIuiE=; b=hgFn4P9MsbnksX9GpfefAf5tw+EmsOSbJktBrYXpoCWIx4QMDQr9GAZbah+KuA+6gv 1d4dIc7/Zs6PmPm4lA8Z5JcO2B2+Vr8p9pef8dIOv9rATURrqIAPbp29VcmGB5qhNz+V F7D5HMtfRvj4ULUPiGAwXPPuV2aS7iR7vB15PHC3dFtFbu8Fjzi6FeAJOV+Ks08qwwKu M212uhqLmqV/CiUIsuGtncb1gTG3gnGtkQR/4eqx400NarKkE6bysKIgc3S1n4bqyhwK +2MdIht0SBSD4V+Zy/JW05ZrjxXYlICfjoydBRNT3JOmGbuDivmcj23pb4lPb5/F+mw9 3E5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=EiZOeVpr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id p7-20020a170906498700b00718d1cddac1si1784780eju.833.2022.08.18.15.08.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:08:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=EiZOeVpr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4D500385AC31 for ; Thu, 18 Aug 2022 22:07:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4D500385AC31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860426; bh=l7QsV/qgjjSoD6GUBUC9667rlV0nAGLJbAHoSAzIuiE=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=EiZOeVprNIc9jmqzWxDHBoezMw62G+TzNDYS9D9XFN19Sa25wPUBxeL72U3N32g6j Zm/9+RHVH6mxvm6ar2Xuc/RTO1Eq7PbcqU38comM0QS7MhdmRmtcS5IKeDJ/sq4RsL 3nC3iULHH1O8zMmfjmDKBWs7XkOz4fj/ARzqYrSc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id CB9503858C55 for ; Thu, 18 Aug 2022 22:04:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CB9503858C55 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqWrE002457 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wr-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 18 Aug 2022 15:04:03 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 8CA563F708E; Thu, 18 Aug 2022 15:04:03 -0700 (PDT) To: Subject: [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS Date: Thu, 18 Aug 2022 15:03:51 -0700 Message-ID: <1660860233-11175-9-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: koh_jubxXZK4Fmprx8j8l3_-BA-TfToI X-Proofpoint-GUID: koh_jubxXZK4Fmprx8j8l3_-BA-TfToI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538442124592860?= X-GMAIL-MSGID: =?utf-8?q?1741538442124592860?= From: Andrew Pinski The problem here is two fold. With RISCV32, 32bit const_int are always signed extended to 64bit in HWI. So that means for SINGLE_BIT_MASK_OPERAND, it should mask off the upper bits to see it is a single bit for !TARGET_64BIT. Plus there are a few locations which forget to call trunc_int_for_mode when generating a SImode constant so they are not sign extended correctly for HWI. The predicates single_bit_mask_operand and not_single_bit_mask_operand need get the same handling as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with --with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64. Thanks, Andrew Pinski gcc/ChangeLog: PR target/106586 * config/riscv/predicates.md (single_bit_mask_operand): Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi. (not_single_bit_mask_operand): Likewise. * config/riscv/riscv.cc (riscv_build_integer_1): Don't special case 1<<31 for 32bits as it is already handled. Call trunc_int_for_mode on the upper part after the subtraction. (riscv_move_integer): Call trunc_int_for_mode before generating the integer just make sure the constant has been sign extended corectly. (riscv_emit_int_compare): Call trunc_int_for_mode after doing the addition for the new rhs. * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT, then mask off the upper 32bits of the HWI as it will be sign extended. --- gcc/config/riscv/predicates.md | 4 ++-- gcc/config/riscv/riscv.cc | 12 +++++++++--- gcc/config/riscv/riscv.h | 4 +++- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 2af7f661d6f..862e72b0983 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -226,11 +226,11 @@ (define_special_predicate "gpr_save_operation" ;; Predicates for the ZBS extension. (define_predicate "single_bit_mask_operand" (and (match_code "const_int") - (match_test "pow2p_hwi (INTVAL (op))"))) + (match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))"))) (define_predicate "not_single_bit_mask_operand" (and (match_code "const_int") - (match_test "pow2p_hwi (~INTVAL (op))"))) + (match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))"))) (define_predicate "const31_operand" (and (match_code "const_int") diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 22d0f6d604c..026c69ce40d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -432,7 +432,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], sign-extended (negative) representation (-1 << 31) for the value, if we want to build (1 << 31) in SImode. This will then expand to an LUI instruction. */ - if (mode == SImode && value == (HOST_WIDE_INT_1U << 31)) + if (TARGET_64BIT && mode == SImode && value == (HOST_WIDE_INT_1U << 31)) codes[0].value = (HOST_WIDE_INT_M1U << 31); return 1; @@ -445,7 +445,11 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], && (mode != HImode || value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1))) { - alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode); + HOST_WIDE_INT upper_part = value - low_part; + if (mode != VOIDmode) + upper_part = trunc_int_for_mode (value - low_part, mode); + + alt_cost = 1 + riscv_build_integer_1 (alt_codes, upper_part, mode); if (alt_cost < cost) { alt_codes[alt_cost-1].code = PLUS; @@ -1550,6 +1554,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, x = riscv_split_integer (value, mode); else { + codes[0].value = trunc_int_for_mode (codes[0].value, mode); /* Apply each binary operation to X. */ x = GEN_INT (codes[0].value); @@ -1559,7 +1564,7 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, x = riscv_emit_set (temp, x); else x = force_reg (mode, x); - + codes[i].value = trunc_int_for_mode (codes[i].value, mode); x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); } } @@ -2651,6 +2656,7 @@ riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) continue; new_rhs = rhs + (increment ? 1 : -1); + new_rhs = trunc_int_for_mode (new_rhs, GET_MODE (*op0)); if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs) && (rhs < 0) == (new_rhs < 0)) { diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 4b07c5487c6..5394776eb50 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -535,7 +535,9 @@ enum reg_class /* If this is a single bit mask, then we can load it with bseti. Special handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ #define SINGLE_BIT_MASK_OPERAND(VALUE) \ - (pow2p_hwi (VALUE)) + (pow2p_hwi (TARGET_64BIT \ + ? (VALUE) \ + : ((VALUE) & ((HOST_WIDE_INT_1U << 32)-1)))) /* Stack layout; function entry, exit and calling. */ From patchwork Thu Aug 18 22:03:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 621 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp553859pxh; Thu, 18 Aug 2022 15:08:38 -0700 (PDT) X-Google-Smtp-Source: AA6agR7gl92zQ8KQFCO5SxvBljEh08UKH2Cn/aI5k4L9qXmQL2ovwnWSUpo4nH8yvFwn6vVxwAdn X-Received: by 2002:a05:6402:331f:b0:43d:931c:6945 with SMTP id e31-20020a056402331f00b0043d931c6945mr3703118eda.199.1660860518540; Thu, 18 Aug 2022 15:08:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860518; cv=none; d=google.com; s=arc-20160816; b=NX+D6Cp9AQ1s9nOgmUwzGKWkzQuxfvZn14Sk0ns7pWbE4+iuduGcwPcLYKsdVmgfTM Xrz4NUiQHcHD377/0FETDx2XOLonThUM/MioN4f9uKTnf9ieBJKvG/tYfh9IGaYykVO3 /rqSYTF8bIXakys/ARrj5f9hv2Xr2vB+g/RkCUUP1ajoSYALZUS5ihvznmacvbVy20kx VNhKNodIHoIkBJDtD72UoACD1YxSkKUE3pGZtaDv4ICH5CJvMw8q+TpfqbII+g8chr+0 50s6qbnrfP+IU/nEKHZDb8HKaYL2IeUE2cEp0mZ1ouyJPOGrJ0vVA6sme7amV1OShQcd 7I0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=Eexnxyy9z0qNs6hddeIdUoGcptcCPl7bNtR+qX9kk1U=; b=DUJA//bQIpONFlZ6tFfxB0rxcFfVx7o0Q7CDeL1G4DZJ8VcYXaajnzbExRVXBKh8aw taavXDJDvjv0tvKHGxrkupeWXQWSSpo4zkt4PBYRyP8NFiNMsS6MTBlqlMNnxJl3hqxN T8++fsghgI/MXo9YRO54y8WGtLZWN71mu+mOxGicuZni+cOPkPtwYFUmJuIQ8hkbIW2R s4xYvcYc6Ii8Yv+dz5UQJigiBgLhcnPqyKQhZV+0GJWD1Nvlze8N/6aNj5qlENJ0EI7M 7WNA14Q6T8a42HHgGSfpwYcYTx2mSJtD0ri0MjCA9l/HhidPZU2NXwkVVEk6dS/LHU3N HuNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="LG/3UO0e"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id qa20-20020a170907869400b007311b7d141dsi1808560ejc.595.2022.08.18.15.08.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:08:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="LG/3UO0e"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D0C0D385695E for ; Thu, 18 Aug 2022 22:07:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D0C0D385695E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860458; bh=Eexnxyy9z0qNs6hddeIdUoGcptcCPl7bNtR+qX9kk1U=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=LG/3UO0e2i+ooQwd+av2CbD0euvtFnNqkcSCJVEl1m6u7Ey8XUDcUch+h0Q3A9af9 yK6ggqrSkOFL1+qjism/D1BeoBqbfUuHX/cY3NBojjwqyAWKC2w55fGBsXZKkElpzr 0rLJXL4BkhZmfeAJG5ykIjeSjAcS6CcMQ44aALaQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 54B2E385842F for ; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 54B2E385842F Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqWrG002457 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wr-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:04 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id E4E693F7062; Thu, 18 Aug 2022 15:04:03 -0700 (PDT) To: Subject: [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand Date: Thu, 18 Aug 2022 15:03:52 -0700 Message-ID: <1660860233-11175-10-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: o57fkh2yvT55KNiR2RGWOKjD7d2eyxpP X-Proofpoint-GUID: o57fkh2yvT55KNiR2RGWOKjD7d2eyxpP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538479415991466?= X-GMAIL-MSGID: =?utf-8?q?1741538479415991466?= From: Andrew Pinski Like a previous patch, just add constraints for predicates not_single_bit_mask_operand and single_bit_mask_operand. OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/constraints.md (DbS): New constraint. (DnS): New constraint. * config/riscv/bitmanip.md (*bset_1_mask): Use new constraint. (*bclr): Likewise. (*binvi): Likewise. --- gcc/config/riscv/bitmanip.md | 6 +++--- gcc/config/riscv/constraints.md | 10 ++++++++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d362f526e79..026299d6703 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -300,7 +300,7 @@ (define_insn "*bset_1_mask" (define_insn "*bseti" [(set (match_operand:X 0 "register_operand" "=r") (ior:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "single_bit_mask_operand" "i")))] + (match_operand:X 2 "single_bit_mask_operand" "DbS")))] "TARGET_ZBS" "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) @@ -317,7 +317,7 @@ (define_insn "*bclr" (define_insn "*bclri" [(set (match_operand:X 0 "register_operand" "=r") (and:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "not_single_bit_mask_operand" "i")))] + (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))] "TARGET_ZBS" "bclri\t%0,%1,%T2" [(set_attr "type" "bitmanip")]) @@ -334,7 +334,7 @@ (define_insn "*binv" (define_insn "*binvi" [(set (match_operand:X 0 "register_operand" "=r") (xor:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "single_bit_mask_operand" "i")))] + (match_operand:X 2 "single_bit_mask_operand" "DbS")))] "TARGET_ZBS" "binvi\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 444870ad060..2873d533cb5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -72,6 +72,16 @@ (define_constraint "DsD" (and (match_code "const_int") (match_test "ival == 63"))) +(define_constraint "DbS" + "@internal" + (and (match_code "const_int") + (match_test "SINGLE_BIT_MASK_OPERAND (ival)"))) + +(define_constraint "DnS" + "@internal" + (and (match_code "const_int") + (match_test "SINGLE_BIT_MASK_OPERAND (~ival)"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" From patchwork Thu Aug 18 22:03:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 622 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6a10:38f:b0:2d5:3c95:9e21 with SMTP id 15csp554107pxh; Thu, 18 Aug 2022 15:09:04 -0700 (PDT) X-Google-Smtp-Source: AA6agR5WXEZ0pUx9uwsPdPUA22t/IWWTJO9g+uuMdnlLjsfDo/rSXIc+TMQEQMO24g/GiDC3JGTg X-Received: by 2002:a17:907:9810:b0:73c:37bb:c4db with SMTP id ji16-20020a170907981000b0073c37bbc4dbmr1855322ejc.79.1660860543980; Thu, 18 Aug 2022 15:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660860543; cv=none; d=google.com; s=arc-20160816; b=pm9JKo+jHux2vdWWc73A19JoqzW32glBoFPqUrw0ALUQdIomDnvHUwyPaUSb7Sfuir aAxvR9e/Dc6gnjwPnGQfeTK6ZdV9pjkJK4cOEUCEDsKT9Ms4rDbblH4wF26BS/YOz57N P/PwCaB4w8i6JONnvYdwjUs5teb1fUqH1VCYAs9fDFbsp9o8UvlBnkZOYGy7E7M2qTDY x6KilUNzv43VO3hLaQ1PAi3Xt0YewKO2nJWdRRRLAWJJVbSau1sVppg1LM7y2U2fHZGD 7ykrYinrGn3Ex6OWAXJkaxOM9pGVwz/X3tP1PRNDcsZIL24HgplZLLFJUnJbBrpL5Akm M8Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:references:in-reply-to:message-id:date:subject:to :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=dMXZcIuSX5tUsXJmdzAbwh6nG2+RoH1xqW6QcNDu4vo=; b=Fi2meKyJtH6zqdnO9fIAO7l0HlMqHv7ZwMejdwLAibdV0O0G+v9q1BQvDDrVUsUkQv oiQ1suC/NnvukP0A3BEx3XbRyBTo7nDnZldNeLyqnUbSdc/fLLkl54EFf+ee/Mwv01JN rm12wiV2MJ0k2uPsAuqcW6JnRdIehB3wxrLzI1xUo4WjGHJMNpfIWHDMOvXURBCaxxxZ D7nVzjeudVZ0edishVqQoCiFjjf6OqGQToMiWJA2MzlI5/xHXrL9tV0J5EgUtKTjJlJu RY6lOZ0wlqgUwEGQq6qEcp0qlIemVG6hIc9wedxPfiauUR8U5NiXuaqFtOOWH6JJQVOi eKtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="ncppS/T3"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f23-20020a170906495700b00731745a7f05si1607415ejt.275.2022.08.18.15.09.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="ncppS/T3"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 285E93857BBE for ; Thu, 18 Aug 2022 22:08:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 285E93857BBE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860483; bh=dMXZcIuSX5tUsXJmdzAbwh6nG2+RoH1xqW6QcNDu4vo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=ncppS/T3iwyAE1thkiqDNk9SvPwLEf2Doq+U87g5a5DruAMSjTvlEEGFIkbaF8gX6 dvxIdyzViboTX/ZKatzFo79CM5dlQ1uMq9sXRiPhMXq6+6l3ey4rnnQfQcDlPsZRYy ZfaL7Um+PlDictUo/GAAr9r/m5oHAgXEntlkb9pc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 9E1E438582A2 for ; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9E1E438582A2 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqWrH002457 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wr-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:04 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 41F0B3F7080; Thu, 18 Aug 2022 15:04:04 -0700 (PDT) To: Subject: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md Date: Thu, 18 Aug 2022 15:03:53 -0700 Message-ID: <1660860233-11175-11-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: khEe3rJrtfgJ71rnKBaFx3wM7fEl93ng X-Proofpoint-GUID: khEe3rJrtfgJ71rnKBaFx3wM7fEl93ng X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538505591768670?= X-GMAIL-MSGID: =?utf-8?q?1741538505591768670?= From: Andrew Pinski The constraints should be n instead of i. Also there needs to a check for out of bounds zero_extract for *bexti. gcc/ChangeLog: PR target/106632 PR target/106588 * config/riscv/bitmanip.md (*shNadduw): Use n constraint instead of i. (*slliuw): Likewise. (*bexti): Likewise. Also add a check for operands[2] to be less than the mode bitsize. --- gcc/config/riscv/bitmanip.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 026299d6703..ecf5b51b533 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -44,7 +44,7 @@ (define_insn "*shNadduw" (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "imm123_operand" "Ds3")) - (match_operand 3 "immediate_operand" "")) + (match_operand 3 "immediate_operand" "n")) (match_operand:DI 4 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" @@ -110,7 +110,7 @@ (define_insn "*slliuw" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" "")))] + (match_operand 3 "immediate_operand" "n")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" "slli.uw\t%0,%1,%2" @@ -354,6 +354,7 @@ (define_insn "*bexti" (zero_extract:X (match_operand:X 1 "register_operand" "r") (const_int 1) (match_operand 2 "immediate_operand" "i")))] - "TARGET_ZBS" + (match_operand 2 "immediate_operand" "n")))] + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")])