From patchwork Thu Aug 10 05:09:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 133691 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp192499vqi; Wed, 9 Aug 2023 22:11:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIo//rjAqaLt1PE8fG5ZAgiwH7iwvM6Sgy6kvZUxqPWPfZrUzBotmGr+nelMxYoUWK54DT X-Received: by 2002:a17:906:51c9:b0:997:caf0:9945 with SMTP id v9-20020a17090651c900b00997caf09945mr1186728ejk.12.1691644293291; Wed, 09 Aug 2023 22:11:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691644293; cv=none; d=google.com; s=arc-20160816; b=QiqkCRnow0OT8imD2xghNVXSVplXbDHRV5UikSN5XEULcyQPeCO39zbP0gjHAyvHKZ 9xWU9pFwAezI2xV9Zxde4pSFlxFjwLugSqN/tLKIiI4Vclms4Ca1B0fkfu+BhTAchGm7 7GvSfCXSl+8lZapsmOQVUZSc/TfxIYukmjeX6TjLnZjC4SRFamKNn7R5yz7RBcrrHtTe TTAhWSzUaCQPvkRcenZJHj8OuyEgOvWzvsp0nPLZoojM0CkkiL3aPZNd5DneLQO1X5yT YQCZlvf8jian1g9fwpMcdbgkjgujcyuBG9u+ZPDitdBxHfJvgDXVex+mBGL5iysbkN6Z ahyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=5Xbtj3VNXKB9/YPFwNSygBDVwAvQE0Rq2oUdTf7dWyo=; fh=PmVSnvRlVeKkg+dPKzMCyvykdI2+tUdRpMZVt54Vt9k=; b=N71qJZELxVWcFs3fGSAceZBMiytb2QBXb2bCvYjmIYMkY8W3fZhTPQ/pu9UsbJYwBa LBKFOdBEHPjdcqo1JZv8nWr8U/PJ5hq31FQnvu9tVCDU1Otll18lkQjKJZGkEoa+2L0J E8SWOI1X+dgu+0fSr+OlXya2oH2iApyZZlCnkTYEhyIlRQO/E1Nkf8L/C5PPCvpqhAYk qfm6Em01weq/ctR26ETugHi5zHnSziCYRGlhQnXR9PfEyi80CUBqbtOSji1TGYpu5a3U mpa6qyjsgGQJudaKU+kmvGNSvUnEy6THSFw9crs309+yu49s7p6xs8fa5uhwxEUura9z y0jA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=XZN32Rna; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id mc11-20020a170906eb4b00b0099cb798de6esi780534ejb.135.2023.08.09.22.11.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 22:11:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=XZN32Rna; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0102B3858298 for ; Thu, 10 Aug 2023 05:11:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0102B3858298 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691644292; bh=5Xbtj3VNXKB9/YPFwNSygBDVwAvQE0Rq2oUdTf7dWyo=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=XZN32RnatsDcjCUJ000dt9nx2VzxQduCmi4M+V0qO28QyoJtbRwCRu4Uf1iDd/duI EWyD9f7YUDepbrl6qNQ8OJgbjykzVA/Qpf2u3EshRnRdNTVoaGlwsumNc1GwKFkru9 U3QPgEjSKXL7lhLLDDw1shVRiE+vgP8gXmVG3isc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id CE1C93858D20 for ; Thu, 10 Aug 2023 05:10:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE1C93858D20 Received: from mgamail.intel.com ([134.134.136.126]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTxwa-0000g2-QZ for gcc-patches@gcc.gnu.org; Thu, 10 Aug 2023 01:10:47 -0400 X-IronPort-AV: E=McAfee;i="6600,9927,10797"; a="356267102" X-IronPort-AV: E=Sophos;i="6.01,161,1684825200"; d="scan'208";a="356267102" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2023 22:09:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10797"; a="735269331" X-IronPort-AV: E=Sophos;i="6.01,161,1684825200"; d="scan'208";a="735269331" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 09 Aug 2023 22:09:43 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id CA9611006F27; Thu, 10 Aug 2023 13:09:42 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFMACC rounding mode intrinsic API Date: Thu, 10 Aug 2023 13:09:40 +0800 Message-Id: <20230810050940.3694097-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.126; envelope-from=pan2.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773817606497551095 X-GMAIL-MSGID: 1773817606497551095 From: Pan Li This patch would like to support the rounding mode API for the VFMACC for the below samples. * __riscv_vfmacc_vv_f32m1_rm * __riscv_vfmacc_vv_f32m1_rm_m * __riscv_vfmacc_vf_f32m1_rm * __riscv_vfmacc_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmacc_frm): New class for vfmacc frm. (vfmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmacc_frm): New function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-macc.c: New test. Signed-off-by: Pan Li --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 3 ++ .../riscv/rvv/base/float-point-macc.c | 47 +++++++++++++++++++ 4 files changed, 76 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index afe3735f5ee..1695d77e8bd 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -356,6 +356,29 @@ public: } }; +/* Implements below instructions for frm + - vfmacc +*/ +class vfmacc_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn (true, + code_for_pred_mul_scalar (PLUS, + e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn (true, + code_for_pred_mul (PLUS, e.vector_mode ())); + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2116,6 +2139,7 @@ static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj; static CONSTEXPR const widen_binop vfwmul_obj; static CONSTEXPR const widen_binop_frm vfwmul_frm_obj; static CONSTEXPR const vfmacc vfmacc_obj; +static CONSTEXPR const vfmacc_frm vfmacc_frm_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; static CONSTEXPR const vfmadd vfmadd_obj; static CONSTEXPR const vfnmsub vfnmsub_obj; @@ -2351,6 +2375,7 @@ BASE (vfrdiv_frm) BASE (vfwmul) BASE (vfwmul_frm) BASE (vfmacc) +BASE (vfmacc_frm) BASE (vfnmsac) BASE (vfmadd) BASE (vfnmsub) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 2d2b52a312c..67d18412b4c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -160,6 +160,7 @@ extern const function_base *const vfrdiv_frm; extern const function_base *const vfwmul; extern const function_base *const vfwmul_frm; extern const function_base *const vfmacc; +extern const function_base *const vfmacc_frm; extern const function_base *const vfnmsac; extern const function_base *const vfmadd; extern const function_base *const vfnmsub; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index d43b33ded17..92ecf8a9065 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -349,6 +349,9 @@ DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvfv_ops) DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops) DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops) +DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops) +DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops) + // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwfv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c new file mode 100644 index 00000000000..df29f4d240f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_rm (vd, op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmacc_vf_f32m1_rm (vd, op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmacc_vv_f32m1 (vd, op1, op2, vl); +} + +vfloat32m1_t +test_vfmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfmacc_vv_f32m1_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */